arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2
   3 /*
   4  * Device tree file for ZII's SSMB SPU3 board
   5  *
   6  * SSMB - SPU3 Switch Management Board
   7  * SPU - Seat Power Unit
   8  *
   9  * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
  10  *
  11  * Based on an original 'vf610-twr.dts' which is Copyright 2015,
  12  * Freescale Semiconductor, Inc.
  13  */
  14
  15 /dts-v1/;
  16 #include "vf610.dtsi"
  17
  18 / {
  19         model = "ZII VF610 SSMB SPU3 Board";
  20         compatible = "zii,vf610spu3", "zii,vf610dev", "fsl,vf610";
  21
  22         chosen {
  23                 stdout-path = &uart0;
  24         };
  25
  26         memory@80000000 {
  27                 reg = <0x80000000 0x20000000>;
  28         };
  29
  30         gpio-leds {
  31                 compatible = "gpio-leds";
  32                 pinctrl-0 = <&pinctrl_leds_debug>;
  33                 pinctrl-names = "default";
  34
  35                 led-debug {
  36                         label = "zii:green:debug1";
  37                         gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
  38                         linux,default-trigger = "heartbeat";
  39                         max-brightness = <1>;
  40                 };
  41         };
  42
  43         reg_vcc_3v3_mcu: regulator {
  44                 compatible = "regulator-fixed";
  45                 regulator-name = "vcc_3v3_mcu";
  46                 regulator-min-microvolt = <3300000>;
  47                 regulator-max-microvolt = <3300000>;
  48         };
  49 };
  50
  51 &adc0 {
  52         vref-supply = <&reg_vcc_3v3_mcu>;
  53         status = "okay";
  54 };
  55
  56 &adc1 {
  57         vref-supply = <&reg_vcc_3v3_mcu>;
  58         status = "okay";
  59 };
  60
  61 &dspi1 {
  62         bus-num = <1>;
  63         pinctrl-names = "default";
  64         pinctrl-0 = <&pinctrl_dspi1>;
  65         /*
  66          * Some SPU3s come with SPI-NOR chip DNPed, so we leave this
  67          * node disabled by default and rely on bootloader to enable
  68          * it when appropriate.
  69          */
  70         status = "disabled";
  71
  72         m25p128@0 {
  73                 #address-cells = <1>;
  74                 #size-cells = <1>;
  75                 compatible = "m25p128", "jedec,spi-nor";
  76                 reg = <0>;
  77                 spi-max-frequency = <50000000>;
  78
  79                 partition@0 {
  80                         label = "m25p128-0";
  81                         reg = <0x0 0x01000000>;
  82                 };
  83         };
  84 };
  85
  86 &edma0 {
  87         status = "okay";
  88 };
  89
  90 &edma1 {
  91         status = "okay";
  92 };
  93
  94 &esdhc0 {
  95         pinctrl-names = "default";
  96         pinctrl-0 = <&pinctrl_esdhc0>;
  97         bus-width = <8>;
  98         non-removable;
  99         no-1-8-v;
 100         keep-power-in-suspend;
 101         status = "okay";
 102 };
 103
 104 &esdhc1 {
 105         pinctrl-names = "default";
 106         pinctrl-0 = <&pinctrl_esdhc1>;
 107         bus-width = <4>;
 108         status = "okay";
 109 };
 110
 111 &fec1 {
 112         phy-mode = "rmii";
 113         pinctrl-names = "default";
 114         pinctrl-0 = <&pinctrl_fec1>;
 115         status = "okay";
 116
 117         fixed-link {
 118                 speed = <100>;
 119                 full-duplex;
 120         };
 121
 122         mdio1: mdio {
 123                 #address-cells = <1>;
 124                 #size-cells = <0>;
 125                 status = "okay";
 126
 127                 switch0: switch0@0 {
 128                         compatible = "marvell,mv88e6190";
 129                         pinctrl-0 = <&pinctrl_gpio_switch0>;
 130                         pinctrl-names = "default";
 131                         reg = <0>;
 132                         eeprom-length = <65536>;
 133                         reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
 134                         interrupt-parent = <&gpio3>;
 135                         interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
 136                         interrupt-controller;
 137                         #interrupt-cells = <2>;
 138
 139                         ports {
 140                                 #address-cells = <1>;
 141                                 #size-cells = <0>;
 142
 143                                 port@0 {
 144                                         reg = <0>;
 145                                         label = "cpu";
 146                                         ethernet = <&fec1>;
 147
 148                                         fixed-link {
 149                                                 speed = <100>;
 150                                                 full-duplex;
 151                                         };
 152                                 };
 153
 154                                 port@1 {
 155                                         reg = <1>;
 156                                         label = "eth_cu_1000_1";
 157                                 };
 158
 159                                 port@2 {
 160                                         reg = <2>;
 161                                         label = "eth_cu_1000_2";
 162                                 };
 163
 164                                 port@3 {
 165                                         reg = <3>;
 166                                         label = "eth_cu_1000_3";
 167                                 };
 168
 169                                 port@4 {
 170                                         reg = <4>;
 171                                         label = "eth_cu_1000_4";
 172                                 };
 173
 174                                 port@5 {
 175                                         reg = <5>;
 176                                         label = "eth_cu_1000_5";
 177                                 };
 178
 179                                 port@6 {
 180                                         reg = <6>;
 181                                         label = "eth_cu_1000_6";
 182                                 };
 183                         };
 184                 };
 185         };
 186 };
 187
 188 &i2c0 {
 189         clock-frequency = <100000>;
 190         pinctrl-names = "default";
 191         pinctrl-0 = <&pinctrl_i2c0>;
 192         status = "okay";
 193
 194         gpio6: pca9505@22 {
 195                 compatible = "nxp,pca9554";
 196                 reg = <0x22>;
 197                 gpio-controller;
 198                 #gpio-cells = <2>;
 199         };
 200
 201         lm75@48 {
 202                 compatible = "national,lm75";
 203                 reg = <0x48>;
 204         };
 205
 206         at24c04@50 {
 207                 compatible = "atmel,24c04";
 208                 reg = <0x50>;
 209                 label = "nameplate";
 210         };
 211
 212         at24c04@52 {
 213                 compatible = "atmel,24c04";
 214                 reg = <0x52>;
 215         };
 216 };
 217
 218 &uart0 {
 219         pinctrl-names = "default";
 220         pinctrl-0 = <&pinctrl_uart0>;
 221         status = "okay";
 222 };
 223
 224 &uart1 {
 225         pinctrl-names = "default";
 226         pinctrl-0 = <&pinctrl_uart1>;
 227         status = "okay";
 228
 229         rave-sp {
 230                 compatible = "zii,rave-sp-rdu2";
 231                 current-speed = <1000000>;
 232                 #address-cells = <1>;
 233                 #size-cells = <1>;
 234
 235                 watchdog {
 236                         compatible = "zii,rave-sp-watchdog";
 237                 };
 238
 239                 eeprom@a3 {
 240                         compatible = "zii,rave-sp-eeprom";
 241                         reg = <0xa3 0x4000>;
 242                         #address-cells = <1>;
 243                         #size-cells = <1>;
 244                         zii,eeprom-name = "main-eeprom";
 245                 };
 246         };
 247 };
 248
 249 &iomuxc {
 250         pinctrl_dspi1: dspi1grp {
 251                 fsl,pins = <
 252                         VF610_PAD_PTD5__DSPI1_CS0               0x1182
 253                         VF610_PAD_PTD4__DSPI1_CS1               0x1182
 254                         VF610_PAD_PTC6__DSPI1_SIN               0x1181
 255                         VF610_PAD_PTC7__DSPI1_SOUT              0x1182
 256                         VF610_PAD_PTC8__DSPI1_SCK               0x1182
 257                 >;
 258         };
 259
 260         pinctrl_esdhc0: esdhc0grp {
 261                 fsl,pins = <
 262                         VF610_PAD_PTC0__ESDHC0_CLK              0x31ef
 263                         VF610_PAD_PTC1__ESDHC0_CMD              0x31ef
 264                         VF610_PAD_PTC2__ESDHC0_DAT0             0x31ef
 265                         VF610_PAD_PTC3__ESDHC0_DAT1             0x31ef
 266                         VF610_PAD_PTC4__ESDHC0_DAT2             0x31ef
 267                         VF610_PAD_PTC5__ESDHC0_DAT3             0x31ef
 268                         VF610_PAD_PTD23__ESDHC0_DAT4            0x31ef
 269                         VF610_PAD_PTD22__ESDHC0_DAT5            0x31ef
 270                         VF610_PAD_PTD21__ESDHC0_DAT6            0x31ef
 271                         VF610_PAD_PTD20__ESDHC0_DAT7            0x31ef
 272                 >;
 273         };
 274
 275         pinctrl_esdhc1: esdhc1grp {
 276                 fsl,pins = <
 277                         VF610_PAD_PTA24__ESDHC1_CLK             0x31ef
 278                         VF610_PAD_PTA25__ESDHC1_CMD             0x31ef
 279                         VF610_PAD_PTA26__ESDHC1_DAT0            0x31ef
 280                         VF610_PAD_PTA27__ESDHC1_DAT1            0x31ef
 281                         VF610_PAD_PTA28__ESDHC1_DATA2           0x31ef
 282                         VF610_PAD_PTA29__ESDHC1_DAT3            0x31ef
 283                 >;
 284         };
 285
 286         pinctrl_fec1: fec1grp {
 287                 fsl,pins = <
 288                         VF610_PAD_PTA6__RMII_CLKIN              0x30d1
 289                         VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
 290                         VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
 291                         VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
 292                         VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30d1
 293                         VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
 294                         VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
 295                         VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
 296                         VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
 297                         VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
 298                 >;
 299         };
 300
 301         pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
 302                 fsl,pins = <
 303                         VF610_PAD_PTE2__GPIO_107                0x31c2
 304                         VF610_PAD_PTB28__GPIO_98                0x219d
 305                 >;
 306         };
 307
 308         pinctrl_i2c0: i2c0grp {
 309                 fsl,pins = <
 310                         VF610_PAD_PTB14__I2C0_SCL               0x37ff
 311                         VF610_PAD_PTB15__I2C0_SDA               0x37ff
 312                 >;
 313         };
 314
 315         pinctrl_i2c1: i2c1grp {
 316                 fsl,pins = <
 317                         VF610_PAD_PTB16__I2C1_SCL               0x37ff
 318                         VF610_PAD_PTB17__I2C1_SDA               0x37ff
 319                 >;
 320         };
 321
 322         pinctrl_leds_debug: pinctrl-leds-debug {
 323                 fsl,pins = <
 324                         VF610_PAD_PTD3__GPIO_82                 0x31c2
 325                 >;
 326         };
 327
 328         pinctrl_uart0: uart0grp {
 329                 fsl,pins = <
 330                         VF610_PAD_PTB10__UART0_TX               0x21a2
 331                         VF610_PAD_PTB11__UART0_RX               0x21a1
 332                 >;
 333         };
 334
 335         pinctrl_uart1: uart1grp {
 336                 fsl,pins = <
 337                         VF610_PAD_PTB23__UART1_TX               0x21a2
 338                         VF610_PAD_PTB24__UART1_RX               0x21a1
 339                 >;
 340         };
 341 };