1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
7 #include "vf610-zii-dev.dtsi"
10 model = "ZII VF610 Development Board, Rev B";
11 compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610";
14 compatible = "mdio-mux-gpio";
15 pinctrl-0 = <&pinctrl_mdio_mux>;
16 pinctrl-names = "default";
17 gpios = <&gpio0 8 GPIO_ACTIVE_HIGH
18 &gpio0 9 GPIO_ACTIVE_HIGH
19 &gpio0 24 GPIO_ACTIVE_HIGH
20 &gpio0 25 GPIO_ACTIVE_HIGH>;
21 mdio-parent-bus = <&mdio1>;
31 compatible = "marvell,mv88e6085";
32 pinctrl-0 = <&pinctrl_gpio_switch0>;
33 pinctrl-names = "default";
36 interrupt-parent = <&gpio0>;
37 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
39 #interrupt-cells = <2>;
40 eeprom-length = <512>;
49 phy-handle = <&switch0phy0>;
55 phy-handle = <&switch0phy1>;
61 phy-handle = <&switch0phy2>;
64 switch0port5: port@5 {
67 phy-mode = "rgmii-txid";
90 switch0phy0: switch0phy0@0 {
92 interrupt-parent = <&switch0>;
93 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
95 switch0phy1: switch1phy0@1 {
97 interrupt-parent = <&switch0>;
98 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
100 switch0phy2: switch1phy0@2 {
102 interrupt-parent = <&switch0>;
103 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
111 #address-cells = <1>;
115 compatible = "marvell,mv88e6085";
116 pinctrl-0 = <&pinctrl_gpio_switch1>;
117 pinctrl-names = "default";
120 interrupt-parent = <&gpio0>;
121 interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
122 interrupt-controller;
123 #interrupt-cells = <2>;
124 eeprom-length = <512>;
127 #address-cells = <1>;
133 phy-handle = <&switch1phy0>;
139 phy-handle = <&switch1phy1>;
145 phy-handle = <&switch1phy2>;
148 switch1port5: port@5 {
151 link = <&switch2port9>;
152 phy-mode = "rgmii-txid";
160 switch1port6: port@6 {
163 phy-mode = "rgmii-txid";
164 link = <&switch0port5>;
172 #address-cells = <1>;
175 switch1phy0: switch1phy0@0 {
177 interrupt-parent = <&switch1>;
178 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
181 switch1phy1: switch1phy0@1 {
183 interrupt-parent = <&switch1>;
184 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
187 switch1phy2: switch1phy0@2 {
189 interrupt-parent = <&switch1>;
190 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
197 #address-cells = <1>;
202 compatible = "marvell,mv88e6085";
207 #address-cells = <1>;
213 phy-handle = <&switch2phy0>;
219 phy-handle = <&switch2phy1>;
225 phy-handle = <&switch2phy2>;
235 link-gpios = <&gpio6 2
247 link-gpios = <&gpio6 3
252 switch2port9: port@9 {
255 phy-mode = "rgmii-txid";
256 link = <&switch1port5
266 #address-cells = <1>;
284 #address-cells = <1>;
290 compatible = "spi-gpio";
291 pinctrl-0 = <&pinctrl_gpio_spi0>;
292 pinctrl-names = "default";
293 #address-cells = <1>;
295 gpio-sck = <&gpio1 12 GPIO_ACTIVE_HIGH>;
296 gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>;
297 gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>;
298 cs-gpios = <&gpio1 9 GPIO_ACTIVE_LOW
299 &gpio1 8 GPIO_ACTIVE_HIGH>;
300 num-chipselects = <2>;
303 compatible = "m25p128", "jedec,spi-nor";
304 #address-cells = <1>;
307 spi-max-frequency = <1000000>;
311 compatible = "atmel,at93c46d";
312 pinctrl-0 = <&pinctrl_gpio_e6185_eeprom_sel>;
313 pinctrl-names = "default";
315 spi-max-frequency = <500000>;
318 select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
324 gpio5: io-expander@20 {
325 compatible = "nxp,pca9554";
332 gpio6: io-expander@22 {
333 compatible = "nxp,pca9554";
334 pinctrl-names = "default";
335 pinctrl-0 = <&pinctrl_pca9554_22>;
339 interrupt-controller;
340 interrupt-parent = <&gpio3>;
341 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
347 compatible = "nxp,pca9548";
348 pinctrl-0 = <&pinctrl_i2c_mux_reset>;
349 pinctrl-names = "default";
350 #address-cells = <1>;
353 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
356 #address-cells = <1>;
361 compatible = "atmel,24c02";
367 #address-cells = <1>;
372 compatible = "atmel,24c02";
378 #address-cells = <1>;
383 compatible = "atmel,24c02";
389 #address-cells = <1>;
394 compatible = "atmel,24c02";
400 #address-cells = <1>;
408 clock-frequency = <5000000>;
412 pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 {
414 VF610_PAD_PTE27__GPIO_132 0x33e2
418 pinctrl_gpio_spi0: pinctrl-gpio-spi0 {
420 VF610_PAD_PTB22__GPIO_44 0x33e2
421 VF610_PAD_PTB21__GPIO_43 0x33e2
422 VF610_PAD_PTB20__GPIO_42 0x33e1
423 VF610_PAD_PTB19__GPIO_41 0x33e2
424 VF610_PAD_PTB18__GPIO_40 0x33e2
428 pinctrl_mdio_mux: pinctrl-mdio-mux {
430 VF610_PAD_PTA18__GPIO_8 0x31c2
431 VF610_PAD_PTA19__GPIO_9 0x31c2
432 VF610_PAD_PTB2__GPIO_24 0x31c2
433 VF610_PAD_PTB3__GPIO_25 0x31c2
437 pinctrl_pca9554_22: pinctrl-pca95540-22 {
439 VF610_PAD_PTB28__GPIO_98 0x219d