arch/arm/boot/dts/vf610-cosmic.dts

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  * Copyright 2013 Linaro Limited
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  */
  10
  11 /dts-v1/;
  12 #include "vf610.dtsi"
  13
  14 / {
  15         model = "PHYTEC Cosmic/Cosmic+ Board";
  16         compatible = "phytec,vf610-cosmic", "fsl,vf610";
  17
  18         chosen {
  19                 bootargs = "console=ttyLP1,115200";
  20         };
  21
  22         memory@80000000 {
  23                 reg = <0x80000000 0x10000000>;
  24         };
  25
  26         enet_ext: enet_ext {
  27                 compatible = "fixed-clock";
  28                 #clock-cells = <0>;
  29                 clock-frequency = <50000000>;
  30         };
  31 };
  32
  33 &clks {
  34         clocks = <&sxosc>, <&fxosc>, <&enet_ext>;
  35         clock-names = "sxosc", "fxosc", "enet_ext";
  36 };
  37
  38 &esdhc1 {
  39         pinctrl-names = "default";
  40         pinctrl-0 = <&pinctrl_esdhc1>;
  41         bus-width = <4>;
  42         status = "okay";
  43 };
  44
  45 &fec1 {
  46         phy-mode = "rmii";
  47         pinctrl-names = "default";
  48         pinctrl-0 = <&pinctrl_fec1>;
  49         status = "okay";
  50 };
  51
  52 &iomuxc {
  53         vf610-cosmic {
  54                 pinctrl_esdhc1: esdhc1grp {
  55                         fsl,pins = <
  56                                 VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
  57                                 VF610_PAD_PTA25__ESDHC1_CMD     0x31ef
  58                                 VF610_PAD_PTA26__ESDHC1_DAT0    0x31ef
  59                                 VF610_PAD_PTA27__ESDHC1_DAT1    0x31ef
  60                                 VF610_PAD_PTA28__ESDHC1_DATA2   0x31ef
  61                                 VF610_PAD_PTA29__ESDHC1_DAT3    0x31ef
  62                                 VF610_PAD_PTB28__GPIO_98        0x219d
  63                         >;
  64                 };
  65
  66                 pinctrl_fec1: fec1grp {
  67                         fsl,pins = <
  68                                 VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
  69                                 VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
  70                                 VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
  71                                 VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30d1
  72                                 VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
  73                                 VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
  74                                 VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
  75                                 VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
  76                                 VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
  77                         >;
  78                 };
  79
  80                 pinctrl_uart1: uart1grp {
  81                         fsl,pins = <
  82                                 VF610_PAD_PTB4__UART1_TX                0x21a2
  83                                 VF610_PAD_PTB5__UART1_RX                0x21a1
  84                         >;
  85                 };
  86         };
  87 };
  88
  89 &uart1 {
  90         pinctrl-names = "default";
  91         pinctrl-0 = <&pinctrl_uart1>;
  92         status = "okay";
  93 };