1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
11 model = "Liebherr BK4 controller";
12 compatible = "lwn,bk4", "fsl,vf610";
19 device_type = "memory";
20 reg = <0x80000000 0x8000000>;
23 audio_ext: oscillator-audio {
24 compatible = "fixed-clock";
26 clock-frequency = <24576000>;
29 enet_ext: oscillator-ethernet {
30 compatible = "fixed-clock";
32 clock-frequency = <50000000>;
36 compatible = "gpio-leds";
37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_gpio_leds>;
43 gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
45 linux,default-trigger = "heartbeat";
49 reg_3p3v: regulator-3p3v {
50 compatible = "regulator-fixed";
51 regulator-name = "3P3V";
52 regulator-min-microvolt = <3300000>;
53 regulator-max-microvolt = <3300000>;
57 reg_vcc_3v3_mcu: regulator-vcc3v3mcu {
58 compatible = "regulator-fixed";
59 regulator-name = "vcc_3v3_mcu";
60 regulator-min-microvolt = <3300000>;
61 regulator-max-microvolt = <3300000>;
65 compatible = "spi-gpio";
66 pinctrl-0 = <&pinctrl_gpio_spi>;
67 pinctrl-names = "default";
70 /* PTD12 ->RPIO[91] */
71 sck-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
72 /* PTD10 ->RPIO[89] */
73 miso-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
74 num-chipselects = <0>;
77 compatible = "pisosr-gpio";
81 /* PTB18 -> RGPIO[40] */
82 load-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
83 spi-max-frequency = <100000>;
89 vref-supply = <®_vcc_3v3_mcu>;
94 vref-supply = <®_vcc_3v3_mcu>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_can0>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_can1>;
111 clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>;
112 clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext";
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_dspi0>;
122 compatible = "lwn,bk4";
123 spi-max-frequency = <30000000>;
125 fsl,spi-cs-sck-delay = <200>;
126 fsl,spi-sck-cs-delay = <400>;
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_dspi3>;
136 #address-cells = <0>;
139 compatible = "lwn,bk4";
140 spi-max-frequency = <30000000>;
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_esdhc1>;
156 cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
162 phy-handle = <ðphy0>;
163 pinctrl-names = "default";
164 pinctrl-0 = <&pinctrl_fec0>;
168 #address-cells = <1>;
171 ethphy0: ethernet-phy@1 {
173 clocks = <&clks VF610_CLK_ENET_50M>;
174 clock-names = "rmii-ref";
181 phy-handle = <ðphy1>;
182 pinctrl-names = "default";
183 pinctrl-0 = <&pinctrl_fec1>;
187 #address-cells = <1>;
190 ethphy1: ethernet-phy@1 {
192 clocks = <&clks VF610_CLK_ENET_50M>;
193 clock-names = "rmii-ref";
199 clock-frequency = <400000>;
200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_i2c2>;
204 at24c256: eeprom@50 {
205 compatible = "atmel,24c256";
210 compatible = "st,m41t62";
216 assigned-clocks = <&clks VF610_CLK_NFC>;
217 assigned-clock-rates = <33000000>;
218 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_nfc>;
223 compatible = "fsl,vf610-nfc-nandcs";
225 #address-cells = <1>;
227 nand-bus-width = <16>;
228 nand-ecc-mode = "hw";
229 nand-ecc-strength = <24>;
230 nand-ecc-step-size = <2048>;
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_qspi0>;
240 n25q128a13_4: flash@0 {
241 compatible = "n25q128a13", "jedec,spi-nor";
242 #address-cells = <1>;
244 spi-max-frequency = <66000000>;
245 spi-rx-bus-width = <4>;
249 n25q128a13_2: flash@2 {
250 compatible = "n25q128a13", "jedec,spi-nor";
251 #address-cells = <1>;
253 spi-max-frequency = <66000000>;
254 spi-rx-bus-width = <2>;
260 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_uart0>;
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_uart1>;
272 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_uart2>;
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_uart3>;
284 disable-over-current;
289 disable-over-current;
310 pinctrl-names = "default";
311 pinctrl-0 = <&pinctrl_hog>;
313 pinctrl_hog: hoggrp {
315 /* One_Wire_PSU_EN */
316 VF610_PAD_PTC29__GPIO_102 0x1183
318 VF610_PAD_PTB26__GPIO_96 0x1183
320 VF610_PAD_PTE14__GPIO_119 0x1183
321 VF610_PAD_PTE4__GPIO_109 0x1181
323 VF610_PAD_PTC31__GPIO_104 0x1181
324 VF610_PAD_PTA7__GPIO_134 0x1181
325 VF610_PAD_PTD9__GPIO_88 0x1181
326 VF610_PAD_PTE1__GPIO_106 0x1183
327 VF610_PAD_PTB2__GPIO_24 0x1181
328 VF610_PAD_PTB3__GPIO_25 0x1181
329 VF610_PAD_PTB1__GPIO_23 0x1181
331 VF610_PAD_PTE19__GPIO_124 0x1183
332 /* SDHC Overcurrent */
333 VF610_PAD_PTB23__GPIO_93 0x1181
335 VF610_PAD_PTE2__GPIO_107 0x1181
336 VF610_PAD_PTE3__GPIO_108 0x1181
337 VF610_PAD_PTE5__GPIO_110 0x1181
338 VF610_PAD_PTE6__GPIO_111 0x1181
340 VF610_PAD_PTE0__GPIO_105 0x1183
341 VF610_PAD_PTE7__GPIO_112 0x1183
343 VF610_PAD_PTB8__GPIO_30 0x1183
344 VF610_PAD_PTB9__GPIO_31 0x1183
345 VF610_PAD_PTE8__GPIO_113 0x1183
347 VF610_PAD_PTE28__GPIO_133 0x1183
349 VF610_PAD_PTE10__GPIO_115 0x1183
350 VF610_PAD_PTE11__GPIO_116 0x1183
351 VF610_PAD_PTE17__GPIO_122 0x1183
352 VF610_PAD_PTC30__GPIO_103 0x1183
353 VF610_PAD_PTB0__GPIO_22 0x1181
355 VF610_PAD_PTE26__GPIO_131 0x1183
356 VF610_PAD_PTD6__GPIO_85 0x1181
357 VF610_PAD_PTE27__GPIO_132 0x1181
358 VF610_PAD_PTE13__GPIO_118 0x1181
359 VF610_PAD_PTE21__GPIO_126 0x1181
360 VF610_PAD_PTE22__GPIO_127 0x1181
362 VF610_PAD_PTE18__GPIO_123 0x1183
364 VF610_PAD_PTE25__GPIO_130 0x1181
368 pinctrl_can0: can0grp {
370 VF610_PAD_PTB14__CAN0_RX 0x1181
371 VF610_PAD_PTB15__CAN0_TX 0x1182
375 pinctrl_can1: can1grp {
377 VF610_PAD_PTB16__CAN1_RX 0x1181
378 VF610_PAD_PTB17__CAN1_TX 0x1182
382 pinctrl_dspi0: dspi0grp {
384 VF610_PAD_PTB18__DSPI0_CS1 0x1182
385 VF610_PAD_PTB19__DSPI0_CS0 0x1182
386 VF610_PAD_PTB20__DSPI0_SIN 0x1181
387 VF610_PAD_PTB21__DSPI0_SOUT 0x1182
388 VF610_PAD_PTB22__DSPI0_SCK 0x1182
392 pinctrl_dspi3: dspi3grp {
394 VF610_PAD_PTD10__DSPI3_CS0 0x1181
395 VF610_PAD_PTD11__DSPI3_SIN 0x1181
396 VF610_PAD_PTD12__DSPI3_SOUT 0x1182
397 VF610_PAD_PTD13__DSPI3_SCK 0x1181
401 pinctrl_esdhc1: esdhc1grp {
403 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
404 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
405 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
406 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
407 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
408 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
409 VF610_PAD_PTB28__GPIO_98 0x219d
413 pinctrl_fec0: fec0grp {
415 VF610_PAD_PTA6__RMII_CLKIN 0x30dd
416 VF610_PAD_PTC0__ENET_RMII0_MDC 0x30de
417 VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30df
418 VF610_PAD_PTC2__ENET_RMII0_CRS 0x30dd
419 VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30dd
420 VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30dd
421 VF610_PAD_PTC5__ENET_RMII0_RXER 0x30dd
422 VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30de
423 VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30de
424 VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30de
428 pinctrl_fec1: fec1grp {
430 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30de
431 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30df
432 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30dd
433 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30dd
434 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30dd
435 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30dd
436 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30de
437 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30de
438 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30de
442 pinctrl_gpio_leds: gpioledsgrp {
445 VF610_PAD_PTE12__GPIO_117 0x1183
447 VF610_PAD_PTE15__GPIO_120 0x1183
448 VF610_PAD_PTA12__GPIO_5 0x1183
449 VF610_PAD_PTA16__GPIO_6 0x1183
450 VF610_PAD_PTE9__GPIO_114 0x1183
451 VF610_PAD_PTE20__GPIO_125 0x1183
452 VF610_PAD_PTE23__GPIO_128 0x1183
453 VF610_PAD_PTE16__GPIO_121 0x1183
457 pinctrl_gpio_spi: pinctrl-gpio-spi {
459 VF610_PAD_PTB18__GPIO_40 0x1183
460 VF610_PAD_PTD10__GPIO_89 0x1183
461 VF610_PAD_PTD12__GPIO_91 0x1183
465 pinctrl_i2c2: i2c2grp {
467 VF610_PAD_PTA22__I2C2_SCL 0x34df
468 VF610_PAD_PTA23__I2C2_SDA 0x34df
472 pinctrl_nfc: nfcgrp {
474 VF610_PAD_PTD23__NF_IO7 0x28df
475 VF610_PAD_PTD22__NF_IO6 0x28df
476 VF610_PAD_PTD21__NF_IO5 0x28df
477 VF610_PAD_PTD20__NF_IO4 0x28df
478 VF610_PAD_PTD19__NF_IO3 0x28df
479 VF610_PAD_PTD18__NF_IO2 0x28df
480 VF610_PAD_PTD17__NF_IO1 0x28df
481 VF610_PAD_PTD16__NF_IO0 0x28df
482 VF610_PAD_PTB24__NF_WE_B 0x28c2
483 VF610_PAD_PTB25__NF_CE0_B 0x28c2
484 VF610_PAD_PTB27__NF_RE_B 0x28c2
485 VF610_PAD_PTC26__NF_RB_B 0x283d
486 VF610_PAD_PTC27__NF_ALE 0x28c2
487 VF610_PAD_PTC28__NF_CLE 0x28c2
491 pinctrl_qspi0: qspi0grp {
493 VF610_PAD_PTD0__QSPI0_A_QSCK 0x397f
494 VF610_PAD_PTD1__QSPI0_A_CS0 0x397f
495 VF610_PAD_PTD2__QSPI0_A_DATA3 0x397f
496 VF610_PAD_PTD3__QSPI0_A_DATA2 0x397f
497 VF610_PAD_PTD4__QSPI0_A_DATA1 0x397f
498 VF610_PAD_PTD5__QSPI0_A_DATA0 0x397f
499 VF610_PAD_PTD7__QSPI0_B_QSCK 0x397f
500 VF610_PAD_PTD8__QSPI0_B_CS0 0x397f
501 VF610_PAD_PTD11__QSPI0_B_DATA1 0x397f
502 VF610_PAD_PTD12__QSPI0_B_DATA0 0x397f
506 pinctrl_uart0: uart0grp {
508 VF610_PAD_PTB10__UART0_TX 0x21a2
509 VF610_PAD_PTB11__UART0_RX 0x21a1
513 pinctrl_uart1: uart1grp {
515 VF610_PAD_PTB4__UART1_TX 0x21a2
516 VF610_PAD_PTB5__UART1_RX 0x21a1
520 pinctrl_uart2: uart2grp {
522 VF610_PAD_PTB6__UART2_TX 0x21a2
523 VF610_PAD_PTB7__UART2_RX 0x21a1
527 pinctrl_uart3: uart3grp {
529 VF610_PAD_PTA20__UART3_TX 0x21a2
530 VF610_PAD_PTA21__UART3_RX 0x21a1