1 // SPDX-License-Identifier: GPL-2.0
3 * ARM Ltd. Versatile Express
5 * CoreTile Express A5x2
6 * Cortex-A5 MPCore (V2P-CA5s)
12 #include "vexpress-v2m-rs1.dtsi"
17 arm,vexpress,site = <0xf>;
18 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
19 interrupt-parent = <&gic>;
26 serial0 = &v2m_serial0;
27 serial1 = &v2m_serial1;
28 serial2 = &v2m_serial2;
29 serial3 = &v2m_serial3;
40 compatible = "arm,cortex-a5";
42 next-level-cache = <&L2>;
47 compatible = "arm,cortex-a5";
49 next-level-cache = <&L2>;
54 device_type = "memory";
55 reg = <0x80000000 0x40000000>;
63 /* Chipselect 2 is physically at 0x18000000 */
65 /* 8 MB of designated video RAM */
66 compatible = "shared-dma-pool";
67 reg = <0x18000000 0x00800000>;
73 compatible = "arm,hdlcd";
74 reg = <0x2a110000 0x1000>;
75 interrupts = <0 85 4>;
76 clocks = <&hdlcd_clk>;
77 clock-names = "pxlclk";
80 memory-controller@2a150000 {
81 compatible = "arm,pl341", "arm,primecell";
82 reg = <0x2a150000 0x1000>;
84 clock-names = "apb_pclk";
87 memory-controller@2a190000 {
88 compatible = "arm,pl354", "arm,primecell";
89 reg = <0x2a190000 0x1000>;
90 interrupts = <0 86 4>,
93 clock-names = "apb_pclk";
97 compatible = "arm,cortex-a5-scu";
98 reg = <0x2c000000 0x58>;
102 compatible = "arm,cortex-a5-twd-timer";
103 reg = <0x2c000600 0x20>;
104 interrupts = <1 13 0x304>;
108 compatible = "arm,cortex-a5-global-timer",
109 "arm,cortex-a9-global-timer";
110 reg = <0x2c000200 0x20>;
111 interrupts = <1 11 0x304>;
116 compatible = "arm,cortex-a5-twd-wdt";
117 reg = <0x2c000620 0x20>;
118 interrupts = <1 14 0x304>;
121 gic: interrupt-controller@2c001000 {
122 compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic";
123 #interrupt-cells = <3>;
124 #address-cells = <0>;
125 interrupt-controller;
126 reg = <0x2c001000 0x1000>,
130 L2: cache-controller@2c0f0000 {
131 compatible = "arm,pl310-cache";
132 reg = <0x2c0f0000 0x1000>;
133 interrupts = <0 84 4>;
139 compatible = "arm,cortex-a5-pmu";
140 interrupts = <0 68 4>,
145 compatible = "arm,vexpress,config-bus";
146 arm,vexpress,config-bridge = <&v2m_sysreg>;
149 /* CPU and internal AXI reference clock */
150 compatible = "arm,vexpress-osc";
151 arm,vexpress-sysreg,func = <1 0>;
152 freq-range = <50000000 100000000>;
154 clock-output-names = "oscclk0";
158 /* Multiplexed AXI master clock */
159 compatible = "arm,vexpress-osc";
160 arm,vexpress-sysreg,func = <1 1>;
161 freq-range = <5000000 50000000>;
163 clock-output-names = "oscclk1";
168 compatible = "arm,vexpress-osc";
169 arm,vexpress-sysreg,func = <1 2>;
170 freq-range = <80000000 120000000>;
172 clock-output-names = "oscclk2";
177 compatible = "arm,vexpress-osc";
178 arm,vexpress-sysreg,func = <1 3>;
179 freq-range = <23750000 165000000>;
181 clock-output-names = "oscclk3";
185 /* Test chip gate configuration */
186 compatible = "arm,vexpress-osc";
187 arm,vexpress-sysreg,func = <1 4>;
188 freq-range = <80000000 80000000>;
190 clock-output-names = "oscclk4";
195 compatible = "arm,vexpress-osc";
196 arm,vexpress-sysreg,func = <1 5>;
197 freq-range = <25000000 60000000>;
199 clock-output-names = "oscclk5";
203 /* DCC internal operating temperature */
204 compatible = "arm,vexpress-temp";
205 arm,vexpress-sysreg,func = <4 0>;
211 compatible = "simple-bus";
213 #address-cells = <2>;
215 ranges = <0 0 0x08000000 0x04000000>,
216 <1 0 0x14000000 0x04000000>,
217 <2 0 0x18000000 0x04000000>,
218 <3 0 0x1c000000 0x04000000>,
219 <4 0 0x0c000000 0x04000000>,
220 <5 0 0x10000000 0x04000000>;
222 #interrupt-cells = <1>;
223 interrupt-map-mask = <0 0 63>;
224 interrupt-map = <0 0 0 &gic 0 0 4>,
234 <0 0 10 &gic 0 10 4>,
235 <0 0 11 &gic 0 11 4>,
236 <0 0 12 &gic 0 12 4>,
237 <0 0 13 &gic 0 13 4>,
238 <0 0 14 &gic 0 14 4>,
239 <0 0 15 &gic 0 15 4>,
240 <0 0 16 &gic 0 16 4>,
241 <0 0 17 &gic 0 17 4>,
242 <0 0 18 &gic 0 18 4>,
243 <0 0 19 &gic 0 19 4>,
244 <0 0 20 &gic 0 20 4>,
245 <0 0 21 &gic 0 21 4>,
246 <0 0 22 &gic 0 22 4>,
247 <0 0 23 &gic 0 23 4>,
248 <0 0 24 &gic 0 24 4>,
249 <0 0 25 &gic 0 25 4>,
250 <0 0 26 &gic 0 26 4>,
251 <0 0 27 &gic 0 27 4>,
252 <0 0 28 &gic 0 28 4>,
253 <0 0 29 &gic 0 29 4>,
254 <0 0 30 &gic 0 30 4>,
255 <0 0 31 &gic 0 31 4>,
256 <0 0 32 &gic 0 32 4>,
257 <0 0 33 &gic 0 33 4>,
258 <0 0 34 &gic 0 34 4>,
259 <0 0 35 &gic 0 35 4>,
260 <0 0 36 &gic 0 36 4>,
261 <0 0 37 &gic 0 37 4>,
262 <0 0 38 &gic 0 38 4>,
263 <0 0 39 &gic 0 39 4>,
264 <0 0 40 &gic 0 40 4>,
265 <0 0 41 &gic 0 41 4>,
266 <0 0 42 &gic 0 42 4>;
269 site2: hsb@40000000 {
270 compatible = "simple-bus";
271 #address-cells = <1>;
273 ranges = <0 0x40000000 0x40000000>;
274 #interrupt-cells = <1>;
275 interrupt-map-mask = <0 3>;
276 interrupt-map = <0 0 &gic 0 36 4>,