1 // SPDX-License-Identifier: GPL-2.0
3 * ARM Ltd. Versatile Express
5 * CoreTile Express A15x2 A7x3
6 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15_CA7";
17 arm,vexpress,site = <0xf>;
18 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
19 interrupt-parent = <&gic>;
26 serial0 = &v2m_serial0;
27 serial1 = &v2m_serial1;
28 serial2 = &v2m_serial2;
29 serial3 = &v2m_serial3;
40 compatible = "arm,cortex-a15";
42 cci-control-port = <&cci_control1>;
43 cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
44 capacity-dmips-mhz = <1024>;
49 compatible = "arm,cortex-a15";
51 cci-control-port = <&cci_control1>;
52 cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
53 capacity-dmips-mhz = <1024>;
58 compatible = "arm,cortex-a7";
60 cci-control-port = <&cci_control2>;
61 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
62 capacity-dmips-mhz = <516>;
67 compatible = "arm,cortex-a7";
69 cci-control-port = <&cci_control2>;
70 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
71 capacity-dmips-mhz = <516>;
76 compatible = "arm,cortex-a7";
78 cci-control-port = <&cci_control2>;
79 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
80 capacity-dmips-mhz = <516>;
84 CLUSTER_SLEEP_BIG: cluster-sleep-big {
85 compatible = "arm,idle-state";
87 entry-latency-us = <1000>;
88 exit-latency-us = <700>;
89 min-residency-us = <2000>;
92 CLUSTER_SLEEP_LITTLE: cluster-sleep-little {
93 compatible = "arm,idle-state";
95 entry-latency-us = <1000>;
96 exit-latency-us = <500>;
97 min-residency-us = <2500>;
103 device_type = "memory";
104 reg = <0 0x80000000 0 0x40000000>;
108 compatible = "arm,sp805", "arm,primecell";
109 reg = <0 0x2a490000 0 0x1000>;
110 interrupts = <0 98 4>;
111 clocks = <&oscclk6a>, <&oscclk6a>;
112 clock-names = "wdogclk", "apb_pclk";
116 compatible = "arm,hdlcd";
117 reg = <0 0x2b000000 0 0x1000>;
118 interrupts = <0 85 4>;
119 clocks = <&hdlcd_clk>;
120 clock-names = "pxlclk";
123 memory-controller@2b0a0000 {
124 compatible = "arm,pl341", "arm,primecell";
125 reg = <0 0x2b0a0000 0 0x1000>;
126 clocks = <&oscclk6a>;
127 clock-names = "apb_pclk";
130 gic: interrupt-controller@2c001000 {
131 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
132 #interrupt-cells = <3>;
133 #address-cells = <0>;
134 interrupt-controller;
135 reg = <0 0x2c001000 0 0x1000>,
136 <0 0x2c002000 0 0x2000>,
137 <0 0x2c004000 0 0x2000>,
138 <0 0x2c006000 0 0x2000>;
139 interrupts = <1 9 0xf04>;
143 compatible = "arm,cci-400";
144 #address-cells = <1>;
146 reg = <0 0x2c090000 0 0x1000>;
147 ranges = <0x0 0x0 0x2c090000 0x10000>;
149 cci_control1: slave-if@4000 {
150 compatible = "arm,cci-400-ctrl-if";
151 interface-type = "ace";
152 reg = <0x4000 0x1000>;
155 cci_control2: slave-if@5000 {
156 compatible = "arm,cci-400-ctrl-if";
157 interface-type = "ace";
158 reg = <0x5000 0x1000>;
162 compatible = "arm,cci-400-pmu,r0";
163 reg = <0x9000 0x5000>;
164 interrupts = <0 105 4>,
172 memory-controller@7ffd0000 {
173 compatible = "arm,pl354", "arm,primecell";
174 reg = <0 0x7ffd0000 0 0x1000>;
175 interrupts = <0 86 4>,
177 clocks = <&oscclk6a>;
178 clock-names = "apb_pclk";
182 compatible = "arm,pl330", "arm,primecell";
183 reg = <0 0x7ff00000 0 0x1000>;
184 interrupts = <0 92 4>,
189 clocks = <&oscclk6a>;
190 clock-names = "apb_pclk";
194 compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
195 reg = <0 0x7fff0000 0 0x1000>;
196 interrupts = <0 95 4>;
200 compatible = "arm,armv7-timer";
201 interrupts = <1 13 0xf08>,
208 compatible = "arm,cortex-a15-pmu";
209 interrupts = <0 68 4>,
211 interrupt-affinity = <&cpu0>,
216 compatible = "arm,cortex-a7-pmu";
217 interrupts = <0 128 4>,
220 interrupt-affinity = <&cpu2>,
226 /* Reference 24MHz clock */
227 compatible = "fixed-clock";
229 clock-frequency = <24000000>;
230 clock-output-names = "oscclk6a";
234 compatible = "arm,vexpress,config-bus";
235 arm,vexpress,config-bridge = <&v2m_sysreg>;
238 /* A15 PLL 0 reference clock */
239 compatible = "arm,vexpress-osc";
240 arm,vexpress-sysreg,func = <1 0>;
241 freq-range = <17000000 50000000>;
243 clock-output-names = "oscclk0";
247 /* A15 PLL 1 reference clock */
248 compatible = "arm,vexpress-osc";
249 arm,vexpress-sysreg,func = <1 1>;
250 freq-range = <17000000 50000000>;
252 clock-output-names = "oscclk1";
256 /* A7 PLL 0 reference clock */
257 compatible = "arm,vexpress-osc";
258 arm,vexpress-sysreg,func = <1 2>;
259 freq-range = <17000000 50000000>;
261 clock-output-names = "oscclk2";
265 /* A7 PLL 1 reference clock */
266 compatible = "arm,vexpress-osc";
267 arm,vexpress-sysreg,func = <1 3>;
268 freq-range = <17000000 50000000>;
270 clock-output-names = "oscclk3";
274 /* External AXI master clock */
275 compatible = "arm,vexpress-osc";
276 arm,vexpress-sysreg,func = <1 4>;
277 freq-range = <20000000 40000000>;
279 clock-output-names = "oscclk4";
283 /* HDLCD PLL reference clock */
284 compatible = "arm,vexpress-osc";
285 arm,vexpress-sysreg,func = <1 5>;
286 freq-range = <23750000 165000000>;
288 clock-output-names = "oscclk5";
292 /* Static memory controller clock */
293 compatible = "arm,vexpress-osc";
294 arm,vexpress-sysreg,func = <1 6>;
295 freq-range = <20000000 40000000>;
297 clock-output-names = "oscclk6";
301 /* SYS PLL reference clock */
302 compatible = "arm,vexpress-osc";
303 arm,vexpress-sysreg,func = <1 7>;
304 freq-range = <17000000 50000000>;
306 clock-output-names = "oscclk7";
310 /* DDR2 PLL reference clock */
311 compatible = "arm,vexpress-osc";
312 arm,vexpress-sysreg,func = <1 8>;
313 freq-range = <20000000 50000000>;
315 clock-output-names = "oscclk8";
319 /* A15 CPU core voltage */
320 compatible = "arm,vexpress-volt";
321 arm,vexpress-sysreg,func = <2 0>;
322 regulator-name = "A15 Vcore";
323 regulator-min-microvolt = <800000>;
324 regulator-max-microvolt = <1050000>;
330 /* A7 CPU core voltage */
331 compatible = "arm,vexpress-volt";
332 arm,vexpress-sysreg,func = <2 1>;
333 regulator-name = "A7 Vcore";
334 regulator-min-microvolt = <800000>;
335 regulator-max-microvolt = <1050000>;
341 /* Total current for the two A15 cores */
342 compatible = "arm,vexpress-amp";
343 arm,vexpress-sysreg,func = <3 0>;
348 /* Total current for the three A7 cores */
349 compatible = "arm,vexpress-amp";
350 arm,vexpress-sysreg,func = <3 1>;
355 /* DCC internal temperature */
356 compatible = "arm,vexpress-temp";
357 arm,vexpress-sysreg,func = <4 0>;
362 /* Total power for the two A15 cores */
363 compatible = "arm,vexpress-power";
364 arm,vexpress-sysreg,func = <12 0>;
369 /* Total power for the three A7 cores */
370 compatible = "arm,vexpress-power";
371 arm,vexpress-sysreg,func = <12 1>;
376 /* Total energy for the two A15 cores */
377 compatible = "arm,vexpress-energy";
378 arm,vexpress-sysreg,func = <13 0>, <13 1>;
383 /* Total energy for the three A7 cores */
384 compatible = "arm,vexpress-energy";
385 arm,vexpress-sysreg,func = <13 2>, <13 3>;
391 compatible = "arm,coresight-etb10", "arm,primecell";
392 reg = <0 0x20010000 0 0x1000>;
394 clocks = <&oscclk6a>;
395 clock-names = "apb_pclk";
397 etb_in_port: endpoint {
399 remote-endpoint = <&replicator_out_port0>;
405 compatible = "arm,coresight-tpiu", "arm,primecell";
406 reg = <0 0x20030000 0 0x1000>;
408 clocks = <&oscclk6a>;
409 clock-names = "apb_pclk";
411 tpiu_in_port: endpoint {
413 remote-endpoint = <&replicator_out_port1>;
419 /* non-configurable replicators don't show up on the
420 * AMBA bus. As such no need to add "arm,primecell".
422 compatible = "arm,coresight-replicator";
425 #address-cells = <1>;
428 /* replicator output ports */
431 replicator_out_port0: endpoint {
432 remote-endpoint = <&etb_in_port>;
438 replicator_out_port1: endpoint {
439 remote-endpoint = <&tpiu_in_port>;
443 /* replicator input port */
446 replicator_in_port0: endpoint {
448 remote-endpoint = <&funnel_out_port0>;
455 compatible = "arm,coresight-funnel", "arm,primecell";
456 reg = <0 0x20040000 0 0x1000>;
458 clocks = <&oscclk6a>;
459 clock-names = "apb_pclk";
461 #address-cells = <1>;
464 /* funnel output port */
467 funnel_out_port0: endpoint {
469 <&replicator_in_port0>;
473 /* funnel input ports */
476 funnel_in_port0: endpoint {
478 remote-endpoint = <&ptm0_out_port>;
484 funnel_in_port1: endpoint {
486 remote-endpoint = <&ptm1_out_port>;
492 funnel_in_port2: endpoint {
494 remote-endpoint = <&etm0_out_port>;
498 /* Input port #3 is for ITM, not supported here */
502 funnel_in_port4: endpoint {
504 remote-endpoint = <&etm1_out_port>;
510 funnel_in_port5: endpoint {
512 remote-endpoint = <&etm2_out_port>;
519 compatible = "arm,coresight-etm3x", "arm,primecell";
520 reg = <0 0x2201c000 0 0x1000>;
523 clocks = <&oscclk6a>;
524 clock-names = "apb_pclk";
526 ptm0_out_port: endpoint {
527 remote-endpoint = <&funnel_in_port0>;
533 compatible = "arm,coresight-etm3x", "arm,primecell";
534 reg = <0 0x2201d000 0 0x1000>;
537 clocks = <&oscclk6a>;
538 clock-names = "apb_pclk";
540 ptm1_out_port: endpoint {
541 remote-endpoint = <&funnel_in_port1>;
547 compatible = "arm,coresight-etm3x", "arm,primecell";
548 reg = <0 0x2203c000 0 0x1000>;
551 clocks = <&oscclk6a>;
552 clock-names = "apb_pclk";
554 etm0_out_port: endpoint {
555 remote-endpoint = <&funnel_in_port2>;
561 compatible = "arm,coresight-etm3x", "arm,primecell";
562 reg = <0 0x2203d000 0 0x1000>;
565 clocks = <&oscclk6a>;
566 clock-names = "apb_pclk";
568 etm1_out_port: endpoint {
569 remote-endpoint = <&funnel_in_port4>;
575 compatible = "arm,coresight-etm3x", "arm,primecell";
576 reg = <0 0x2203e000 0 0x1000>;
579 clocks = <&oscclk6a>;
580 clock-names = "apb_pclk";
582 etm2_out_port: endpoint {
583 remote-endpoint = <&funnel_in_port5>;
589 compatible = "simple-bus";
591 #address-cells = <2>;
593 ranges = <0 0 0 0x08000000 0x04000000>,
594 <1 0 0 0x14000000 0x04000000>,
595 <2 0 0 0x18000000 0x04000000>,
596 <3 0 0 0x1c000000 0x04000000>,
597 <4 0 0 0x0c000000 0x04000000>,
598 <5 0 0 0x10000000 0x04000000>;
600 #interrupt-cells = <1>;
601 interrupt-map-mask = <0 0 63>;
602 interrupt-map = <0 0 0 &gic 0 0 4>,
612 <0 0 10 &gic 0 10 4>,
613 <0 0 11 &gic 0 11 4>,
614 <0 0 12 &gic 0 12 4>,
615 <0 0 13 &gic 0 13 4>,
616 <0 0 14 &gic 0 14 4>,
617 <0 0 15 &gic 0 15 4>,
618 <0 0 16 &gic 0 16 4>,
619 <0 0 17 &gic 0 17 4>,
620 <0 0 18 &gic 0 18 4>,
621 <0 0 19 &gic 0 19 4>,
622 <0 0 20 &gic 0 20 4>,
623 <0 0 21 &gic 0 21 4>,
624 <0 0 22 &gic 0 22 4>,
625 <0 0 23 &gic 0 23 4>,
626 <0 0 24 &gic 0 24 4>,
627 <0 0 25 &gic 0 25 4>,
628 <0 0 26 &gic 0 26 4>,
629 <0 0 27 &gic 0 27 4>,
630 <0 0 28 &gic 0 28 4>,
631 <0 0 29 &gic 0 29 4>,
632 <0 0 30 &gic 0 30 4>,
633 <0 0 31 &gic 0 31 4>,
634 <0 0 32 &gic 0 32 4>,
635 <0 0 33 &gic 0 33 4>,
636 <0 0 34 &gic 0 34 4>,
637 <0 0 35 &gic 0 35 4>,
638 <0 0 36 &gic 0 36 4>,
639 <0 0 37 &gic 0 37 4>,
640 <0 0 38 &gic 0 38 4>,
641 <0 0 39 &gic 0 39 4>,
642 <0 0 40 &gic 0 40 4>,
643 <0 0 41 &gic 0 41 4>,
644 <0 0 42 &gic 0 42 4>;
647 site2: hsb@40000000 {
648 compatible = "simple-bus";
649 #address-cells = <1>;
651 ranges = <0 0 0x40000000 0x3fef0000>;
652 #interrupt-cells = <1>;
653 interrupt-map-mask = <0 3>;
654 interrupt-map = <0 0 &gic 0 36 4>,