arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ARM Ltd. Versatile Express
   4  *
   5  * CoreTile Express A15x2 (version with Test Chip 1)
   6  * Cortex-A15 MPCore (V2P-CA15)
   7  *
   8  * HBI-0237A
   9  */
  10
  11 /dts-v1/;
  12 #include "vexpress-v2m-rs1.dtsi"
  13
  14 / {
  15         model = "V2P-CA15";
  16         arm,hbi = <0x237>;
  17         arm,vexpress,site = <0xf>;
  18         compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         chosen { };
  24
  25         aliases {
  26                 serial0 = &v2m_serial0;
  27                 serial1 = &v2m_serial1;
  28                 serial2 = &v2m_serial2;
  29                 serial3 = &v2m_serial3;
  30                 i2c0 = &v2m_i2c_dvi;
  31                 i2c1 = &v2m_i2c_pcie;
  32         };
  33
  34         cpus {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 cpu@0 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a15";
  41                         reg = <0>;
  42                 };
  43
  44                 cpu@1 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a15";
  47                         reg = <1>;
  48                 };
  49         };
  50
  51         memory@80000000 {
  52                 device_type = "memory";
  53                 reg = <0 0x80000000 0 0x40000000>;
  54         };
  55
  56         hdlcd@2b000000 {
  57                 compatible = "arm,hdlcd";
  58                 reg = <0 0x2b000000 0 0x1000>;
  59                 interrupts = <0 85 4>;
  60                 clocks = <&hdlcd_clk>;
  61                 clock-names = "pxlclk";
  62         };
  63
  64         memory-controller@2b0a0000 {
  65                 compatible = "arm,pl341", "arm,primecell";
  66                 reg = <0 0x2b0a0000 0 0x1000>;
  67                 clocks = <&sys_pll>;
  68                 clock-names = "apb_pclk";
  69         };
  70
  71         wdt@2b060000 {
  72                 compatible = "arm,sp805", "arm,primecell";
  73                 status = "disabled";
  74                 reg = <0 0x2b060000 0 0x1000>;
  75                 interrupts = <0 98 4>;
  76                 clocks = <&sys_pll>;
  77                 clock-names = "apb_pclk";
  78         };
  79
  80         gic: interrupt-controller@2c001000 {
  81                 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  82                 #interrupt-cells = <3>;
  83                 #address-cells = <0>;
  84                 interrupt-controller;
  85                 reg = <0 0x2c001000 0 0x1000>,
  86                       <0 0x2c002000 0 0x2000>,
  87                       <0 0x2c004000 0 0x2000>,
  88                       <0 0x2c006000 0 0x2000>;
  89                 interrupts = <1 9 0xf04>;
  90         };
  91
  92         memory-controller@7ffd0000 {
  93                 compatible = "arm,pl354", "arm,primecell";
  94                 reg = <0 0x7ffd0000 0 0x1000>;
  95                 interrupts = <0 86 4>,
  96                              <0 87 4>;
  97                 clocks = <&sys_pll>;
  98                 clock-names = "apb_pclk";
  99         };
 100
 101         dma@7ffb0000 {
 102                 compatible = "arm,pl330", "arm,primecell";
 103                 reg = <0 0x7ffb0000 0 0x1000>;
 104                 interrupts = <0 92 4>,
 105                              <0 88 4>,
 106                              <0 89 4>,
 107                              <0 90 4>,
 108                              <0 91 4>;
 109                 clocks = <&sys_pll>;
 110                 clock-names = "apb_pclk";
 111         };
 112
 113         timer {
 114                 compatible = "arm,armv7-timer";
 115                 interrupts = <1 13 0xf08>,
 116                              <1 14 0xf08>,
 117                              <1 11 0xf08>,
 118                              <1 10 0xf08>;
 119         };
 120
 121         pmu {
 122                 compatible = "arm,cortex-a15-pmu";
 123                 interrupts = <0 68 4>,
 124                              <0 69 4>;
 125         };
 126
 127         dcc {
 128                 compatible = "arm,vexpress,config-bus";
 129                 arm,vexpress,config-bridge = <&v2m_sysreg>;
 130
 131                 oscclk0 {
 132                         /* CPU PLL reference clock */
 133                         compatible = "arm,vexpress-osc";
 134                         arm,vexpress-sysreg,func = <1 0>;
 135                         freq-range = <50000000 60000000>;
 136                         #clock-cells = <0>;
 137                         clock-output-names = "oscclk0";
 138                 };
 139
 140                 oscclk4 {
 141                         /* Multiplexed AXI master clock */
 142                         compatible = "arm,vexpress-osc";
 143                         arm,vexpress-sysreg,func = <1 4>;
 144                         freq-range = <20000000 40000000>;
 145                         #clock-cells = <0>;
 146                         clock-output-names = "oscclk4";
 147                 };
 148
 149                 hdlcd_clk: oscclk5 {
 150                         /* HDLCD PLL reference clock */
 151                         compatible = "arm,vexpress-osc";
 152                         arm,vexpress-sysreg,func = <1 5>;
 153                         freq-range = <23750000 165000000>;
 154                         #clock-cells = <0>;
 155                         clock-output-names = "oscclk5";
 156                 };
 157
 158                 smbclk: oscclk6 {
 159                         /* SMB clock */
 160                         compatible = "arm,vexpress-osc";
 161                         arm,vexpress-sysreg,func = <1 6>;
 162                         freq-range = <20000000 50000000>;
 163                         #clock-cells = <0>;
 164                         clock-output-names = "oscclk6";
 165                 };
 166
 167                 sys_pll: oscclk7 {
 168                         /* SYS PLL reference clock */
 169                         compatible = "arm,vexpress-osc";
 170                         arm,vexpress-sysreg,func = <1 7>;
 171                         freq-range = <20000000 60000000>;
 172                         #clock-cells = <0>;
 173                         clock-output-names = "oscclk7";
 174                 };
 175
 176                 oscclk8 {
 177                         /* DDR2 PLL reference clock */
 178                         compatible = "arm,vexpress-osc";
 179                         arm,vexpress-sysreg,func = <1 8>;
 180                         freq-range = <40000000 40000000>;
 181                         #clock-cells = <0>;
 182                         clock-output-names = "oscclk8";
 183                 };
 184
 185                 volt-cores {
 186                         /* CPU core voltage */
 187                         compatible = "arm,vexpress-volt";
 188                         arm,vexpress-sysreg,func = <2 0>;
 189                         regulator-name = "Cores";
 190                         regulator-min-microvolt = <800000>;
 191                         regulator-max-microvolt = <1050000>;
 192                         regulator-always-on;
 193                         label = "Cores";
 194                 };
 195
 196                 amp-cores {
 197                         /* Total current for the two cores */
 198                         compatible = "arm,vexpress-amp";
 199                         arm,vexpress-sysreg,func = <3 0>;
 200                         label = "Cores";
 201                 };
 202
 203                 temp-dcc {
 204                         /* DCC internal temperature */
 205                         compatible = "arm,vexpress-temp";
 206                         arm,vexpress-sysreg,func = <4 0>;
 207                         label = "DCC";
 208                 };
 209
 210                 power-cores {
 211                         /* Total power */
 212                         compatible = "arm,vexpress-power";
 213                         arm,vexpress-sysreg,func = <12 0>;
 214                         label = "Cores";
 215                 };
 216
 217                 energy {
 218                         /* Total energy */
 219                         compatible = "arm,vexpress-energy";
 220                         arm,vexpress-sysreg,func = <13 0>;
 221                         label = "Cores";
 222                 };
 223         };
 224
 225         smb@8000000 {
 226                 compatible = "simple-bus";
 227
 228                 #address-cells = <2>;
 229                 #size-cells = <1>;
 230                 ranges = <0 0 0 0x08000000 0x04000000>,
 231                          <1 0 0 0x14000000 0x04000000>,
 232                          <2 0 0 0x18000000 0x04000000>,
 233                          <3 0 0 0x1c000000 0x04000000>,
 234                          <4 0 0 0x0c000000 0x04000000>,
 235                          <5 0 0 0x10000000 0x04000000>;
 236
 237                 #interrupt-cells = <1>;
 238                 interrupt-map-mask = <0 0 63>;
 239                 interrupt-map = <0 0  0 &gic 0  0 4>,
 240                                 <0 0  1 &gic 0  1 4>,
 241                                 <0 0  2 &gic 0  2 4>,
 242                                 <0 0  3 &gic 0  3 4>,
 243                                 <0 0  4 &gic 0  4 4>,
 244                                 <0 0  5 &gic 0  5 4>,
 245                                 <0 0  6 &gic 0  6 4>,
 246                                 <0 0  7 &gic 0  7 4>,
 247                                 <0 0  8 &gic 0  8 4>,
 248                                 <0 0  9 &gic 0  9 4>,
 249                                 <0 0 10 &gic 0 10 4>,
 250                                 <0 0 11 &gic 0 11 4>,
 251                                 <0 0 12 &gic 0 12 4>,
 252                                 <0 0 13 &gic 0 13 4>,
 253                                 <0 0 14 &gic 0 14 4>,
 254                                 <0 0 15 &gic 0 15 4>,
 255                                 <0 0 16 &gic 0 16 4>,
 256                                 <0 0 17 &gic 0 17 4>,
 257                                 <0 0 18 &gic 0 18 4>,
 258                                 <0 0 19 &gic 0 19 4>,
 259                                 <0 0 20 &gic 0 20 4>,
 260                                 <0 0 21 &gic 0 21 4>,
 261                                 <0 0 22 &gic 0 22 4>,
 262                                 <0 0 23 &gic 0 23 4>,
 263                                 <0 0 24 &gic 0 24 4>,
 264                                 <0 0 25 &gic 0 25 4>,
 265                                 <0 0 26 &gic 0 26 4>,
 266                                 <0 0 27 &gic 0 27 4>,
 267                                 <0 0 28 &gic 0 28 4>,
 268                                 <0 0 29 &gic 0 29 4>,
 269                                 <0 0 30 &gic 0 30 4>,
 270                                 <0 0 31 &gic 0 31 4>,
 271                                 <0 0 32 &gic 0 32 4>,
 272                                 <0 0 33 &gic 0 33 4>,
 273                                 <0 0 34 &gic 0 34 4>,
 274                                 <0 0 35 &gic 0 35 4>,
 275                                 <0 0 36 &gic 0 36 4>,
 276                                 <0 0 37 &gic 0 37 4>,
 277                                 <0 0 38 &gic 0 38 4>,
 278                                 <0 0 39 &gic 0 39 4>,
 279                                 <0 0 40 &gic 0 40 4>,
 280                                 <0 0 41 &gic 0 41 4>,
 281                                 <0 0 42 &gic 0 42 4>;
 282         };
 283
 284         site2: hsb@40000000 {
 285                 compatible = "simple-bus";
 286                 #address-cells = <1>;
 287                 #size-cells = <1>;
 288                 ranges = <0 0 0x40000000 0x3fef0000>;
 289                 #interrupt-cells = <1>;
 290                 interrupt-map-mask = <0 3>;
 291                 interrupt-map = <0 0 &gic 0 36 4>,
 292                                 <0 1 &gic 0 37 4>,
 293                                 <0 2 &gic 0 38 4>,
 294                                 <0 3 &gic 0 39 4>;
 295         };
 296 };