1 // SPDX-License-Identifier: GPL-2.0
3 * ARM Ltd. Versatile Express
5 * Motherboard Express uATX
10 * Original memory map ("Legacy memory map" in the board's
11 * Technical Reference Manual)
13 * WARNING! The hardware described in this file is independent from the
14 * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
15 * correspondence between the two configurations.
17 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
18 * CHANGES TO vexpress-v2m-rs1.dtsi!
20 #include <dt-bindings/interrupt-controller/arm-gic.h>
24 compatible = "simple-bus";
27 ranges = <0x40000000 0x40000000 0x10000000>,
28 <0x10000000 0x10000000 0x00020000>;
30 #interrupt-cells = <1>;
31 interrupt-map-mask = <0 63>;
32 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
33 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
34 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
35 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
36 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
37 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
38 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
39 <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
40 <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
41 <0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
42 <0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
43 <0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
44 <0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
45 <0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
46 <0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
47 <0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
48 <0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
49 <0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
50 <0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
51 <0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
52 <0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
53 <0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
54 <0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
55 <0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
56 <0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
57 <0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
58 <0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
59 <0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
60 <0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
61 <0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
62 <0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
63 <0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
64 <0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
65 <0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
66 <0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
67 <0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
68 <0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
69 <0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
70 <0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
71 <0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
72 <0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
73 <0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
74 <0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
76 motherboard-bus@40000000 {
78 arm,vexpress,site = <0>;
79 compatible = "arm,vexpress,v2m-p1", "simple-bus";
80 #address-cells = <2>; /* SMB chipselect number and offset */
82 ranges = <0 0 0x40000000 0x04000000>,
83 <1 0 0x44000000 0x04000000>,
84 <2 0 0x48000000 0x04000000>,
85 <3 0 0x4c000000 0x04000000>,
86 <7 0 0x10000000 0x00020000>;
89 compatible = "arm,vexpress-flash", "cfi-flash";
90 reg = <0 0x00000000 0x04000000>,
91 <1 0x00000000 0x04000000>;
94 compatible = "arm,arm-firmware-suite";
99 compatible = "arm,vexpress-psram", "mtd-ram";
100 reg = <2 0x00000000 0x02000000>;
104 ethernet@3,02000000 {
105 compatible = "smsc,lan9118", "smsc,lan9115";
106 reg = <3 0x02000000 0x10000>;
110 smsc,irq-active-high;
112 vdd33a-supply = <&v2m_fixed_3v3>;
113 vddvario-supply = <&v2m_fixed_3v3>;
117 compatible = "nxp,usb-isp1761";
118 reg = <3 0x03000000 0x20000>;
120 dr_mode = "peripheral";
124 compatible = "simple-bus";
125 #address-cells = <1>;
127 ranges = <0 7 0 0x20000>;
129 v2m_sysreg: sysreg@0 {
130 compatible = "arm,vexpress-sysreg";
131 reg = <0x00000 0x1000>;
132 #address-cells = <1>;
134 ranges = <0 0 0x1000>;
136 v2m_led_gpios: gpio@8 {
137 compatible = "arm,vexpress-sysreg,sys_led";
143 v2m_mmc_gpios: gpio@48 {
144 compatible = "arm,vexpress-sysreg,sys_mci";
150 v2m_flash_gpios: gpio@4c {
151 compatible = "arm,vexpress-sysreg,sys_flash";
158 v2m_sysctl: sysctl@1000 {
159 compatible = "arm,sp810", "arm,primecell";
160 reg = <0x01000 0x1000>;
161 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
162 clock-names = "refclk", "timclk", "apb_pclk";
164 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
165 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
166 assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
170 v2m_i2c_pcie: i2c@2000 {
171 compatible = "arm,versatile-i2c";
172 reg = <0x02000 0x1000>;
174 #address-cells = <1>;
178 compatible = "idt,89hpes32h8";
184 compatible = "arm,pl041", "arm,primecell";
185 reg = <0x04000 0x1000>;
188 clock-names = "apb_pclk";
192 compatible = "arm,pl180", "arm,primecell";
193 reg = <0x05000 0x1000>;
194 interrupts = <9>, <10>;
195 cd-gpios = <&v2m_mmc_gpios 0 0>;
196 wp-gpios = <&v2m_mmc_gpios 1 0>;
197 max-frequency = <12000000>;
198 vmmc-supply = <&v2m_fixed_3v3>;
199 clocks = <&v2m_clk24mhz>, <&smbclk>;
200 clock-names = "mclk", "apb_pclk";
204 compatible = "arm,pl050", "arm,primecell";
205 reg = <0x06000 0x1000>;
207 clocks = <&v2m_clk24mhz>, <&smbclk>;
208 clock-names = "KMIREFCLK", "apb_pclk";
212 compatible = "arm,pl050", "arm,primecell";
213 reg = <0x07000 0x1000>;
215 clocks = <&v2m_clk24mhz>, <&smbclk>;
216 clock-names = "KMIREFCLK", "apb_pclk";
219 v2m_serial0: uart@9000 {
220 compatible = "arm,pl011", "arm,primecell";
221 reg = <0x09000 0x1000>;
223 clocks = <&v2m_oscclk2>, <&smbclk>;
224 clock-names = "uartclk", "apb_pclk";
227 v2m_serial1: uart@a000 {
228 compatible = "arm,pl011", "arm,primecell";
229 reg = <0x0a000 0x1000>;
231 clocks = <&v2m_oscclk2>, <&smbclk>;
232 clock-names = "uartclk", "apb_pclk";
235 v2m_serial2: uart@b000 {
236 compatible = "arm,pl011", "arm,primecell";
237 reg = <0x0b000 0x1000>;
239 clocks = <&v2m_oscclk2>, <&smbclk>;
240 clock-names = "uartclk", "apb_pclk";
243 v2m_serial3: uart@c000 {
244 compatible = "arm,pl011", "arm,primecell";
245 reg = <0x0c000 0x1000>;
247 clocks = <&v2m_oscclk2>, <&smbclk>;
248 clock-names = "uartclk", "apb_pclk";
252 compatible = "arm,sp805", "arm,primecell";
253 reg = <0x0f000 0x1000>;
255 clocks = <&v2m_refclk32khz>, <&smbclk>;
256 clock-names = "wdog_clk", "apb_pclk";
259 v2m_timer01: timer@11000 {
260 compatible = "arm,sp804", "arm,primecell";
261 reg = <0x11000 0x1000>;
263 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
264 clock-names = "timclken1", "timclken2", "apb_pclk";
267 v2m_timer23: timer@12000 {
268 compatible = "arm,sp804", "arm,primecell";
269 reg = <0x12000 0x1000>;
271 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
272 clock-names = "timclken1", "timclken2", "apb_pclk";
276 v2m_i2c_dvi: i2c@16000 {
277 compatible = "arm,versatile-i2c";
278 reg = <0x16000 0x1000>;
279 #address-cells = <1>;
283 compatible = "sil,sii9022-tpi", "sil,sii9022";
287 #address-cells = <1>;
291 * Both the core tile and the motherboard routes their output
292 * pads to this transmitter. The motherboard system controller
293 * can select one of them as input using a mux register in
294 * "arm,vexpress-muxfpga". The Vexpress with the CA9 core tile is
295 * the only platform with this specific set-up.
299 dvi_bridge_in_ct: endpoint {
300 remote-endpoint = <&clcd_pads_ct>;
305 dvi_bridge_in_mb: endpoint {
306 remote-endpoint = <&clcd_pads_mb>;
313 compatible = "sil,sii9022-cpi", "sil,sii9022";
319 compatible = "arm,pl031", "arm,primecell";
320 reg = <0x17000 0x1000>;
323 clock-names = "apb_pclk";
326 compact-flash@1a000 {
327 compatible = "arm,vexpress-cf", "ata-generic";
335 compatible = "arm,pl111", "arm,primecell";
336 reg = <0x1f000 0x1000>;
337 interrupt-names = "combined";
339 clocks = <&v2m_oscclk1>, <&smbclk>;
340 clock-names = "clcdclk", "apb_pclk";
341 /* 800x600 16bpp @36MHz works fine */
342 max-memory-bandwidth = <54000000>;
343 memory-region = <&vram>;
346 clcd_pads_mb: endpoint {
347 remote-endpoint = <&dvi_bridge_in_mb>;
348 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
354 v2m_fixed_3v3: fixed-regulator-0 {
355 compatible = "regulator-fixed";
356 regulator-name = "3V3";
357 regulator-min-microvolt = <3300000>;
358 regulator-max-microvolt = <3300000>;
362 v2m_clk24mhz: clk24mhz {
363 compatible = "fixed-clock";
365 clock-frequency = <24000000>;
366 clock-output-names = "v2m:clk24mhz";
369 v2m_refclk1mhz: refclk1mhz {
370 compatible = "fixed-clock";
372 clock-frequency = <1000000>;
373 clock-output-names = "v2m:refclk1mhz";
376 v2m_refclk32khz: refclk32khz {
377 compatible = "fixed-clock";
379 clock-frequency = <32768>;
380 clock-output-names = "v2m:refclk32khz";
384 compatible = "gpio-leds";
387 label = "v2m:green:user1";
388 gpios = <&v2m_led_gpios 0 0>;
389 linux,default-trigger = "heartbeat";
393 label = "v2m:green:user2";
394 gpios = <&v2m_led_gpios 1 0>;
395 linux,default-trigger = "mmc0";
399 label = "v2m:green:user3";
400 gpios = <&v2m_led_gpios 2 0>;
401 linux,default-trigger = "cpu0";
405 label = "v2m:green:user4";
406 gpios = <&v2m_led_gpios 3 0>;
407 linux,default-trigger = "cpu1";
411 label = "v2m:green:user5";
412 gpios = <&v2m_led_gpios 4 0>;
413 linux,default-trigger = "cpu2";
417 label = "v2m:green:user6";
418 gpios = <&v2m_led_gpios 5 0>;
419 linux,default-trigger = "cpu3";
423 label = "v2m:green:user7";
424 gpios = <&v2m_led_gpios 6 0>;
425 linux,default-trigger = "cpu4";
429 label = "v2m:green:user8";
430 gpios = <&v2m_led_gpios 7 0>;
431 linux,default-trigger = "cpu5";
436 compatible = "arm,vexpress,config-bus";
437 arm,vexpress,config-bridge = <&v2m_sysreg>;
440 /* MCC static memory clock */
441 compatible = "arm,vexpress-osc";
442 arm,vexpress-sysreg,func = <1 0>;
443 freq-range = <25000000 60000000>;
445 clock-output-names = "v2m:oscclk0";
448 v2m_oscclk1: oscclk1 {
450 compatible = "arm,vexpress-osc";
451 arm,vexpress-sysreg,func = <1 1>;
452 freq-range = <23750000 65000000>;
454 clock-output-names = "v2m:oscclk1";
457 v2m_oscclk2: oscclk2 {
458 /* IO FPGA peripheral clock */
459 compatible = "arm,vexpress-osc";
460 arm,vexpress-sysreg,func = <1 2>;
461 freq-range = <24000000 24000000>;
463 clock-output-names = "v2m:oscclk2";
467 /* Logic level voltage */
468 compatible = "arm,vexpress-volt";
469 arm,vexpress-sysreg,func = <2 0>;
470 regulator-name = "VIO";
476 /* MCC internal operating temperature */
477 compatible = "arm,vexpress-temp";
478 arm,vexpress-sysreg,func = <4 0>;
483 compatible = "arm,vexpress-reset";
484 arm,vexpress-sysreg,func = <5 0>;
488 compatible = "arm,vexpress-muxfpga";
489 arm,vexpress-sysreg,func = <7 0>;
493 compatible = "arm,vexpress-shutdown";
494 arm,vexpress-sysreg,func = <8 0>;
498 compatible = "arm,vexpress-reboot";
499 arm,vexpress-sysreg,func = <9 0>;
503 compatible = "arm,vexpress-dvimode";
504 arm,vexpress-sysreg,func = <11 0>;