arch/arm/boot/dts/vexpress-v2m-rs1.dtsi

   1 /*
   2  * ARM Ltd. Versatile Express
   3  *
   4  * Motherboard Express uATX
   5  * V2M-P1
   6  *
   7  * HBI-0190D
   8  *
   9  * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
  10  * Technical Reference Manual)
  11  *
  12  * WARNING! The hardware described in this file is independent from the
  13  * original variant (vexpress-v2m.dtsi), but there is a strong
  14  * correspondence between the two configurations.
  15  *
  16  * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
  17  * CHANGES TO vexpress-v2m.dtsi!
  18  */
  19
  20 / {
  21         smb@8000000 {
  22                 motherboard {
  23                         model = "V2M-P1";
  24                         arm,hbi = <0x190>;
  25                         arm,vexpress,site = <0>;
  26                         arm,v2m-memory-map = "rs1";
  27                         compatible = "arm,vexpress,v2m-p1", "simple-bus";
  28                         #address-cells = <2>; /* SMB chipselect number and offset */
  29                         #size-cells = <1>;
  30                         #interrupt-cells = <1>;
  31                         ranges;
  32
  33                         flash@0,00000000 {
  34                                 compatible = "arm,vexpress-flash", "cfi-flash";
  35                                 reg = <0 0x00000000 0x04000000>,
  36                                       <4 0x00000000 0x04000000>;
  37                                 bank-width = <4>;
  38                         };
  39
  40                         psram@1,00000000 {
  41                                 compatible = "arm,vexpress-psram", "mtd-ram";
  42                                 reg = <1 0x00000000 0x02000000>;
  43                                 bank-width = <4>;
  44                         };
  45
  46                         v2m_video_ram: vram@2,00000000 {
  47                                 compatible = "arm,vexpress-vram";
  48                                 reg = <2 0x00000000 0x00800000>;
  49                         };
  50
  51                         ethernet@2,02000000 {
  52                                 compatible = "smsc,lan9118", "smsc,lan9115";
  53                                 reg = <2 0x02000000 0x10000>;
  54                                 interrupts = <15>;
  55                                 phy-mode = "mii";
  56                                 reg-io-width = <4>;
  57                                 smsc,irq-active-high;
  58                                 smsc,irq-push-pull;
  59                                 vdd33a-supply = <&v2m_fixed_3v3>;
  60                                 vddvario-supply = <&v2m_fixed_3v3>;
  61                         };
  62
  63                         usb@2,03000000 {
  64                                 compatible = "nxp,usb-isp1761";
  65                                 reg = <2 0x03000000 0x20000>;
  66                                 interrupts = <16>;
  67                                 port1-otg;
  68                         };
  69
  70                         iofpga@3,00000000 {
  71                                 compatible = "simple-bus";
  72                                 #address-cells = <1>;
  73                                 #size-cells = <1>;
  74                                 ranges = <0 3 0 0x200000>;
  75
  76                                 v2m_sysreg: sysreg@10000 {
  77                                         compatible = "arm,vexpress-sysreg";
  78                                         reg = <0x010000 0x1000>;
  79                                         #address-cells = <1>;
  80                                         #size-cells = <1>;
  81                                         ranges = <0 0x10000 0x1000>;
  82
  83                                         v2m_led_gpios: gpio@8 {
  84                                                 compatible = "arm,vexpress-sysreg,sys_led";
  85                                                 reg = <0x008 4>;
  86                                                 gpio-controller;
  87                                                 #gpio-cells = <2>;
  88                                         };
  89
  90                                         v2m_mmc_gpios: gpio@48 {
  91                                                 compatible = "arm,vexpress-sysreg,sys_mci";
  92                                                 reg = <0x048 4>;
  93                                                 gpio-controller;
  94                                                 #gpio-cells = <2>;
  95                                         };
  96
  97                                         v2m_flash_gpios: gpio@4c {
  98                                                 compatible = "arm,vexpress-sysreg,sys_flash";
  99                                                 reg = <0x04c 4>;
 100                                                 gpio-controller;
 101                                                 #gpio-cells = <2>;
 102                                         };
 103                                 };
 104
 105                                 v2m_sysctl: sysctl@20000 {
 106                                         compatible = "arm,sp810", "arm,primecell";
 107                                         reg = <0x020000 0x1000>;
 108                                         clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
 109                                         clock-names = "refclk", "timclk", "apb_pclk";
 110                                         #clock-cells = <1>;
 111                                         clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
 112                                         assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
 113                                         assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
 114                                 };
 115
 116                                 /* PCI-E I2C bus */
 117                                 v2m_i2c_pcie: i2c@30000 {
 118                                         compatible = "arm,versatile-i2c";
 119                                         reg = <0x030000 0x1000>;
 120
 121                                         #address-cells = <1>;
 122                                         #size-cells = <0>;
 123
 124                                         pcie-switch@60 {
 125                                                 compatible = "idt,89hpes32h8";
 126                                                 reg = <0x60>;
 127                                         };
 128                                 };
 129
 130                                 aaci@40000 {
 131                                         compatible = "arm,pl041", "arm,primecell";
 132                                         reg = <0x040000 0x1000>;
 133                                         interrupts = <11>;
 134                                         clocks = <&smbclk>;
 135                                         clock-names = "apb_pclk";
 136                                 };
 137
 138                                 mmci@50000 {
 139                                         compatible = "arm,pl180", "arm,primecell";
 140                                         reg = <0x050000 0x1000>;
 141                                         interrupts = <9 10>;
 142                                         cd-gpios = <&v2m_mmc_gpios 0 0>;
 143                                         wp-gpios = <&v2m_mmc_gpios 1 0>;
 144                                         max-frequency = <12000000>;
 145                                         vmmc-supply = <&v2m_fixed_3v3>;
 146                                         clocks = <&v2m_clk24mhz>, <&smbclk>;
 147                                         clock-names = "mclk", "apb_pclk";
 148                                 };
 149
 150                                 kmi@60000 {
 151                                         compatible = "arm,pl050", "arm,primecell";
 152                                         reg = <0x060000 0x1000>;
 153                                         interrupts = <12>;
 154                                         clocks = <&v2m_clk24mhz>, <&smbclk>;
 155                                         clock-names = "KMIREFCLK", "apb_pclk";
 156                                 };
 157
 158                                 kmi@70000 {
 159                                         compatible = "arm,pl050", "arm,primecell";
 160                                         reg = <0x070000 0x1000>;
 161                                         interrupts = <13>;
 162                                         clocks = <&v2m_clk24mhz>, <&smbclk>;
 163                                         clock-names = "KMIREFCLK", "apb_pclk";
 164                                 };
 165
 166                                 v2m_serial0: uart@90000 {
 167                                         compatible = "arm,pl011", "arm,primecell";
 168                                         reg = <0x090000 0x1000>;
 169                                         interrupts = <5>;
 170                                         clocks = <&v2m_oscclk2>, <&smbclk>;
 171                                         clock-names = "uartclk", "apb_pclk";
 172                                 };
 173
 174                                 v2m_serial1: uart@a0000 {
 175                                         compatible = "arm,pl011", "arm,primecell";
 176                                         reg = <0x0a0000 0x1000>;
 177                                         interrupts = <6>;
 178                                         clocks = <&v2m_oscclk2>, <&smbclk>;
 179                                         clock-names = "uartclk", "apb_pclk";
 180                                 };
 181
 182                                 v2m_serial2: uart@b0000 {
 183                                         compatible = "arm,pl011", "arm,primecell";
 184                                         reg = <0x0b0000 0x1000>;
 185                                         interrupts = <7>;
 186                                         clocks = <&v2m_oscclk2>, <&smbclk>;
 187                                         clock-names = "uartclk", "apb_pclk";
 188                                 };
 189
 190                                 v2m_serial3: uart@c0000 {
 191                                         compatible = "arm,pl011", "arm,primecell";
 192                                         reg = <0x0c0000 0x1000>;
 193                                         interrupts = <8>;
 194                                         clocks = <&v2m_oscclk2>, <&smbclk>;
 195                                         clock-names = "uartclk", "apb_pclk";
 196                                 };
 197
 198                                 wdt@f0000 {
 199                                         compatible = "arm,sp805", "arm,primecell";
 200                                         reg = <0x0f0000 0x1000>;
 201                                         interrupts = <0>;
 202                                         clocks = <&v2m_refclk32khz>, <&smbclk>;
 203                                         clock-names = "wdogclk", "apb_pclk";
 204                                 };
 205
 206                                 v2m_timer01: timer@110000 {
 207                                         compatible = "arm,sp804", "arm,primecell";
 208                                         reg = <0x110000 0x1000>;
 209                                         interrupts = <2>;
 210                                         clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
 211                                         clock-names = "timclken1", "timclken2", "apb_pclk";
 212                                 };
 213
 214                                 v2m_timer23: timer@120000 {
 215                                         compatible = "arm,sp804", "arm,primecell";
 216                                         reg = <0x120000 0x1000>;
 217                                         interrupts = <3>;
 218                                         clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
 219                                         clock-names = "timclken1", "timclken2", "apb_pclk";
 220                                 };
 221
 222                                 /* DVI I2C bus */
 223                                 v2m_i2c_dvi: i2c@160000 {
 224                                         compatible = "arm,versatile-i2c";
 225                                         reg = <0x160000 0x1000>;
 226
 227                                         #address-cells = <1>;
 228                                         #size-cells = <0>;
 229
 230                                         dvi-transmitter@39 {
 231                                                 compatible = "sil,sii9022-tpi", "sil,sii9022";
 232                                                 reg = <0x39>;
 233                                         };
 234
 235                                         dvi-transmitter@60 {
 236                                                 compatible = "sil,sii9022-cpi", "sil,sii9022";
 237                                                 reg = <0x60>;
 238                                         };
 239                                 };
 240
 241                                 rtc@170000 {
 242                                         compatible = "arm,pl031", "arm,primecell";
 243                                         reg = <0x170000 0x1000>;
 244                                         interrupts = <4>;
 245                                         clocks = <&smbclk>;
 246                                         clock-names = "apb_pclk";
 247                                 };
 248
 249                                 compact-flash@1a0000 {
 250                                         compatible = "arm,vexpress-cf", "ata-generic";
 251                                         reg = <0x1a0000 0x100
 252                                                0x1a0100 0xf00>;
 253                                         reg-shift = <2>;
 254                                 };
 255
 256                                 clcd@1f0000 {
 257                                         compatible = "arm,pl111", "arm,primecell";
 258                                         reg = <0x1f0000 0x1000>;
 259                                         interrupt-names = "combined";
 260                                         interrupts = <14>;
 261                                         clocks = <&v2m_oscclk1>, <&smbclk>;
 262                                         clock-names = "clcdclk", "apb_pclk";
 263                                         memory-region = <&v2m_video_ram>;
 264                                         max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */
 265
 266                                         port {
 267                                                 v2m_clcd_pads: endpoint {
 268                                                         remote-endpoint = <&v2m_clcd_panel>;
 269                                                         arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
 270                                                 };
 271                                         };
 272
 273                                         panel {
 274                                                 compatible = "panel-dpi";
 275
 276                                                 port {
 277                                                         v2m_clcd_panel: endpoint {
 278                                                                 remote-endpoint = <&v2m_clcd_pads>;
 279                                                         };
 280                                                 };
 281
 282                                                 panel-timing {
 283                                                         clock-frequency = <25175000>;
 284                                                         hactive = <640>;
 285                                                         hback-porch = <40>;
 286                                                         hfront-porch = <24>;
 287                                                         hsync-len = <96>;
 288                                                         vactive = <480>;
 289                                                         vback-porch = <32>;
 290                                                         vfront-porch = <11>;
 291                                                         vsync-len = <2>;
 292                                                 };
 293                                         };
 294                                 };
 295                         };
 296
 297                         v2m_fixed_3v3: fixed-regulator-0 {
 298                                 compatible = "regulator-fixed";
 299                                 regulator-name = "3V3";
 300                                 regulator-min-microvolt = <3300000>;
 301                                 regulator-max-microvolt = <3300000>;
 302                                 regulator-always-on;
 303                         };
 304
 305                         v2m_clk24mhz: clk24mhz {
 306                                 compatible = "fixed-clock";
 307                                 #clock-cells = <0>;
 308                                 clock-frequency = <24000000>;
 309                                 clock-output-names = "v2m:clk24mhz";
 310                         };
 311
 312                         v2m_refclk1mhz: refclk1mhz {
 313                                 compatible = "fixed-clock";
 314                                 #clock-cells = <0>;
 315                                 clock-frequency = <1000000>;
 316                                 clock-output-names = "v2m:refclk1mhz";
 317                         };
 318
 319                         v2m_refclk32khz: refclk32khz {
 320                                 compatible = "fixed-clock";
 321                                 #clock-cells = <0>;
 322                                 clock-frequency = <32768>;
 323                                 clock-output-names = "v2m:refclk32khz";
 324                         };
 325
 326                         leds {
 327                                 compatible = "gpio-leds";
 328
 329                                 user1 {
 330                                         label = "v2m:green:user1";
 331                                         gpios = <&v2m_led_gpios 0 0>;
 332                                         linux,default-trigger = "heartbeat";
 333                                 };
 334
 335                                 user2 {
 336                                         label = "v2m:green:user2";
 337                                         gpios = <&v2m_led_gpios 1 0>;
 338                                         linux,default-trigger = "mmc0";
 339                                 };
 340
 341                                 user3 {
 342                                         label = "v2m:green:user3";
 343                                         gpios = <&v2m_led_gpios 2 0>;
 344                                         linux,default-trigger = "cpu0";
 345                                 };
 346
 347                                 user4 {
 348                                         label = "v2m:green:user4";
 349                                         gpios = <&v2m_led_gpios 3 0>;
 350                                         linux,default-trigger = "cpu1";
 351                                 };
 352
 353                                 user5 {
 354                                         label = "v2m:green:user5";
 355                                         gpios = <&v2m_led_gpios 4 0>;
 356                                         linux,default-trigger = "cpu2";
 357                                 };
 358
 359                                 user6 {
 360                                         label = "v2m:green:user6";
 361                                         gpios = <&v2m_led_gpios 5 0>;
 362                                         linux,default-trigger = "cpu3";
 363                                 };
 364
 365                                 user7 {
 366                                         label = "v2m:green:user7";
 367                                         gpios = <&v2m_led_gpios 6 0>;
 368                                         linux,default-trigger = "cpu4";
 369                                 };
 370
 371                                 user8 {
 372                                         label = "v2m:green:user8";
 373                                         gpios = <&v2m_led_gpios 7 0>;
 374                                         linux,default-trigger = "cpu5";
 375                                 };
 376                         };
 377
 378                         mcc {
 379                                 compatible = "arm,vexpress,config-bus";
 380                                 arm,vexpress,config-bridge = <&v2m_sysreg>;
 381
 382                                 oscclk0 {
 383                                         /* MCC static memory clock */
 384                                         compatible = "arm,vexpress-osc";
 385                                         arm,vexpress-sysreg,func = <1 0>;
 386                                         freq-range = <25000000 60000000>;
 387                                         #clock-cells = <0>;
 388                                         clock-output-names = "v2m:oscclk0";
 389                                 };
 390
 391                                 v2m_oscclk1: oscclk1 {
 392                                         /* CLCD clock */
 393                                         compatible = "arm,vexpress-osc";
 394                                         arm,vexpress-sysreg,func = <1 1>;
 395                                         freq-range = <23750000 65000000>;
 396                                         #clock-cells = <0>;
 397                                         clock-output-names = "v2m:oscclk1";
 398                                 };
 399
 400                                 v2m_oscclk2: oscclk2 {
 401                                         /* IO FPGA peripheral clock */
 402                                         compatible = "arm,vexpress-osc";
 403                                         arm,vexpress-sysreg,func = <1 2>;
 404                                         freq-range = <24000000 24000000>;
 405                                         #clock-cells = <0>;
 406                                         clock-output-names = "v2m:oscclk2";
 407                                 };
 408
 409                                 volt-vio {
 410                                         /* Logic level voltage */
 411                                         compatible = "arm,vexpress-volt";
 412                                         arm,vexpress-sysreg,func = <2 0>;
 413                                         regulator-name = "VIO";
 414                                         regulator-always-on;
 415                                         label = "VIO";
 416                                 };
 417
 418                                 temp-mcc {
 419                                         /* MCC internal operating temperature */
 420                                         compatible = "arm,vexpress-temp";
 421                                         arm,vexpress-sysreg,func = <4 0>;
 422                                         label = "MCC";
 423                                 };
 424
 425                                 reset {
 426                                         compatible = "arm,vexpress-reset";
 427                                         arm,vexpress-sysreg,func = <5 0>;
 428                                 };
 429
 430                                 muxfpga {
 431                                         compatible = "arm,vexpress-muxfpga";
 432                                         arm,vexpress-sysreg,func = <7 0>;
 433                                 };
 434
 435                                 shutdown {
 436                                         compatible = "arm,vexpress-shutdown";
 437                                         arm,vexpress-sysreg,func = <8 0>;
 438                                 };
 439
 440                                 reboot {
 441                                         compatible = "arm,vexpress-reboot";
 442                                         arm,vexpress-sysreg,func = <9 0>;
 443                                 };
 444
 445                                 dvimode {
 446                                         compatible = "arm,vexpress-dvimode";
 447                                         arm,vexpress-sysreg,func = <11 0>;
 448                                 };
 449                         };
 450                 };
 451         };
 452 };