2 /include/ "skeleton.dtsi"
5 model = "ARM Versatile AB";
6 compatible = "arm,versatile-ab";
9 interrupt-parent = <&vic>;
23 reg = <0x0 0x08000000>;
26 xtal24mhz: xtal24mhz@24M {
28 compatible = "fixed-clock";
29 clock-frequency = <24000000>;
32 core-module@10000000 {
33 compatible = "arm,core-module-versatile", "syscon";
34 reg = <0x10000000 0x200>;
36 /* OSC1 on AB, OSC4 on PB */
37 osc1: cm_aux_osc@24M {
39 compatible = "arm,versatile-cm-auxosc";
40 clocks = <&xtal24mhz>;
43 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
46 compatible = "fixed-factor-clock";
49 clocks = <&xtal24mhz>;
54 compatible = "fixed-factor-clock";
57 clocks = <&xtal24mhz>;
62 compatible = "arm,versatile-flash";
63 reg = <0x34000000 0x4000000>;
70 compatible = "arm,versatile-i2c";
71 reg = <0x10002000 0x1000>;
74 compatible = "dallas,ds1338";
80 compatible = "smsc,lan91c111";
81 reg = <0x10010000 0x10000>;
86 compatible = "arm,versatile-lcd";
87 reg = <0x10008000 0x1000>;
91 compatible = "arm,amba-bus";
96 vic: interrupt-controller@10140000 {
97 compatible = "arm,versatile-vic";
99 #interrupt-cells = <1>;
100 reg = <0x10140000 0x1000>;
101 valid-mask = <0xffffffff>;
104 sic: interrupt-controller@10003000 {
105 compatible = "arm,versatile-sic";
106 interrupt-controller;
107 #interrupt-cells = <1>;
108 reg = <0x10003000 0x1000>;
109 interrupt-parent = <&vic>;
110 interrupts = <31>; /* Cascaded to vic */
111 clear-mask = <0xffffffff>;
113 * Valid interrupt lines mask according to
114 * table 4-36 page 4-50 of ARM DUI 0225D
116 valid-mask = <0x0760031b>;
120 compatible = "arm,pl081", "arm,primecell";
121 reg = <0x10130000 0x1000>;
124 clock-names = "apb_pclk";
127 uart0: uart@101f1000 {
128 compatible = "arm,pl011", "arm,primecell";
129 reg = <0x101f1000 0x1000>;
131 clocks = <&xtal24mhz>, <&pclk>;
132 clock-names = "uartclk", "apb_pclk";
135 uart1: uart@101f2000 {
136 compatible = "arm,pl011", "arm,primecell";
137 reg = <0x101f2000 0x1000>;
139 clocks = <&xtal24mhz>, <&pclk>;
140 clock-names = "uartclk", "apb_pclk";
143 uart2: uart@101f3000 {
144 compatible = "arm,pl011", "arm,primecell";
145 reg = <0x101f3000 0x1000>;
147 clocks = <&xtal24mhz>, <&pclk>;
148 clock-names = "uartclk", "apb_pclk";
152 compatible = "arm,primecell";
153 reg = <0x10100000 0x1000>;
155 clock-names = "apb_pclk";
159 compatible = "arm,primecell";
160 reg = <0x10110000 0x1000>;
162 clock-names = "apb_pclk";
166 compatible = "arm,pl110", "arm,primecell";
167 reg = <0x10120000 0x1000>;
169 clocks = <&osc1>, <&pclk>;
170 clock-names = "clcd", "apb_pclk";
174 compatible = "arm,primecell";
175 reg = <0x101e0000 0x1000>;
177 clock-names = "apb_pclk";
181 compatible = "arm,primecell";
182 reg = <0x101e1000 0x1000>;
185 clock-names = "apb_pclk";
189 compatible = "arm,sp804", "arm,primecell";
190 reg = <0x101e2000 0x1000>;
192 clocks = <&timclk>, <&timclk>, <&pclk>;
193 clock-names = "timer0", "timer1", "apb_pclk";
197 compatible = "arm,sp804", "arm,primecell";
198 reg = <0x101e3000 0x1000>;
200 clocks = <&timclk>, <&timclk>, <&pclk>;
201 clock-names = "timer0", "timer1", "apb_pclk";
204 gpio0: gpio@101e4000 {
205 compatible = "arm,pl061", "arm,primecell";
206 reg = <0x101e4000 0x1000>;
210 interrupt-controller;
211 #interrupt-cells = <2>;
213 clock-names = "apb_pclk";
216 gpio1: gpio@101e5000 {
217 compatible = "arm,pl061", "arm,primecell";
218 reg = <0x101e5000 0x1000>;
222 interrupt-controller;
223 #interrupt-cells = <2>;
225 clock-names = "apb_pclk";
229 compatible = "arm,pl030", "arm,primecell";
230 reg = <0x101e8000 0x1000>;
233 clock-names = "apb_pclk";
237 compatible = "arm,primecell";
238 reg = <0x101f0000 0x1000>;
241 clock-names = "apb_pclk";
245 compatible = "arm,pl022", "arm,primecell";
246 reg = <0x101f4000 0x1000>;
248 clocks = <&xtal24mhz>, <&pclk>;
249 clock-names = "SSPCLK", "apb_pclk";
253 compatible = "arm,versatile-fpga", "simple-bus";
254 #address-cells = <1>;
256 ranges = <0 0x10000000 0x10000>;
259 compatible = "arm,versatile-sysreg", "syscon";
260 reg = <0x00000 0x1000>;
264 compatible = "arm,primecell";
265 reg = <0x4000 0x1000>;
268 clock-names = "apb_pclk";
271 compatible = "arm,pl180", "arm,primecell";
272 reg = <0x5000 0x1000>;
273 interrupts-extended = <&vic 22 &sic 1>;
274 clocks = <&xtal24mhz>, <&pclk>;
275 clock-names = "mclk", "apb_pclk";
278 compatible = "arm,pl050", "arm,primecell";
279 reg = <0x6000 0x1000>;
280 interrupt-parent = <&sic>;
282 clocks = <&xtal24mhz>, <&pclk>;
283 clock-names = "KMIREFCLK", "apb_pclk";
286 compatible = "arm,pl050", "arm,primecell";
287 reg = <0x7000 0x1000>;
288 interrupt-parent = <&sic>;
290 clocks = <&xtal24mhz>, <&pclk>;
291 clock-names = "KMIREFCLK", "apb_pclk";