1 // SPDX-License-Identifier: GPL-2.0
5 model = "ARM Versatile AB";
6 compatible = "arm,versatile-ab";
9 interrupt-parent = <&vic>;
23 device_type = "memory";
24 reg = <0x0 0x08000000>;
27 xtal24mhz: xtal24mhz@24M {
29 compatible = "fixed-clock";
30 clock-frequency = <24000000>;
34 compatible = "ti,ths8134b", "ti,ths8134";
45 vga_bridge_in: endpoint {
46 remote-endpoint = <&clcd_pads_vga_dac>;
53 vga_bridge_out: endpoint {
54 remote-endpoint = <&vga_con_in>;
61 compatible = "vga-connector";
64 vga_con_in: endpoint {
65 remote-endpoint = <&vga_bridge_out>;
70 core-module@10000000 {
71 compatible = "arm,core-module-versatile", "syscon", "simple-mfd";
72 reg = <0x10000000 0x200>;
75 compatible = "register-bit-led";
78 label = "versatile:0";
79 linux,default-trigger = "heartbeat";
83 compatible = "register-bit-led";
86 label = "versatile:1";
87 linux,default-trigger = "mmc0";
88 default-state = "off";
91 compatible = "register-bit-led";
94 label = "versatile:2";
95 linux,default-trigger = "cpu0";
96 default-state = "off";
99 compatible = "register-bit-led";
102 label = "versatile:3";
103 default-state = "off";
106 compatible = "register-bit-led";
109 label = "versatile:4";
110 default-state = "off";
113 compatible = "register-bit-led";
116 label = "versatile:5";
117 default-state = "off";
120 compatible = "register-bit-led";
123 label = "versatile:6";
124 default-state = "off";
127 compatible = "register-bit-led";
130 label = "versatile:7";
131 default-state = "off";
134 /* OSC1 on AB, OSC4 on PB */
135 osc1: cm_aux_osc@24M {
137 compatible = "arm,versatile-cm-auxosc";
138 clocks = <&xtal24mhz>;
141 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
144 compatible = "fixed-factor-clock";
147 clocks = <&xtal24mhz>;
152 compatible = "fixed-factor-clock";
155 clocks = <&xtal24mhz>;
160 /* 64 MiB NOR flash in non-interleaved chips */
161 compatible = "arm,versatile-flash", "cfi-flash";
162 reg = <0x34000000 0x04000000>;
165 compatible = "arm,arm-firmware-suite";
170 #address-cells = <1>;
172 compatible = "arm,versatile-i2c";
173 reg = <0x10002000 0x1000>;
176 compatible = "dallas,ds1338";
182 compatible = "smsc,lan91c111";
183 reg = <0x10010000 0x10000>;
188 compatible = "arm,versatile-lcd";
189 reg = <0x10008000 0x1000>;
193 compatible = "simple-bus";
194 #address-cells = <1>;
198 vic: interrupt-controller@10140000 {
199 compatible = "arm,versatile-vic";
200 interrupt-controller;
201 #interrupt-cells = <1>;
202 reg = <0x10140000 0x1000>;
203 valid-mask = <0xffffffff>;
206 sic: interrupt-controller@10003000 {
207 compatible = "arm,versatile-sic";
208 interrupt-controller;
209 #interrupt-cells = <1>;
210 reg = <0x10003000 0x1000>;
211 interrupt-parent = <&vic>;
212 interrupts = <31>; /* Cascaded to vic */
213 clear-mask = <0xffffffff>;
215 * Valid interrupt lines mask according to
216 * table 4-36 page 4-50 of ARM DUI 0225D
218 valid-mask = <0x0760031b>;
222 compatible = "arm,pl081", "arm,primecell";
223 reg = <0x10130000 0x1000>;
226 clock-names = "apb_pclk";
229 uart0: uart@101f1000 {
230 compatible = "arm,pl011", "arm,primecell";
231 reg = <0x101f1000 0x1000>;
233 clocks = <&xtal24mhz>, <&pclk>;
234 clock-names = "uartclk", "apb_pclk";
237 uart1: uart@101f2000 {
238 compatible = "arm,pl011", "arm,primecell";
239 reg = <0x101f2000 0x1000>;
241 clocks = <&xtal24mhz>, <&pclk>;
242 clock-names = "uartclk", "apb_pclk";
245 uart2: uart@101f3000 {
246 compatible = "arm,pl011", "arm,primecell";
247 reg = <0x101f3000 0x1000>;
249 clocks = <&xtal24mhz>, <&pclk>;
250 clock-names = "uartclk", "apb_pclk";
254 compatible = "arm,primecell";
255 reg = <0x10100000 0x1000>;
257 clock-names = "apb_pclk";
261 compatible = "arm,primecell";
262 reg = <0x10110000 0x1000>;
264 clock-names = "apb_pclk";
268 compatible = "arm,pl110", "arm,primecell";
269 reg = <0x10120000 0x1000>;
271 clocks = <&osc1>, <&pclk>;
272 clock-names = "clcdclk", "apb_pclk";
273 /* 800x600 16bpp @ 36MHz works fine */
274 max-memory-bandwidth = <54000000>;
277 * This port is routed through a PLD (Programmable
278 * Logic Device) that routes the output from the CLCD
279 * (after transformations) to the VGA DAC and also an
280 * external panel connector. The PLD is essential for
281 * supporting RGB565/BGR565.
283 * The signals from the port thus reaches two endpoints.
284 * The PLD is managed through a few special bits in the
287 * This arrangement can be clearly seen in
288 * ARM DUI 0225D, page 3-41, figure 3-19.
291 #address-cells = <1>;
294 clcd_pads_panel: endpoint@0 {
296 remote-endpoint = <&panel_in>;
297 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
299 clcd_pads_vga_dac: endpoint@1 {
301 remote-endpoint = <&vga_bridge_in>;
302 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
308 compatible = "arm,primecell";
309 reg = <0x101e0000 0x1000>;
311 clock-names = "apb_pclk";
315 compatible = "arm,primecell";
316 reg = <0x101e1000 0x1000>;
319 clock-names = "apb_pclk";
323 compatible = "arm,sp804", "arm,primecell";
324 reg = <0x101e2000 0x1000>;
326 clocks = <&timclk>, <&timclk>, <&pclk>;
327 clock-names = "timer0", "timer1", "apb_pclk";
331 compatible = "arm,sp804", "arm,primecell";
332 reg = <0x101e3000 0x1000>;
334 clocks = <&timclk>, <&timclk>, <&pclk>;
335 clock-names = "timer0", "timer1", "apb_pclk";
338 gpio0: gpio@101e4000 {
339 compatible = "arm,pl061", "arm,primecell";
340 reg = <0x101e4000 0x1000>;
344 interrupt-controller;
345 #interrupt-cells = <2>;
347 clock-names = "apb_pclk";
350 gpio1: gpio@101e5000 {
351 compatible = "arm,pl061", "arm,primecell";
352 reg = <0x101e5000 0x1000>;
356 interrupt-controller;
357 #interrupt-cells = <2>;
359 clock-names = "apb_pclk";
363 compatible = "arm,pl030", "arm,primecell";
364 reg = <0x101e8000 0x1000>;
367 clock-names = "apb_pclk";
371 compatible = "arm,primecell";
372 reg = <0x101f0000 0x1000>;
375 clock-names = "apb_pclk";
379 compatible = "arm,pl022", "arm,primecell";
380 reg = <0x101f4000 0x1000>;
382 clocks = <&xtal24mhz>, <&pclk>;
383 clock-names = "SSPCLK", "apb_pclk";
387 compatible = "arm,versatile-fpga", "simple-bus";
388 #address-cells = <1>;
390 ranges = <0 0x10000000 0x10000>;
393 compatible = "arm,versatile-sysreg", "syscon", "simple-mfd";
394 reg = <0x00000 0x1000>;
397 compatible = "arm,versatile-tft-panel";
401 remote-endpoint = <&clcd_pads_panel>;
408 compatible = "arm,primecell";
409 reg = <0x4000 0x1000>;
412 clock-names = "apb_pclk";
415 compatible = "arm,pl180", "arm,primecell";
416 reg = <0x5000 0x1000>;
417 interrupts-extended = <&vic 22 &sic 1>;
418 clocks = <&xtal24mhz>, <&pclk>;
419 clock-names = "mclk", "apb_pclk";
422 compatible = "arm,pl050", "arm,primecell";
423 reg = <0x6000 0x1000>;
424 interrupt-parent = <&sic>;
426 clocks = <&xtal24mhz>, <&pclk>;
427 clock-names = "KMIREFCLK", "apb_pclk";
430 compatible = "arm,pl050", "arm,primecell";
431 reg = <0x7000 0x1000>;
432 interrupt-parent = <&sic>;
434 clocks = <&xtal24mhz>, <&pclk>;
435 clock-names = "KMIREFCLK", "apb_pclk";