arch/arm/boot/dts/versatile-ab.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3
   4 / {
   5         model = "ARM Versatile AB";
   6         compatible = "arm,versatile-ab";
   7         #address-cells = <1>;
   8         #size-cells = <1>;
   9         interrupt-parent = <&vic>;
  10
  11         aliases {
  12                 serial0 = &uart0;
  13                 serial1 = &uart1;
  14                 serial2 = &uart2;
  15                 i2c0 = &i2c0;
  16         };
  17
  18         chosen {
  19                 stdout-path = &uart0;
  20         };
  21
  22         memory {
  23                 device_type = "memory";
  24                 reg = <0x0 0x08000000>;
  25         };
  26
  27         xtal24mhz: xtal24mhz@24M {
  28                 #clock-cells = <0>;
  29                 compatible = "fixed-clock";
  30                 clock-frequency = <24000000>;
  31         };
  32
  33         bridge {
  34                 compatible = "ti,ths8134b", "ti,ths8134";
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 ports {
  39                         #address-cells = <1>;
  40                         #size-cells = <0>;
  41
  42                         port@0 {
  43                                 reg = <0>;
  44
  45                                 vga_bridge_in: endpoint {
  46                                         remote-endpoint = <&clcd_pads_vga_dac>;
  47                                 };
  48                         };
  49
  50                         port@1 {
  51                                 reg = <1>;
  52
  53                                 vga_bridge_out: endpoint {
  54                                         remote-endpoint = <&vga_con_in>;
  55                                 };
  56                         };
  57                 };
  58         };
  59
  60         vga {
  61                 compatible = "vga-connector";
  62
  63                 port {
  64                         vga_con_in: endpoint {
  65                                 remote-endpoint = <&vga_bridge_out>;
  66                         };
  67                 };
  68         };
  69
  70         core-module@10000000 {
  71                 compatible = "arm,core-module-versatile", "syscon", "simple-mfd";
  72                 reg = <0x10000000 0x200>;
  73                 ranges = <0x0 0x10000000 0x200>;
  74                 #address-cells = <1>;
  75                 #size-cells = <1>;
  76
  77                 led@8,0 {
  78                         compatible = "register-bit-led";
  79                         reg = <0x08 0x04>;
  80                         offset = <0x08>;
  81                         mask = <0x01>;
  82                         label = "versatile:0";
  83                         linux,default-trigger = "heartbeat";
  84                         default-state = "on";
  85                 };
  86                 led@8,1 {
  87                         compatible = "register-bit-led";
  88                         reg = <0x08 0x04>;
  89                         offset = <0x08>;
  90                         mask = <0x02>;
  91                         label = "versatile:1";
  92                         linux,default-trigger = "mmc0";
  93                         default-state = "off";
  94                 };
  95                 led@8,2 {
  96                         compatible = "register-bit-led";
  97                         reg = <0x08 0x04>;
  98                         offset = <0x08>;
  99                         mask = <0x04>;
 100                         label = "versatile:2";
 101                         linux,default-trigger = "cpu0";
 102                         default-state = "off";
 103                 };
 104                 led@8,3 {
 105                         compatible = "register-bit-led";
 106                         reg = <0x08 0x04>;
 107                         offset = <0x08>;
 108                         mask = <0x08>;
 109                         label = "versatile:3";
 110                         default-state = "off";
 111                 };
 112                 led@8,4 {
 113                         compatible = "register-bit-led";
 114                         reg = <0x08 0x04>;
 115                         offset = <0x08>;
 116                         mask = <0x10>;
 117                         label = "versatile:4";
 118                         default-state = "off";
 119                 };
 120                 led@8,5 {
 121                         compatible = "register-bit-led";
 122                         reg = <0x08 0x04>;
 123                         offset = <0x08>;
 124                         mask = <0x20>;
 125                         label = "versatile:5";
 126                         default-state = "off";
 127                 };
 128                 led@8,6 {
 129                         compatible = "register-bit-led";
 130                         reg = <0x08 0x04>;
 131                         offset = <0x08>;
 132                         mask = <0x40>;
 133                         label = "versatile:6";
 134                         default-state = "off";
 135                 };
 136                 led@8,7 {
 137                         compatible = "register-bit-led";
 138                         reg = <0x08 0x04>;
 139                         offset = <0x08>;
 140                         mask = <0x80>;
 141                         label = "versatile:7";
 142                         default-state = "off";
 143                 };
 144
 145                 /* OSC1 on AB, OSC4 on PB */
 146                 osc1: cm_aux_osc@24M {
 147                         #clock-cells = <0>;
 148                         compatible = "arm,versatile-cm-auxosc";
 149                         clocks = <&xtal24mhz>;
 150                 };
 151
 152                 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
 153                 timclk: timclk@1M {
 154                         #clock-cells = <0>;
 155                         compatible = "fixed-factor-clock";
 156                         clock-div = <24>;
 157                         clock-mult = <1>;
 158                         clocks = <&xtal24mhz>;
 159                 };
 160
 161                 pclk: pclk@24M {
 162                         #clock-cells = <0>;
 163                         compatible = "fixed-factor-clock";
 164                         clock-div = <1>;
 165                         clock-mult = <1>;
 166                         clocks = <&xtal24mhz>;
 167                 };
 168         };
 169
 170         flash@34000000 {
 171                 /* 64 MiB NOR flash in non-interleaved chips */
 172                 compatible = "arm,versatile-flash", "cfi-flash";
 173                 reg = <0x34000000 0x04000000>;
 174                 bank-width = <4>;
 175                 partitions {
 176                         compatible = "arm,arm-firmware-suite";
 177                 };
 178         };
 179
 180         i2c0: i2c@10002000 {
 181                 #address-cells = <1>;
 182                 #size-cells = <0>;
 183                 compatible = "arm,versatile-i2c";
 184                 reg = <0x10002000 0x1000>;
 185
 186                 rtc@68 {
 187                         compatible = "dallas,ds1338";
 188                         reg = <0x68>;
 189                 };
 190         };
 191
 192         net@10010000 {
 193                 compatible = "smsc,lan91c111";
 194                 reg = <0x10010000 0x10000>;
 195                 interrupts = <25>;
 196         };
 197
 198         lcd@10008000 {
 199                 compatible = "arm,versatile-lcd";
 200                 reg = <0x10008000 0x1000>;
 201         };
 202
 203         amba {
 204                 compatible = "simple-bus";
 205                 #address-cells = <1>;
 206                 #size-cells = <1>;
 207                 ranges;
 208
 209                 vic: interrupt-controller@10140000 {
 210                         compatible = "arm,versatile-vic";
 211                         interrupt-controller;
 212                         #interrupt-cells = <1>;
 213                         reg = <0x10140000 0x1000>;
 214                         valid-mask = <0xffffffff>;
 215                 };
 216
 217                 sic: interrupt-controller@10003000 {
 218                         compatible = "arm,versatile-sic";
 219                         interrupt-controller;
 220                         #interrupt-cells = <1>;
 221                         reg = <0x10003000 0x1000>;
 222                         interrupt-parent = <&vic>;
 223                         interrupts = <31>; /* Cascaded to vic */
 224                         clear-mask = <0xffffffff>;
 225                         /*
 226                          * Valid interrupt lines mask according to
 227                          * table 4-36 page 4-50 of ARM DUI 0225D
 228                          */
 229                         valid-mask = <0x0760031b>;
 230                 };
 231
 232                 dma@10130000 {
 233                         compatible = "arm,pl081", "arm,primecell";
 234                         reg = <0x10130000 0x1000>;
 235                         interrupts = <17>;
 236                         clocks = <&pclk>;
 237                         clock-names = "apb_pclk";
 238                 };
 239
 240                 uart0: uart@101f1000 {
 241                         compatible = "arm,pl011", "arm,primecell";
 242                         reg = <0x101f1000 0x1000>;
 243                         interrupts = <12>;
 244                         clocks = <&xtal24mhz>, <&pclk>;
 245                         clock-names = "uartclk", "apb_pclk";
 246                 };
 247
 248                 uart1: uart@101f2000 {
 249                         compatible = "arm,pl011", "arm,primecell";
 250                         reg = <0x101f2000 0x1000>;
 251                         interrupts = <13>;
 252                         clocks = <&xtal24mhz>, <&pclk>;
 253                         clock-names = "uartclk", "apb_pclk";
 254                 };
 255
 256                 uart2: uart@101f3000 {
 257                         compatible = "arm,pl011", "arm,primecell";
 258                         reg = <0x101f3000 0x1000>;
 259                         interrupts = <14>;
 260                         clocks = <&xtal24mhz>, <&pclk>;
 261                         clock-names = "uartclk", "apb_pclk";
 262                 };
 263
 264                 smc@10100000 {
 265                         compatible = "arm,primecell";
 266                         reg = <0x10100000 0x1000>;
 267                         clocks = <&pclk>;
 268                         clock-names = "apb_pclk";
 269                 };
 270
 271                 mpmc@10110000 {
 272                         compatible = "arm,primecell";
 273                         reg = <0x10110000 0x1000>;
 274                         clocks = <&pclk>;
 275                         clock-names = "apb_pclk";
 276                 };
 277
 278                 display@10120000 {
 279                         compatible = "arm,pl110", "arm,primecell";
 280                         reg = <0x10120000 0x1000>;
 281                         interrupts = <16>;
 282                         clocks = <&osc1>, <&pclk>;
 283                         clock-names = "clcdclk", "apb_pclk";
 284                         /* 800x600 16bpp @ 36MHz works fine */
 285                         max-memory-bandwidth = <54000000>;
 286
 287                         /*
 288                          * This port is routed through a PLD (Programmable
 289                          * Logic Device) that routes the output from the CLCD
 290                          * (after transformations) to the VGA DAC and also an
 291                          * external panel connector. The PLD is essential for
 292                          * supporting RGB565/BGR565.
 293                          *
 294                          * The signals from the port thus reaches two endpoints.
 295                          * The PLD is managed through a few special bits in the
 296                          * FPGA "sysreg".
 297                          *
 298                          * This arrangement can be clearly seen in
 299                          * ARM DUI 0225D, page 3-41, figure 3-19.
 300                          */
 301                         port@0 {
 302                                 #address-cells = <1>;
 303                                 #size-cells = <0>;
 304
 305                                 clcd_pads_panel: endpoint@0 {
 306                                         reg = <0>;
 307                                         remote-endpoint = <&panel_in>;
 308                                         arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
 309                                 };
 310                                 clcd_pads_vga_dac: endpoint@1 {
 311                                         reg = <1>;
 312                                         remote-endpoint = <&vga_bridge_in>;
 313                                         arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
 314                                 };
 315                         };
 316                 };
 317
 318                 sctl@101e0000 {
 319                         compatible = "arm,primecell";
 320                         reg = <0x101e0000 0x1000>;
 321                         clocks = <&pclk>;
 322                         clock-names = "apb_pclk";
 323                 };
 324
 325                 watchdog@101e1000 {
 326                         compatible = "arm,primecell";
 327                         reg = <0x101e1000 0x1000>;
 328                         interrupts = <0>;
 329                         clocks = <&pclk>;
 330                         clock-names = "apb_pclk";
 331                 };
 332
 333                 timer@101e2000 {
 334                         compatible = "arm,sp804", "arm,primecell";
 335                         reg = <0x101e2000 0x1000>;
 336                         interrupts = <4>;
 337                         clocks = <&timclk>, <&timclk>, <&pclk>;
 338                         clock-names = "timer0", "timer1", "apb_pclk";
 339                 };
 340
 341                 timer@101e3000 {
 342                         compatible = "arm,sp804", "arm,primecell";
 343                         reg = <0x101e3000 0x1000>;
 344                         interrupts = <5>;
 345                         clocks = <&timclk>, <&timclk>, <&pclk>;
 346                         clock-names = "timer0", "timer1", "apb_pclk";
 347                 };
 348
 349                 gpio0: gpio@101e4000 {
 350                         compatible = "arm,pl061", "arm,primecell";
 351                         reg = <0x101e4000 0x1000>;
 352                         gpio-controller;
 353                         interrupts = <6>;
 354                         #gpio-cells = <2>;
 355                         interrupt-controller;
 356                         #interrupt-cells = <2>;
 357                         clocks = <&pclk>;
 358                         clock-names = "apb_pclk";
 359                 };
 360
 361                 gpio1: gpio@101e5000 {
 362                         compatible = "arm,pl061", "arm,primecell";
 363                         reg = <0x101e5000 0x1000>;
 364                         interrupts = <7>;
 365                         gpio-controller;
 366                         #gpio-cells = <2>;
 367                         interrupt-controller;
 368                         #interrupt-cells = <2>;
 369                         clocks = <&pclk>;
 370                         clock-names = "apb_pclk";
 371                 };
 372
 373                 rtc@101e8000 {
 374                         compatible = "arm,pl030", "arm,primecell";
 375                         reg = <0x101e8000 0x1000>;
 376                         interrupts = <10>;
 377                         clocks = <&pclk>;
 378                         clock-names = "apb_pclk";
 379                 };
 380
 381                 sci@101f0000 {
 382                         compatible = "arm,primecell";
 383                         reg = <0x101f0000 0x1000>;
 384                         interrupts = <15>;
 385                         clocks = <&pclk>;
 386                         clock-names = "apb_pclk";
 387                 };
 388
 389                 spi@101f4000 {
 390                         compatible = "arm,pl022", "arm,primecell";
 391                         reg = <0x101f4000 0x1000>;
 392                         interrupts = <11>;
 393                         clocks = <&xtal24mhz>, <&pclk>;
 394                         clock-names = "sspclk", "apb_pclk";
 395                 };
 396
 397                 fpga {
 398                         compatible = "arm,versatile-fpga", "simple-bus";
 399                         #address-cells = <1>;
 400                         #size-cells = <1>;
 401                         ranges = <0 0x10000000 0x10000>;
 402
 403                         sysreg@0 {
 404                                 compatible = "arm,versatile-sysreg", "syscon", "simple-mfd";
 405                                 reg = <0x00000 0x1000>;
 406
 407                                 panel: display@0 {
 408                                         compatible = "arm,versatile-tft-panel";
 409
 410                                         port {
 411                                                 panel_in: endpoint {
 412                                                         remote-endpoint = <&clcd_pads_panel>;
 413                                                 };
 414                                         };
 415                                 };
 416                         };
 417
 418                         aaci@4000 {
 419                                 compatible = "arm,primecell";
 420                                 reg = <0x4000 0x1000>;
 421                                 interrupts = <24>;
 422                                 clocks = <&pclk>;
 423                                 clock-names = "apb_pclk";
 424                         };
 425                         mmc@5000 {
 426                                 compatible = "arm,pl180", "arm,primecell";
 427                                 reg = <0x5000 0x1000>;
 428                                 interrupts-extended = <&vic 22 &sic 1>;
 429                                 clocks = <&xtal24mhz>, <&pclk>;
 430                                 clock-names = "mclk", "apb_pclk";
 431                         };
 432                         kmi@6000 {
 433                                 compatible = "arm,pl050", "arm,primecell";
 434                                 reg = <0x6000 0x1000>;
 435                                 interrupt-parent = <&sic>;
 436                                 interrupts = <3>;
 437                                 clocks = <&xtal24mhz>, <&pclk>;
 438                                 clock-names = "KMIREFCLK", "apb_pclk";
 439                         };
 440                         kmi@7000 {
 441                                 compatible = "arm,pl050", "arm,primecell";
 442                                 reg = <0x7000 0x1000>;
 443                                 interrupt-parent = <&sic>;
 444                                 interrupts = <4>;
 445                                 clocks = <&xtal24mhz>, <&pclk>;
 446                                 clock-names = "KMIREFCLK", "apb_pclk";
 447                         };
 448                 };
 449         };
 450 };