1 // SPDX-License-Identifier: GPL-2.0
3 /include/ "skeleton.dtsi"
6 model = "ARM Versatile AB";
7 compatible = "arm,versatile-ab";
10 interrupt-parent = <&vic>;
24 reg = <0x0 0x08000000>;
27 xtal24mhz: xtal24mhz@24M {
29 compatible = "fixed-clock";
30 clock-frequency = <24000000>;
34 compatible = "ti,ths8134b", "ti,ths8134";
45 vga_bridge_in: endpoint {
46 remote-endpoint = <&clcd_pads_vga_dac>;
53 vga_bridge_out: endpoint {
54 remote-endpoint = <&vga_con_in>;
61 compatible = "vga-connector";
64 vga_con_in: endpoint {
65 remote-endpoint = <&vga_bridge_out>;
70 core-module@10000000 {
71 compatible = "arm,core-module-versatile", "syscon", "simple-mfd";
72 reg = <0x10000000 0x200>;
75 compatible = "register-bit-led";
78 label = "versatile:0";
79 linux,default-trigger = "heartbeat";
83 compatible = "register-bit-led";
86 label = "versatile:1";
87 linux,default-trigger = "mmc0";
88 default-state = "off";
91 compatible = "register-bit-led";
94 label = "versatile:2";
95 linux,default-trigger = "cpu0";
96 default-state = "off";
99 compatible = "register-bit-led";
102 label = "versatile:3";
103 default-state = "off";
106 compatible = "register-bit-led";
109 label = "versatile:4";
110 default-state = "off";
113 compatible = "register-bit-led";
116 label = "versatile:5";
117 default-state = "off";
120 compatible = "register-bit-led";
123 label = "versatile:6";
124 default-state = "off";
127 compatible = "register-bit-led";
130 label = "versatile:7";
131 default-state = "off";
134 /* OSC1 on AB, OSC4 on PB */
135 osc1: cm_aux_osc@24M {
137 compatible = "arm,versatile-cm-auxosc";
138 clocks = <&xtal24mhz>;
141 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
144 compatible = "fixed-factor-clock";
147 clocks = <&xtal24mhz>;
152 compatible = "fixed-factor-clock";
155 clocks = <&xtal24mhz>;
160 /* 64 MiB NOR flash in non-interleaved chips */
161 compatible = "arm,versatile-flash", "cfi-flash";
162 reg = <0x34000000 0x04000000>;
167 #address-cells = <1>;
169 compatible = "arm,versatile-i2c";
170 reg = <0x10002000 0x1000>;
173 compatible = "dallas,ds1338";
179 compatible = "smsc,lan91c111";
180 reg = <0x10010000 0x10000>;
185 compatible = "arm,versatile-lcd";
186 reg = <0x10008000 0x1000>;
190 compatible = "simple-bus";
191 #address-cells = <1>;
195 vic: interrupt-controller@10140000 {
196 compatible = "arm,versatile-vic";
197 interrupt-controller;
198 #interrupt-cells = <1>;
199 reg = <0x10140000 0x1000>;
200 valid-mask = <0xffffffff>;
203 sic: interrupt-controller@10003000 {
204 compatible = "arm,versatile-sic";
205 interrupt-controller;
206 #interrupt-cells = <1>;
207 reg = <0x10003000 0x1000>;
208 interrupt-parent = <&vic>;
209 interrupts = <31>; /* Cascaded to vic */
210 clear-mask = <0xffffffff>;
212 * Valid interrupt lines mask according to
213 * table 4-36 page 4-50 of ARM DUI 0225D
215 valid-mask = <0x0760031b>;
219 compatible = "arm,pl081", "arm,primecell";
220 reg = <0x10130000 0x1000>;
223 clock-names = "apb_pclk";
226 uart0: uart@101f1000 {
227 compatible = "arm,pl011", "arm,primecell";
228 reg = <0x101f1000 0x1000>;
230 clocks = <&xtal24mhz>, <&pclk>;
231 clock-names = "uartclk", "apb_pclk";
234 uart1: uart@101f2000 {
235 compatible = "arm,pl011", "arm,primecell";
236 reg = <0x101f2000 0x1000>;
238 clocks = <&xtal24mhz>, <&pclk>;
239 clock-names = "uartclk", "apb_pclk";
242 uart2: uart@101f3000 {
243 compatible = "arm,pl011", "arm,primecell";
244 reg = <0x101f3000 0x1000>;
246 clocks = <&xtal24mhz>, <&pclk>;
247 clock-names = "uartclk", "apb_pclk";
251 compatible = "arm,primecell";
252 reg = <0x10100000 0x1000>;
254 clock-names = "apb_pclk";
258 compatible = "arm,primecell";
259 reg = <0x10110000 0x1000>;
261 clock-names = "apb_pclk";
265 compatible = "arm,pl110", "arm,primecell";
266 reg = <0x10120000 0x1000>;
268 clocks = <&osc1>, <&pclk>;
269 clock-names = "clcdclk", "apb_pclk";
270 /* 800x600 16bpp @ 36MHz works fine */
271 max-memory-bandwidth = <54000000>;
274 * This port is routed through a PLD (Programmable
275 * Logic Device) that routes the output from the CLCD
276 * (after transformations) to the VGA DAC and also an
277 * external panel connector. The PLD is essential for
278 * supporting RGB565/BGR565.
280 * The signals from the port thus reaches two endpoints.
281 * The PLD is managed through a few special bits in the
284 * This arrangement can be clearly seen in
285 * ARM DUI 0225D, page 3-41, figure 3-19.
288 #address-cells = <1>;
291 clcd_pads_panel: endpoint@0 {
293 remote-endpoint = <&panel_in>;
294 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
296 clcd_pads_vga_dac: endpoint@1 {
298 remote-endpoint = <&vga_bridge_in>;
299 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
305 compatible = "arm,primecell";
306 reg = <0x101e0000 0x1000>;
308 clock-names = "apb_pclk";
312 compatible = "arm,primecell";
313 reg = <0x101e1000 0x1000>;
316 clock-names = "apb_pclk";
320 compatible = "arm,sp804", "arm,primecell";
321 reg = <0x101e2000 0x1000>;
323 clocks = <&timclk>, <&timclk>, <&pclk>;
324 clock-names = "timer0", "timer1", "apb_pclk";
328 compatible = "arm,sp804", "arm,primecell";
329 reg = <0x101e3000 0x1000>;
331 clocks = <&timclk>, <&timclk>, <&pclk>;
332 clock-names = "timer0", "timer1", "apb_pclk";
335 gpio0: gpio@101e4000 {
336 compatible = "arm,pl061", "arm,primecell";
337 reg = <0x101e4000 0x1000>;
341 interrupt-controller;
342 #interrupt-cells = <2>;
344 clock-names = "apb_pclk";
347 gpio1: gpio@101e5000 {
348 compatible = "arm,pl061", "arm,primecell";
349 reg = <0x101e5000 0x1000>;
353 interrupt-controller;
354 #interrupt-cells = <2>;
356 clock-names = "apb_pclk";
360 compatible = "arm,pl030", "arm,primecell";
361 reg = <0x101e8000 0x1000>;
364 clock-names = "apb_pclk";
368 compatible = "arm,primecell";
369 reg = <0x101f0000 0x1000>;
372 clock-names = "apb_pclk";
376 compatible = "arm,pl022", "arm,primecell";
377 reg = <0x101f4000 0x1000>;
379 clocks = <&xtal24mhz>, <&pclk>;
380 clock-names = "SSPCLK", "apb_pclk";
384 compatible = "arm,versatile-fpga", "simple-bus";
385 #address-cells = <1>;
387 ranges = <0 0x10000000 0x10000>;
390 compatible = "arm,versatile-sysreg", "syscon", "simple-mfd";
391 reg = <0x00000 0x1000>;
394 compatible = "arm,versatile-tft-panel";
398 remote-endpoint = <&clcd_pads_panel>;
405 compatible = "arm,primecell";
406 reg = <0x4000 0x1000>;
409 clock-names = "apb_pclk";
412 compatible = "arm,pl180", "arm,primecell";
413 reg = <0x5000 0x1000>;
414 interrupts-extended = <&vic 22 &sic 1>;
415 clocks = <&xtal24mhz>, <&pclk>;
416 clock-names = "mclk", "apb_pclk";
419 compatible = "arm,pl050", "arm,primecell";
420 reg = <0x6000 0x1000>;
421 interrupt-parent = <&sic>;
423 clocks = <&xtal24mhz>, <&pclk>;
424 clock-names = "KMIREFCLK", "apb_pclk";
427 compatible = "arm,pl050", "arm,primecell";
428 reg = <0x7000 0x1000>;
429 interrupt-parent = <&sic>;
431 clocks = <&xtal24mhz>, <&pclk>;
432 clock-names = "KMIREFCLK", "apb_pclk";