1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier sLD8 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "socionext,uniphier-sld8";
22 compatible = "arm,cortex-a9";
24 enable-method = "psci";
25 next-level-cache = <&l2>;
30 compatible = "arm,psci-0.2";
36 compatible = "fixed-clock";
38 clock-frequency = <25000000>;
41 arm_timer_clk: arm-timer {
43 compatible = "fixed-clock";
44 clock-frequency = <50000000>;
49 compatible = "simple-bus";
53 interrupt-parent = <&intc>;
55 l2: cache-controller@500c0000 {
56 compatible = "socionext,uniphier-system-cache";
57 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
59 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
62 cache-size = <(256 * 1024)>;
64 cache-line-size = <128>;
69 compatible = "socionext,uniphier-scssi";
71 reg = <0x54006000 0x100>;
74 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_spi0>;
77 clocks = <&peri_clk 11>;
78 resets = <&peri_rst 11>;
81 serial0: serial@54006800 {
82 compatible = "socionext,uniphier-uart";
84 reg = <0x54006800 0x40>;
85 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_uart0>;
88 clocks = <&peri_clk 0>;
89 resets = <&peri_rst 0>;
92 serial1: serial@54006900 {
93 compatible = "socionext,uniphier-uart";
95 reg = <0x54006900 0x40>;
96 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_uart1>;
99 clocks = <&peri_clk 1>;
100 resets = <&peri_rst 1>;
103 serial2: serial@54006a00 {
104 compatible = "socionext,uniphier-uart";
106 reg = <0x54006a00 0x40>;
107 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_uart2>;
110 clocks = <&peri_clk 2>;
111 resets = <&peri_rst 2>;
114 serial3: serial@54006b00 {
115 compatible = "socionext,uniphier-uart";
117 reg = <0x54006b00 0x40>;
118 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_uart3>;
121 clocks = <&peri_clk 3>;
122 resets = <&peri_rst 3>;
125 gpio: gpio@55000000 {
126 compatible = "socionext,uniphier-gpio";
127 reg = <0x55000000 0x200>;
128 interrupt-parent = <&aidet>;
129 interrupt-controller;
130 #interrupt-cells = <2>;
133 gpio-ranges = <&pinctrl 0 0 0>,
136 gpio-ranges-group-names = "gpio_range0",
140 socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
144 compatible = "socionext,uniphier-i2c";
146 reg = <0x58400000 0x40>;
147 #address-cells = <1>;
149 interrupts = <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>;
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_i2c0>;
152 clocks = <&peri_clk 4>;
153 resets = <&peri_rst 4>;
154 clock-frequency = <100000>;
158 compatible = "socionext,uniphier-i2c";
160 reg = <0x58480000 0x40>;
161 #address-cells = <1>;
163 interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_i2c1>;
166 clocks = <&peri_clk 5>;
167 resets = <&peri_rst 5>;
168 clock-frequency = <100000>;
171 /* chip-internal connection for DMD */
173 compatible = "socionext,uniphier-i2c";
174 reg = <0x58500000 0x40>;
175 #address-cells = <1>;
177 interrupts = <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_i2c2>;
180 clocks = <&peri_clk 6>;
181 resets = <&peri_rst 6>;
182 clock-frequency = <400000>;
186 compatible = "socionext,uniphier-i2c";
188 reg = <0x58580000 0x40>;
189 #address-cells = <1>;
191 interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>;
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_i2c3>;
194 clocks = <&peri_clk 7>;
195 resets = <&peri_rst 7>;
196 clock-frequency = <100000>;
199 system_bus: system-bus@58c00000 {
200 compatible = "socionext,uniphier-system-bus";
202 reg = <0x58c00000 0x400>;
203 #address-cells = <2>;
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_system_bus>;
210 compatible = "socionext,uniphier-smpctrl";
211 reg = <0x59801000 0x400>;
215 compatible = "socionext,uniphier-sld8-mioctrl",
216 "simple-mfd", "syscon";
217 reg = <0x59810000 0x800>;
220 compatible = "socionext,uniphier-sld8-mio-clock";
225 compatible = "socionext,uniphier-sld8-mio-reset";
231 compatible = "socionext,uniphier-sld8-perictrl",
232 "simple-mfd", "syscon";
233 reg = <0x59820000 0x200>;
236 compatible = "socionext,uniphier-sld8-peri-clock";
241 compatible = "socionext,uniphier-sld8-peri-reset";
246 dmac: dma-controller@5a000000 {
247 compatible = "socionext,uniphier-mio-dmac";
248 reg = <0x5a000000 0x1000>;
249 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&mio_clk 7>;
257 resets = <&mio_rst 7>;
262 compatible = "socionext,uniphier-sd-v2.91";
264 reg = <0x5a400000 0x200>;
265 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
266 pinctrl-names = "default", "uhs";
267 pinctrl-0 = <&pinctrl_sd>;
268 pinctrl-1 = <&pinctrl_sd_uhs>;
269 clocks = <&mio_clk 0>;
270 reset-names = "host", "bridge";
271 resets = <&mio_rst 0>, <&mio_rst 3>;
282 compatible = "socionext,uniphier-sd-v2.91";
284 reg = <0x5a500000 0x200>;
285 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
286 pinctrl-names = "default";
287 pinctrl-0 = <&pinctrl_emmc>;
288 clocks = <&mio_clk 1>;
289 reset-names = "host", "bridge", "hw";
290 resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
300 compatible = "socionext,uniphier-ehci", "generic-ehci";
302 reg = <0x5a800100 0x100>;
303 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
304 pinctrl-names = "default";
305 pinctrl-0 = <&pinctrl_usb0>;
306 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
308 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
310 has-transaction-translator;
314 compatible = "socionext,uniphier-ehci", "generic-ehci";
316 reg = <0x5a810100 0x100>;
317 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
318 pinctrl-names = "default";
319 pinctrl-0 = <&pinctrl_usb1>;
320 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
322 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
324 has-transaction-translator;
328 compatible = "socionext,uniphier-ehci", "generic-ehci";
330 reg = <0x5a820100 0x100>;
331 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
332 pinctrl-names = "default";
333 pinctrl-0 = <&pinctrl_usb2>;
334 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
336 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
338 has-transaction-translator;
342 compatible = "socionext,uniphier-sld8-soc-glue",
343 "simple-mfd", "syscon";
344 reg = <0x5f800000 0x2000>;
347 compatible = "socionext,uniphier-sld8-pinctrl";
352 compatible = "socionext,uniphier-sld8-soc-glue-debug",
354 #address-cells = <1>;
356 ranges = <0 0x5f900000 0x2000>;
359 compatible = "socionext,uniphier-efuse";
364 compatible = "socionext,uniphier-efuse";
370 compatible = "arm,cortex-a9-global-timer";
371 reg = <0x60000200 0x20>;
372 interrupts = <GIC_PPI 11
373 (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
374 clocks = <&arm_timer_clk>;
378 compatible = "arm,cortex-a9-twd-timer";
379 reg = <0x60000600 0x20>;
380 interrupts = <GIC_PPI 13
381 (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
382 clocks = <&arm_timer_clk>;
385 intc: interrupt-controller@60001000 {
386 compatible = "arm,cortex-a9-gic";
387 reg = <0x60001000 0x1000>,
389 #interrupt-cells = <3>;
390 interrupt-controller;
393 aidet: interrupt-controller@61830000 {
394 compatible = "socionext,uniphier-sld8-aidet";
395 reg = <0x61830000 0x200>;
396 interrupt-controller;
397 #interrupt-cells = <2>;
401 compatible = "socionext,uniphier-sld8-sysctrl",
402 "simple-mfd", "syscon";
403 reg = <0x61840000 0x10000>;
406 compatible = "socionext,uniphier-sld8-clock";
411 compatible = "socionext,uniphier-sld8-reset";
416 nand: nand-controller@68000000 {
417 compatible = "socionext,uniphier-denali-nand-v5a";
419 reg-names = "nand_data", "denali_reg";
420 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
421 #address-cells = <1>;
423 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
424 pinctrl-names = "default";
425 pinctrl-0 = <&pinctrl_nand>;
426 clock-names = "nand", "nand_x", "ecc";
427 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
428 reset-names = "nand", "reg";
429 resets = <&sys_rst 2>, <&sys_rst 2>;
434 #include "uniphier-pinctrl.dtsi"