arch/arm/boot/dts/uniphier-sld8.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Device Tree Source for UniPhier sLD8 SoC
   4 //
   5 // Copyright (C) 2015-2016 Socionext Inc.
   6 //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   7
   8 #include <dt-bindings/gpio/uniphier-gpio.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10
  11 / {
  12         compatible = "socionext,uniphier-sld8";
  13         #address-cells = <1>;
  14         #size-cells = <1>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu@0 {
  21                         device_type = "cpu";
  22                         compatible = "arm,cortex-a9";
  23                         reg = <0>;
  24                         enable-method = "psci";
  25                         next-level-cache = <&l2>;
  26                 };
  27         };
  28
  29         psci {
  30                 compatible = "arm,psci-0.2";
  31                 method = "smc";
  32         };
  33
  34         clocks {
  35                 refclk: ref {
  36                         compatible = "fixed-clock";
  37                         #clock-cells = <0>;
  38                         clock-frequency = <25000000>;
  39                 };
  40
  41                 arm_timer_clk: arm-timer {
  42                         #clock-cells = <0>;
  43                         compatible = "fixed-clock";
  44                         clock-frequency = <50000000>;
  45                 };
  46         };
  47
  48         soc {
  49                 compatible = "simple-bus";
  50                 #address-cells = <1>;
  51                 #size-cells = <1>;
  52                 ranges;
  53                 interrupt-parent = <&intc>;
  54
  55                 l2: cache-controller@500c0000 {
  56                         compatible = "socionext,uniphier-system-cache";
  57                         reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
  58                               <0x506c0000 0x400>;
  59                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
  60                                      <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
  61                         cache-unified;
  62                         cache-size = <(256 * 1024)>;
  63                         cache-sets = <256>;
  64                         cache-line-size = <128>;
  65                         cache-level = <2>;
  66                 };
  67
  68                 spi: spi@54006000 {
  69                         compatible = "socionext,uniphier-scssi";
  70                         status = "disabled";
  71                         reg = <0x54006000 0x100>;
  72                         #address-cells = <1>;
  73                         #size-cells = <0>;
  74                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
  75                         pinctrl-names = "default";
  76                         pinctrl-0 = <&pinctrl_spi0>;
  77                         clocks = <&peri_clk 11>;
  78                         resets = <&peri_rst 11>;
  79                 };
  80
  81                 serial0: serial@54006800 {
  82                         compatible = "socionext,uniphier-uart";
  83                         status = "disabled";
  84                         reg = <0x54006800 0x40>;
  85                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
  86                         pinctrl-names = "default";
  87                         pinctrl-0 = <&pinctrl_uart0>;
  88                         clocks = <&peri_clk 0>;
  89                         resets = <&peri_rst 0>;
  90                 };
  91
  92                 serial1: serial@54006900 {
  93                         compatible = "socionext,uniphier-uart";
  94                         status = "disabled";
  95                         reg = <0x54006900 0x40>;
  96                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  97                         pinctrl-names = "default";
  98                         pinctrl-0 = <&pinctrl_uart1>;
  99                         clocks = <&peri_clk 1>;
 100                         resets = <&peri_rst 1>;
 101                 };
 102
 103                 serial2: serial@54006a00 {
 104                         compatible = "socionext,uniphier-uart";
 105                         status = "disabled";
 106                         reg = <0x54006a00 0x40>;
 107                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 108                         pinctrl-names = "default";
 109                         pinctrl-0 = <&pinctrl_uart2>;
 110                         clocks = <&peri_clk 2>;
 111                         resets = <&peri_rst 2>;
 112                 };
 113
 114                 serial3: serial@54006b00 {
 115                         compatible = "socionext,uniphier-uart";
 116                         status = "disabled";
 117                         reg = <0x54006b00 0x40>;
 118                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 119                         pinctrl-names = "default";
 120                         pinctrl-0 = <&pinctrl_uart3>;
 121                         clocks = <&peri_clk 3>;
 122                         resets = <&peri_rst 3>;
 123                 };
 124
 125                 gpio: gpio@55000000 {
 126                         compatible = "socionext,uniphier-gpio";
 127                         reg = <0x55000000 0x200>;
 128                         interrupt-parent = <&aidet>;
 129                         interrupt-controller;
 130                         #interrupt-cells = <2>;
 131                         gpio-controller;
 132                         #gpio-cells = <2>;
 133                         gpio-ranges = <&pinctrl 0 0 0>,
 134                                       <&pinctrl 104 0 0>,
 135                                       <&pinctrl 112 0 0>;
 136                         gpio-ranges-group-names = "gpio_range0",
 137                                                   "gpio_range1",
 138                                                   "gpio_range2";
 139                         ngpios = <136>;
 140                         socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
 141                 };
 142
 143                 i2c0: i2c@58400000 {
 144                         compatible = "socionext,uniphier-i2c";
 145                         status = "disabled";
 146                         reg = <0x58400000 0x40>;
 147                         #address-cells = <1>;
 148                         #size-cells = <0>;
 149                         interrupts = <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>;
 150                         pinctrl-names = "default";
 151                         pinctrl-0 = <&pinctrl_i2c0>;
 152                         clocks = <&peri_clk 4>;
 153                         resets = <&peri_rst 4>;
 154                         clock-frequency = <100000>;
 155                 };
 156
 157                 i2c1: i2c@58480000 {
 158                         compatible = "socionext,uniphier-i2c";
 159                         status = "disabled";
 160                         reg = <0x58480000 0x40>;
 161                         #address-cells = <1>;
 162                         #size-cells = <0>;
 163                         interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>;
 164                         pinctrl-names = "default";
 165                         pinctrl-0 = <&pinctrl_i2c1>;
 166                         clocks = <&peri_clk 5>;
 167                         resets = <&peri_rst 5>;
 168                         clock-frequency = <100000>;
 169                 };
 170
 171                 /* chip-internal connection for DMD */
 172                 i2c2: i2c@58500000 {
 173                         compatible = "socionext,uniphier-i2c";
 174                         reg = <0x58500000 0x40>;
 175                         #address-cells = <1>;
 176                         #size-cells = <0>;
 177                         interrupts = <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>;
 178                         pinctrl-names = "default";
 179                         pinctrl-0 = <&pinctrl_i2c2>;
 180                         clocks = <&peri_clk 6>;
 181                         resets = <&peri_rst 6>;
 182                         clock-frequency = <400000>;
 183                 };
 184
 185                 i2c3: i2c@58580000 {
 186                         compatible = "socionext,uniphier-i2c";
 187                         status = "disabled";
 188                         reg = <0x58580000 0x40>;
 189                         #address-cells = <1>;
 190                         #size-cells = <0>;
 191                         interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>;
 192                         pinctrl-names = "default";
 193                         pinctrl-0 = <&pinctrl_i2c3>;
 194                         clocks = <&peri_clk 7>;
 195                         resets = <&peri_rst 7>;
 196                         clock-frequency = <100000>;
 197                 };
 198
 199                 system_bus: system-bus@58c00000 {
 200                         compatible = "socionext,uniphier-system-bus";
 201                         status = "disabled";
 202                         reg = <0x58c00000 0x400>;
 203                         #address-cells = <2>;
 204                         #size-cells = <1>;
 205                         pinctrl-names = "default";
 206                         pinctrl-0 = <&pinctrl_system_bus>;
 207                 };
 208
 209                 smpctrl@59801000 {
 210                         compatible = "socionext,uniphier-smpctrl";
 211                         reg = <0x59801000 0x400>;
 212                 };
 213
 214                 mioctrl@59810000 {
 215                         compatible = "socionext,uniphier-sld8-mioctrl",
 216                                      "simple-mfd", "syscon";
 217                         reg = <0x59810000 0x800>;
 218
 219                         mio_clk: clock {
 220                                 compatible = "socionext,uniphier-sld8-mio-clock";
 221                                 #clock-cells = <1>;
 222                         };
 223
 224                         mio_rst: reset {
 225                                 compatible = "socionext,uniphier-sld8-mio-reset";
 226                                 #reset-cells = <1>;
 227                         };
 228                 };
 229
 230                 perictrl@59820000 {
 231                         compatible = "socionext,uniphier-sld8-perictrl",
 232                                      "simple-mfd", "syscon";
 233                         reg = <0x59820000 0x200>;
 234
 235                         peri_clk: clock {
 236                                 compatible = "socionext,uniphier-sld8-peri-clock";
 237                                 #clock-cells = <1>;
 238                         };
 239
 240                         peri_rst: reset {
 241                                 compatible = "socionext,uniphier-sld8-peri-reset";
 242                                 #reset-cells = <1>;
 243                         };
 244                 };
 245
 246                 dmac: dma-controller@5a000000 {
 247                         compatible = "socionext,uniphier-mio-dmac";
 248                         reg = <0x5a000000 0x1000>;
 249                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 250                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 251                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 252                                      <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 253                                      <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
 254                                      <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 255                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 256                         clocks = <&mio_clk 7>;
 257                         resets = <&mio_rst 7>;
 258                         #dma-cells = <1>;
 259                 };
 260
 261                 sd: mmc@5a400000 {
 262                         compatible = "socionext,uniphier-sd-v2.91";
 263                         status = "disabled";
 264                         reg = <0x5a400000 0x200>;
 265                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 266                         pinctrl-names = "default", "uhs";
 267                         pinctrl-0 = <&pinctrl_sd>;
 268                         pinctrl-1 = <&pinctrl_sd_uhs>;
 269                         clocks = <&mio_clk 0>;
 270                         reset-names = "host", "bridge";
 271                         resets = <&mio_rst 0>, <&mio_rst 3>;
 272                         dma-names = "rx-tx";
 273                         dmas = <&dmac 4>;
 274                         bus-width = <4>;
 275                         cap-sd-highspeed;
 276                         sd-uhs-sdr12;
 277                         sd-uhs-sdr25;
 278                         sd-uhs-sdr50;
 279                 };
 280
 281                 emmc: mmc@5a500000 {
 282                         compatible = "socionext,uniphier-sd-v2.91";
 283                         status = "disabled";
 284                         reg = <0x5a500000 0x200>;
 285                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 286                         pinctrl-names = "default";
 287                         pinctrl-0 = <&pinctrl_emmc>;
 288                         clocks = <&mio_clk 1>;
 289                         reset-names = "host", "bridge", "hw";
 290                         resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
 291                         dma-names = "rx-tx";
 292                         dmas = <&dmac 6>;
 293                         bus-width = <8>;
 294                         cap-mmc-highspeed;
 295                         cap-mmc-hw-reset;
 296                         non-removable;
 297                 };
 298
 299                 usb0: usb@5a800100 {
 300                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 301                         status = "disabled";
 302                         reg = <0x5a800100 0x100>;
 303                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 304                         pinctrl-names = "default";
 305                         pinctrl-0 = <&pinctrl_usb0>;
 306                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
 307                                  <&mio_clk 12>;
 308                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 309                                  <&mio_rst 12>;
 310                         has-transaction-translator;
 311                 };
 312
 313                 usb1: usb@5a810100 {
 314                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 315                         status = "disabled";
 316                         reg = <0x5a810100 0x100>;
 317                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 318                         pinctrl-names = "default";
 319                         pinctrl-0 = <&pinctrl_usb1>;
 320                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
 321                                  <&mio_clk 13>;
 322                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 323                                  <&mio_rst 13>;
 324                         has-transaction-translator;
 325                 };
 326
 327                 usb2: usb@5a820100 {
 328                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 329                         status = "disabled";
 330                         reg = <0x5a820100 0x100>;
 331                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 332                         pinctrl-names = "default";
 333                         pinctrl-0 = <&pinctrl_usb2>;
 334                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
 335                                  <&mio_clk 14>;
 336                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
 337                                  <&mio_rst 14>;
 338                         has-transaction-translator;
 339                 };
 340
 341                 soc-glue@5f800000 {
 342                         compatible = "socionext,uniphier-sld8-soc-glue",
 343                                      "simple-mfd", "syscon";
 344                         reg = <0x5f800000 0x2000>;
 345
 346                         pinctrl: pinctrl {
 347                                 compatible = "socionext,uniphier-sld8-pinctrl";
 348                         };
 349                 };
 350
 351                 soc-glue@5f900000 {
 352                         compatible = "socionext,uniphier-sld8-soc-glue-debug",
 353                                      "simple-mfd";
 354                         #address-cells = <1>;
 355                         #size-cells = <1>;
 356                         ranges = <0 0x5f900000 0x2000>;
 357
 358                         efuse@100 {
 359                                 compatible = "socionext,uniphier-efuse";
 360                                 reg = <0x100 0x28>;
 361                         };
 362
 363                         efuse@200 {
 364                                 compatible = "socionext,uniphier-efuse";
 365                                 reg = <0x200 0x14>;
 366                         };
 367                 };
 368
 369                 timer@60000200 {
 370                         compatible = "arm,cortex-a9-global-timer";
 371                         reg = <0x60000200 0x20>;
 372                         interrupts = <GIC_PPI 11
 373                                 (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
 374                         clocks = <&arm_timer_clk>;
 375                 };
 376
 377                 timer@60000600 {
 378                         compatible = "arm,cortex-a9-twd-timer";
 379                         reg = <0x60000600 0x20>;
 380                         interrupts = <GIC_PPI 13
 381                                 (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
 382                         clocks = <&arm_timer_clk>;
 383                 };
 384
 385                 intc: interrupt-controller@60001000 {
 386                         compatible = "arm,cortex-a9-gic";
 387                         reg = <0x60001000 0x1000>,
 388                               <0x60000100 0x100>;
 389                         #interrupt-cells = <3>;
 390                         interrupt-controller;
 391                 };
 392
 393                 aidet: interrupt-controller@61830000 {
 394                         compatible = "socionext,uniphier-sld8-aidet";
 395                         reg = <0x61830000 0x200>;
 396                         interrupt-controller;
 397                         #interrupt-cells = <2>;
 398                 };
 399
 400                 sysctrl@61840000 {
 401                         compatible = "socionext,uniphier-sld8-sysctrl",
 402                                      "simple-mfd", "syscon";
 403                         reg = <0x61840000 0x10000>;
 404
 405                         sys_clk: clock {
 406                                 compatible = "socionext,uniphier-sld8-clock";
 407                                 #clock-cells = <1>;
 408                         };
 409
 410                         sys_rst: reset {
 411                                 compatible = "socionext,uniphier-sld8-reset";
 412                                 #reset-cells = <1>;
 413                         };
 414                 };
 415
 416                 nand: nand-controller@68000000 {
 417                         compatible = "socionext,uniphier-denali-nand-v5a";
 418                         status = "disabled";
 419                         reg-names = "nand_data", "denali_reg";
 420                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 421                         #address-cells = <1>;
 422                         #size-cells = <0>;
 423                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 424                         pinctrl-names = "default";
 425                         pinctrl-0 = <&pinctrl_nand>;
 426                         clock-names = "nand", "nand_x", "ecc";
 427                         clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
 428                         reset-names = "nand", "reg";
 429                         resets = <&sys_rst 2>, <&sys_rst 2>;
 430                 };
 431         };
 432 };
 433
 434 #include "uniphier-pinctrl.dtsi"