2 * Device Tree Source for UniPhier sLD3 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
46 /include/ "skeleton.dtsi"
49 compatible = "socionext,uniphier-sld3";
57 compatible = "arm,cortex-a9";
59 enable-method = "psci";
60 next-level-cache = <&l2>;
65 compatible = "arm,cortex-a9";
67 enable-method = "psci";
68 next-level-cache = <&l2>;
73 compatible = "arm,psci-0.2";
80 compatible = "fixed-clock";
81 clock-frequency = <24576000>;
84 arm_timer_clk: arm_timer_clk {
86 compatible = "fixed-clock";
87 clock-frequency = <50000000>;
92 compatible = "simple-bus";
96 interrupt-parent = <&intc>;
99 compatible = "arm,cortex-a9-global-timer";
100 reg = <0x20000200 0x20>;
101 interrupts = <1 11 0x304>;
102 clocks = <&arm_timer_clk>;
106 compatible = "arm,cortex-a9-twd-timer";
107 reg = <0x20000600 0x20>;
108 interrupts = <1 13 0x304>;
109 clocks = <&arm_timer_clk>;
112 intc: interrupt-controller@20001000 {
113 compatible = "arm,cortex-a9-gic";
114 #interrupt-cells = <3>;
115 interrupt-controller;
116 reg = <0x20001000 0x1000>,
120 l2: l2-cache@500c0000 {
121 compatible = "socionext,uniphier-system-cache";
122 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
124 interrupts = <0 174 4>, <0 175 4>;
126 cache-size = <(512 * 1024)>;
128 cache-line-size = <128>;
132 serial0: serial@54006800 {
133 compatible = "socionext,uniphier-uart";
135 reg = <0x54006800 0x40>;
136 interrupts = <0 33 4>;
137 clocks = <&sys_clk 0>;
141 serial1: serial@54006900 {
142 compatible = "socionext,uniphier-uart";
144 reg = <0x54006900 0x40>;
145 interrupts = <0 35 4>;
146 clocks = <&sys_clk 0>;
150 serial2: serial@54006a00 {
151 compatible = "socionext,uniphier-uart";
153 reg = <0x54006a00 0x40>;
154 interrupts = <0 37 4>;
155 clocks = <&sys_clk 0>;
160 compatible = "socionext,uniphier-i2c";
162 reg = <0x58400000 0x40>;
163 #address-cells = <1>;
165 interrupts = <0 41 1>;
166 clocks = <&sys_clk 1>;
167 clock-frequency = <100000>;
171 compatible = "socionext,uniphier-i2c";
173 reg = <0x58480000 0x40>;
174 #address-cells = <1>;
176 interrupts = <0 42 1>;
177 clocks = <&sys_clk 1>;
178 clock-frequency = <100000>;
182 compatible = "socionext,uniphier-i2c";
184 reg = <0x58500000 0x40>;
185 #address-cells = <1>;
187 interrupts = <0 43 1>;
188 clocks = <&sys_clk 1>;
189 clock-frequency = <100000>;
193 compatible = "socionext,uniphier-i2c";
195 reg = <0x58580000 0x40>;
196 #address-cells = <1>;
198 interrupts = <0 44 1>;
199 clocks = <&sys_clk 1>;
200 clock-frequency = <100000>;
203 /* chip-internal connection for DMD */
205 compatible = "socionext,uniphier-i2c";
206 reg = <0x58600000 0x40>;
207 #address-cells = <1>;
209 interrupts = <0 45 1>;
210 clocks = <&sys_clk 1>;
211 clock-frequency = <400000>;
214 system_bus: system-bus@58c00000 {
215 compatible = "socionext,uniphier-system-bus";
217 reg = <0x58c00000 0x400>;
218 #address-cells = <2>;
223 compatible = "socionext,uniphier-smpctrl";
224 reg = <0x59801000 0x400>;
228 compatible = "socionext,uniphier-mioctrl",
229 "simple-mfd", "syscon";
230 reg = <0x59810000 0x800>;
233 compatible = "socionext,uniphier-sld3-mio-clock";
238 compatible = "socionext,uniphier-sld3-mio-reset";
244 compatible = "socionext,uniphier-ehci", "generic-ehci";
246 reg = <0x5a800100 0x100>;
247 interrupts = <0 80 4>;
251 compatible = "socionext,uniphier-ehci", "generic-ehci";
253 reg = <0x5a810100 0x100>;
254 interrupts = <0 81 4>;
258 compatible = "socionext,uniphier-ehci", "generic-ehci";
260 reg = <0x5a820100 0x100>;
261 interrupts = <0 82 4>;
265 compatible = "socionext,uniphier-ehci", "generic-ehci";
267 reg = <0x5a830100 0x100>;
268 interrupts = <0 83 4>;
272 compatible = "socionext,uniphier-sysctrl",
273 "simple-mfd", "syscon";
274 reg = <0xf1840000 0x4000>;
277 compatible = "socionext,uniphier-sld3-clock";
282 compatible = "socionext,uniphier-sld3-reset";