1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier PXs2 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/thermal/thermal.h>
12 compatible = "socionext,uniphier-pxs2";
22 compatible = "arm,cortex-a9";
24 clocks = <&sys_clk 32>;
25 enable-method = "psci";
26 next-level-cache = <&l2>;
27 operating-points-v2 = <&cpu_opp>;
33 compatible = "arm,cortex-a9";
35 clocks = <&sys_clk 32>;
36 enable-method = "psci";
37 next-level-cache = <&l2>;
38 operating-points-v2 = <&cpu_opp>;
44 compatible = "arm,cortex-a9";
46 clocks = <&sys_clk 32>;
47 enable-method = "psci";
48 next-level-cache = <&l2>;
49 operating-points-v2 = <&cpu_opp>;
55 compatible = "arm,cortex-a9";
57 clocks = <&sys_clk 32>;
58 enable-method = "psci";
59 next-level-cache = <&l2>;
60 operating-points-v2 = <&cpu_opp>;
66 compatible = "operating-points-v2";
70 opp-hz = /bits/ 64 <100000000>;
71 clock-latency-ns = <300>;
74 opp-hz = /bits/ 64 <150000000>;
75 clock-latency-ns = <300>;
78 opp-hz = /bits/ 64 <200000000>;
79 clock-latency-ns = <300>;
82 opp-hz = /bits/ 64 <300000000>;
83 clock-latency-ns = <300>;
86 opp-hz = /bits/ 64 <400000000>;
87 clock-latency-ns = <300>;
90 opp-hz = /bits/ 64 <600000000>;
91 clock-latency-ns = <300>;
94 opp-hz = /bits/ 64 <800000000>;
95 clock-latency-ns = <300>;
98 opp-hz = /bits/ 64 <1200000000>;
99 clock-latency-ns = <300>;
104 compatible = "arm,psci-0.2";
110 compatible = "fixed-clock";
112 clock-frequency = <25000000>;
115 arm_timer_clk: arm-timer {
117 compatible = "fixed-clock";
118 clock-frequency = <50000000>;
124 polling-delay-passive = <250>; /* 250ms */
125 polling-delay = <1000>; /* 1000ms */
126 thermal-sensors = <&pvtctl>;
130 temperature = <95000>; /* 95C */
134 cpu_alert: cpu-alert {
135 temperature = <85000>; /* 85C */
144 cooling-device = <&cpu0
145 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
152 compatible = "simple-bus";
153 #address-cells = <1>;
156 interrupt-parent = <&intc>;
158 l2: l2-cache@500c0000 {
159 compatible = "socionext,uniphier-system-cache";
160 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
162 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
164 cache-size = <(1280 * 1024)>;
166 cache-line-size = <128>;
170 serial0: serial@54006800 {
171 compatible = "socionext,uniphier-uart";
173 reg = <0x54006800 0x40>;
174 interrupts = <0 33 4>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_uart0>;
177 clocks = <&peri_clk 0>;
178 resets = <&peri_rst 0>;
181 serial1: serial@54006900 {
182 compatible = "socionext,uniphier-uart";
184 reg = <0x54006900 0x40>;
185 interrupts = <0 35 4>;
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_uart1>;
188 clocks = <&peri_clk 1>;
189 resets = <&peri_rst 1>;
192 serial2: serial@54006a00 {
193 compatible = "socionext,uniphier-uart";
195 reg = <0x54006a00 0x40>;
196 interrupts = <0 37 4>;
197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_uart2>;
199 clocks = <&peri_clk 2>;
200 resets = <&peri_rst 2>;
203 serial3: serial@54006b00 {
204 compatible = "socionext,uniphier-uart";
206 reg = <0x54006b00 0x40>;
207 interrupts = <0 177 4>;
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_uart3>;
210 clocks = <&peri_clk 3>;
211 resets = <&peri_rst 3>;
214 gpio: gpio@55000000 {
215 compatible = "socionext,uniphier-gpio";
216 reg = <0x55000000 0x200>;
217 interrupt-parent = <&aidet>;
218 interrupt-controller;
219 #interrupt-cells = <2>;
222 gpio-ranges = <&pinctrl 0 0 0>,
224 gpio-ranges-group-names = "gpio_range0",
227 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
232 compatible = "socionext,uniphier-pxs2-aio";
233 reg = <0x56000000 0x80000>;
234 interrupts = <0 144 4>;
235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_ain1>,
244 clocks = <&sys_clk 40>;
246 resets = <&sys_rst 40>;
247 #sound-dai-cells = <1>;
248 socionext,syscon = <&soc_glue>;
265 spdif_port0: port@3 {
266 spdif_hiecout1: endpoint {
270 spdif_port1: port@4 {
271 spdif_iecout1: endpoint {
275 comp_spdif_port0: port@5 {
276 comp_spdif_hiecout1: endpoint {
280 comp_spdif_port1: port@6 {
281 comp_spdif_iecout1: endpoint {
287 compatible = "socionext,uniphier-fi2c";
289 reg = <0x58780000 0x80>;
290 #address-cells = <1>;
292 interrupts = <0 41 4>;
293 pinctrl-names = "default";
294 pinctrl-0 = <&pinctrl_i2c0>;
295 clocks = <&peri_clk 4>;
296 resets = <&peri_rst 4>;
297 clock-frequency = <100000>;
301 compatible = "socionext,uniphier-fi2c";
303 reg = <0x58781000 0x80>;
304 #address-cells = <1>;
306 interrupts = <0 42 4>;
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_i2c1>;
309 clocks = <&peri_clk 5>;
310 resets = <&peri_rst 5>;
311 clock-frequency = <100000>;
315 compatible = "socionext,uniphier-fi2c";
317 reg = <0x58782000 0x80>;
318 #address-cells = <1>;
320 interrupts = <0 43 4>;
321 pinctrl-names = "default";
322 pinctrl-0 = <&pinctrl_i2c2>;
323 clocks = <&peri_clk 6>;
324 resets = <&peri_rst 6>;
325 clock-frequency = <100000>;
329 compatible = "socionext,uniphier-fi2c";
331 reg = <0x58783000 0x80>;
332 #address-cells = <1>;
334 interrupts = <0 44 4>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&pinctrl_i2c3>;
337 clocks = <&peri_clk 7>;
338 resets = <&peri_rst 7>;
339 clock-frequency = <100000>;
342 /* chip-internal connection for DMD */
344 compatible = "socionext,uniphier-fi2c";
345 reg = <0x58784000 0x80>;
346 #address-cells = <1>;
348 interrupts = <0 45 4>;
349 clocks = <&peri_clk 8>;
350 resets = <&peri_rst 8>;
351 clock-frequency = <400000>;
354 /* chip-internal connection for STM */
356 compatible = "socionext,uniphier-fi2c";
357 reg = <0x58785000 0x80>;
358 #address-cells = <1>;
360 interrupts = <0 25 4>;
361 clocks = <&peri_clk 9>;
362 resets = <&peri_rst 9>;
363 clock-frequency = <400000>;
366 /* chip-internal connection for HDMI */
368 compatible = "socionext,uniphier-fi2c";
369 reg = <0x58786000 0x80>;
370 #address-cells = <1>;
372 interrupts = <0 26 4>;
373 clocks = <&peri_clk 10>;
374 resets = <&peri_rst 10>;
375 clock-frequency = <400000>;
378 system_bus: system-bus@58c00000 {
379 compatible = "socionext,uniphier-system-bus";
381 reg = <0x58c00000 0x400>;
382 #address-cells = <2>;
384 pinctrl-names = "default";
385 pinctrl-0 = <&pinctrl_system_bus>;
389 compatible = "socionext,uniphier-smpctrl";
390 reg = <0x59801000 0x400>;
394 compatible = "socionext,uniphier-pxs2-sdctrl",
395 "simple-mfd", "syscon";
396 reg = <0x59810000 0x400>;
399 compatible = "socionext,uniphier-pxs2-sd-clock";
404 compatible = "socionext,uniphier-pxs2-sd-reset";
410 compatible = "socionext,uniphier-pxs2-perictrl",
411 "simple-mfd", "syscon";
412 reg = <0x59820000 0x200>;
415 compatible = "socionext,uniphier-pxs2-peri-clock";
420 compatible = "socionext,uniphier-pxs2-peri-reset";
425 soc_glue: soc-glue@5f800000 {
426 compatible = "socionext,uniphier-pxs2-soc-glue",
427 "simple-mfd", "syscon";
428 reg = <0x5f800000 0x2000>;
431 compatible = "socionext,uniphier-pxs2-pinctrl";
436 compatible = "socionext,uniphier-pxs2-soc-glue-debug",
438 #address-cells = <1>;
440 ranges = <0 0x5f900000 0x2000>;
443 compatible = "socionext,uniphier-efuse";
448 compatible = "socionext,uniphier-efuse";
453 aidet: aidet@5fc20000 {
454 compatible = "socionext,uniphier-pxs2-aidet";
455 reg = <0x5fc20000 0x200>;
456 interrupt-controller;
457 #interrupt-cells = <2>;
461 compatible = "arm,cortex-a9-global-timer";
462 reg = <0x60000200 0x20>;
463 interrupts = <1 11 0xf04>;
464 clocks = <&arm_timer_clk>;
468 compatible = "arm,cortex-a9-twd-timer";
469 reg = <0x60000600 0x20>;
470 interrupts = <1 13 0xf04>;
471 clocks = <&arm_timer_clk>;
474 intc: interrupt-controller@60001000 {
475 compatible = "arm,cortex-a9-gic";
476 reg = <0x60001000 0x1000>,
478 #interrupt-cells = <3>;
479 interrupt-controller;
483 compatible = "socionext,uniphier-pxs2-sysctrl",
484 "simple-mfd", "syscon";
485 reg = <0x61840000 0x10000>;
488 compatible = "socionext,uniphier-pxs2-clock";
493 compatible = "socionext,uniphier-pxs2-reset";
498 compatible = "socionext,uniphier-pxs2-thermal";
499 interrupts = <0 3 4>;
500 #thermal-sensor-cells = <0>;
501 socionext,tmod-calibration = <0x0f86 0x6844>;
505 eth: ethernet@65000000 {
506 compatible = "socionext,uniphier-pxs2-ave4";
508 reg = <0x65000000 0x8500>;
509 interrupts = <0 66 4>;
510 pinctrl-names = "default";
511 pinctrl-0 = <&pinctrl_ether_rgmii>;
512 clock-names = "ether";
513 clocks = <&sys_clk 6>;
514 reset-names = "ether";
515 resets = <&sys_rst 6>;
516 phy-mode = "rgmii-id";
517 local-mac-address = [00 00 00 00 00 00];
518 socionext,syscon-phy-mode = <&soc_glue 0>;
521 #address-cells = <1>;
526 nand: nand@68000000 {
527 compatible = "socionext,uniphier-denali-nand-v5b";
529 reg-names = "nand_data", "denali_reg";
530 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
531 interrupts = <0 65 4>;
532 pinctrl-names = "default";
533 pinctrl-0 = <&pinctrl_nand2cs>;
534 clocks = <&sys_clk 2>;
535 resets = <&sys_rst 2>;
540 #include "uniphier-pinctrl.dtsi"