2 * Device Tree Source for UniPhier PXs2 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
46 /include/ "uniphier-common32.dtsi"
49 compatible = "socionext,uniphier-pxs2";
57 compatible = "arm,cortex-a9";
59 enable-method = "psci";
60 next-level-cache = <&l2>;
65 compatible = "arm,cortex-a9";
67 enable-method = "psci";
68 next-level-cache = <&l2>;
73 compatible = "arm,cortex-a9";
75 enable-method = "psci";
76 next-level-cache = <&l2>;
81 compatible = "arm,cortex-a9";
83 enable-method = "psci";
84 next-level-cache = <&l2>;
89 arm_timer_clk: arm_timer_clk {
91 compatible = "fixed-clock";
92 clock-frequency = <50000000>;
98 l2: l2-cache@500c0000 {
99 compatible = "socionext,uniphier-system-cache";
100 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
101 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
103 cache-size = <(1280 * 1024)>;
105 cache-line-size = <128>;
110 compatible = "socionext,uniphier-fi2c";
112 reg = <0x58780000 0x80>;
113 #address-cells = <1>;
115 interrupts = <0 41 4>;
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_i2c0>;
118 clocks = <&peri_clk 4>;
119 clock-frequency = <100000>;
123 compatible = "socionext,uniphier-fi2c";
125 reg = <0x58781000 0x80>;
126 #address-cells = <1>;
128 interrupts = <0 42 4>;
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_i2c1>;
131 clocks = <&peri_clk 5>;
132 clock-frequency = <100000>;
136 compatible = "socionext,uniphier-fi2c";
138 reg = <0x58782000 0x80>;
139 #address-cells = <1>;
141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_i2c2>;
143 interrupts = <0 43 4>;
144 clocks = <&peri_clk 6>;
145 clock-frequency = <100000>;
149 compatible = "socionext,uniphier-fi2c";
151 reg = <0x58783000 0x80>;
152 #address-cells = <1>;
154 interrupts = <0 44 4>;
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_i2c3>;
157 clocks = <&peri_clk 7>;
158 clock-frequency = <100000>;
161 /* chip-internal connection for DMD */
163 compatible = "socionext,uniphier-fi2c";
164 reg = <0x58784000 0x80>;
165 #address-cells = <1>;
167 interrupts = <0 45 4>;
168 clocks = <&peri_clk 8>;
169 clock-frequency = <400000>;
172 /* chip-internal connection for STM */
174 compatible = "socionext,uniphier-fi2c";
175 reg = <0x58785000 0x80>;
176 #address-cells = <1>;
178 interrupts = <0 25 4>;
179 clocks = <&peri_clk 9>;
180 clock-frequency = <400000>;
183 /* chip-internal connection for HDMI */
185 compatible = "socionext,uniphier-fi2c";
186 reg = <0x58786000 0x80>;
187 #address-cells = <1>;
189 interrupts = <0 26 4>;
190 clocks = <&peri_clk 10>;
191 clock-frequency = <400000>;
196 clock-frequency = <25000000>;
200 compatible = "socionext,uniphier-pxs2-sd-clock";
204 compatible = "socionext,uniphier-pxs2-sd-reset";
208 compatible = "socionext,uniphier-pxs2-peri-clock";
212 compatible = "socionext,uniphier-pxs2-peri-reset";
216 compatible = "socionext,uniphier-pxs2-pinctrl";
220 compatible = "socionext,uniphier-pxs2-clock";
224 compatible = "socionext,uniphier-pxs2-reset";