arch/arm/boot/dts/uniphier-pro5.dtsi

   1 /*
   2  * Device Tree Source for UniPhier Pro5 SoC
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   8  */
   9
  10 / {
  11         compatible = "socionext,uniphier-pro5";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a9";
  22                         reg = <0>;
  23                         clocks = <&sys_clk 32>;
  24                         enable-method = "psci";
  25                         next-level-cache = <&l2>;
  26                         operating-points-v2 = <&cpu_opp>;
  27                 };
  28
  29                 cpu@1 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a9";
  32                         reg = <1>;
  33                         clocks = <&sys_clk 32>;
  34                         enable-method = "psci";
  35                         next-level-cache = <&l2>;
  36                         operating-points-v2 = <&cpu_opp>;
  37                 };
  38         };
  39
  40         cpu_opp: opp_table {
  41                 compatible = "operating-points-v2";
  42                 opp-shared;
  43
  44                 opp-100000000 {
  45                         opp-hz = /bits/ 64 <100000000>;
  46                         clock-latency-ns = <300>;
  47                 };
  48                 opp-116667000 {
  49                         opp-hz = /bits/ 64 <116667000>;
  50                         clock-latency-ns = <300>;
  51                 };
  52                 opp-150000000 {
  53                         opp-hz = /bits/ 64 <150000000>;
  54                         clock-latency-ns = <300>;
  55                 };
  56                 opp-175000000 {
  57                         opp-hz = /bits/ 64 <175000000>;
  58                         clock-latency-ns = <300>;
  59                 };
  60                 opp-200000000 {
  61                         opp-hz = /bits/ 64 <200000000>;
  62                         clock-latency-ns = <300>;
  63                 };
  64                 opp-233334000 {
  65                         opp-hz = /bits/ 64 <233334000>;
  66                         clock-latency-ns = <300>;
  67                 };
  68                 opp-300000000 {
  69                         opp-hz = /bits/ 64 <300000000>;
  70                         clock-latency-ns = <300>;
  71                 };
  72                 opp-350000000 {
  73                         opp-hz = /bits/ 64 <350000000>;
  74                         clock-latency-ns = <300>;
  75                 };
  76                 opp-400000000 {
  77                         opp-hz = /bits/ 64 <400000000>;
  78                         clock-latency-ns = <300>;
  79                 };
  80                 opp-466667000 {
  81                         opp-hz = /bits/ 64 <466667000>;
  82                         clock-latency-ns = <300>;
  83                 };
  84                 opp-600000000 {
  85                         opp-hz = /bits/ 64 <600000000>;
  86                         clock-latency-ns = <300>;
  87                 };
  88                 opp-700000000 {
  89                         opp-hz = /bits/ 64 <700000000>;
  90                         clock-latency-ns = <300>;
  91                 };
  92                 opp-800000000 {
  93                         opp-hz = /bits/ 64 <800000000>;
  94                         clock-latency-ns = <300>;
  95                 };
  96                 opp-933334000 {
  97                         opp-hz = /bits/ 64 <933334000>;
  98                         clock-latency-ns = <300>;
  99                 };
 100                 opp-1200000000 {
 101                         opp-hz = /bits/ 64 <1200000000>;
 102                         clock-latency-ns = <300>;
 103                 };
 104                 opp-1400000000 {
 105                         opp-hz = /bits/ 64 <1400000000>;
 106                         clock-latency-ns = <300>;
 107                 };
 108         };
 109
 110         psci {
 111                 compatible = "arm,psci-0.2";
 112                 method = "smc";
 113         };
 114
 115         clocks {
 116                 refclk: ref {
 117                         compatible = "fixed-clock";
 118                         #clock-cells = <0>;
 119                         clock-frequency = <20000000>;
 120                 };
 121
 122                 arm_timer_clk: arm_timer_clk {
 123                         #clock-cells = <0>;
 124                         compatible = "fixed-clock";
 125                         clock-frequency = <50000000>;
 126                 };
 127         };
 128
 129         soc {
 130                 compatible = "simple-bus";
 131                 #address-cells = <1>;
 132                 #size-cells = <1>;
 133                 ranges;
 134                 interrupt-parent = <&intc>;
 135
 136                 l2: l2-cache@500c0000 {
 137                         compatible = "socionext,uniphier-system-cache";
 138                         reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
 139                               <0x506c0000 0x400>;
 140                         interrupts = <0 190 4>, <0 191 4>;
 141                         cache-unified;
 142                         cache-size = <(2 * 1024 * 1024)>;
 143                         cache-sets = <512>;
 144                         cache-line-size = <128>;
 145                         cache-level = <2>;
 146                         next-level-cache = <&l3>;
 147                 };
 148
 149                 l3: l3-cache@500c8000 {
 150                         compatible = "socionext,uniphier-system-cache";
 151                         reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
 152                               <0x506c8000 0x400>;
 153                         interrupts = <0 174 4>, <0 175 4>;
 154                         cache-unified;
 155                         cache-size = <(2 * 1024 * 1024)>;
 156                         cache-sets = <512>;
 157                         cache-line-size = <256>;
 158                         cache-level = <3>;
 159                 };
 160
 161                 serial0: serial@54006800 {
 162                         compatible = "socionext,uniphier-uart";
 163                         status = "disabled";
 164                         reg = <0x54006800 0x40>;
 165                         interrupts = <0 33 4>;
 166                         pinctrl-names = "default";
 167                         pinctrl-0 = <&pinctrl_uart0>;
 168                         clocks = <&peri_clk 0>;
 169                 };
 170
 171                 serial1: serial@54006900 {
 172                         compatible = "socionext,uniphier-uart";
 173                         status = "disabled";
 174                         reg = <0x54006900 0x40>;
 175                         interrupts = <0 35 4>;
 176                         pinctrl-names = "default";
 177                         pinctrl-0 = <&pinctrl_uart1>;
 178                         clocks = <&peri_clk 1>;
 179                 };
 180
 181                 serial2: serial@54006a00 {
 182                         compatible = "socionext,uniphier-uart";
 183                         status = "disabled";
 184                         reg = <0x54006a00 0x40>;
 185                         interrupts = <0 37 4>;
 186                         pinctrl-names = "default";
 187                         pinctrl-0 = <&pinctrl_uart2>;
 188                         clocks = <&peri_clk 2>;
 189                 };
 190
 191                 serial3: serial@54006b00 {
 192                         compatible = "socionext,uniphier-uart";
 193                         status = "disabled";
 194                         reg = <0x54006b00 0x40>;
 195                         interrupts = <0 177 4>;
 196                         pinctrl-names = "default";
 197                         pinctrl-0 = <&pinctrl_uart3>;
 198                         clocks = <&peri_clk 3>;
 199                 };
 200
 201                 i2c0: i2c@58780000 {
 202                         compatible = "socionext,uniphier-fi2c";
 203                         status = "disabled";
 204                         reg = <0x58780000 0x80>;
 205                         #address-cells = <1>;
 206                         #size-cells = <0>;
 207                         interrupts = <0 41 4>;
 208                         pinctrl-names = "default";
 209                         pinctrl-0 = <&pinctrl_i2c0>;
 210                         clocks = <&peri_clk 4>;
 211                         clock-frequency = <100000>;
 212                 };
 213
 214                 i2c1: i2c@58781000 {
 215                         compatible = "socionext,uniphier-fi2c";
 216                         status = "disabled";
 217                         reg = <0x58781000 0x80>;
 218                         #address-cells = <1>;
 219                         #size-cells = <0>;
 220                         interrupts = <0 42 4>;
 221                         pinctrl-names = "default";
 222                         pinctrl-0 = <&pinctrl_i2c1>;
 223                         clocks = <&peri_clk 5>;
 224                         clock-frequency = <100000>;
 225                 };
 226
 227                 i2c2: i2c@58782000 {
 228                         compatible = "socionext,uniphier-fi2c";
 229                         status = "disabled";
 230                         reg = <0x58782000 0x80>;
 231                         #address-cells = <1>;
 232                         #size-cells = <0>;
 233                         interrupts = <0 43 4>;
 234                         pinctrl-names = "default";
 235                         pinctrl-0 = <&pinctrl_i2c2>;
 236                         clocks = <&peri_clk 6>;
 237                         clock-frequency = <100000>;
 238                 };
 239
 240                 i2c3: i2c@58783000 {
 241                         compatible = "socionext,uniphier-fi2c";
 242                         status = "disabled";
 243                         reg = <0x58783000 0x80>;
 244                         #address-cells = <1>;
 245                         #size-cells = <0>;
 246                         interrupts = <0 44 4>;
 247                         pinctrl-names = "default";
 248                         pinctrl-0 = <&pinctrl_i2c3>;
 249                         clocks = <&peri_clk 7>;
 250                         clock-frequency = <100000>;
 251                 };
 252
 253                 /* i2c4 does not exist */
 254
 255                 /* chip-internal connection for DMD */
 256                 i2c5: i2c@58785000 {
 257                         compatible = "socionext,uniphier-fi2c";
 258                         reg = <0x58785000 0x80>;
 259                         #address-cells = <1>;
 260                         #size-cells = <0>;
 261                         interrupts = <0 25 4>;
 262                         clocks = <&peri_clk 9>;
 263                         clock-frequency = <400000>;
 264                 };
 265
 266                 /* chip-internal connection for HDMI */
 267                 i2c6: i2c@58786000 {
 268                         compatible = "socionext,uniphier-fi2c";
 269                         reg = <0x58786000 0x80>;
 270                         #address-cells = <1>;
 271                         #size-cells = <0>;
 272                         interrupts = <0 26 4>;
 273                         clocks = <&peri_clk 10>;
 274                         clock-frequency = <400000>;
 275                 };
 276
 277                 system_bus: system-bus@58c00000 {
 278                         compatible = "socionext,uniphier-system-bus";
 279                         status = "disabled";
 280                         reg = <0x58c00000 0x400>;
 281                         #address-cells = <2>;
 282                         #size-cells = <1>;
 283                         pinctrl-names = "default";
 284                         pinctrl-0 = <&pinctrl_system_bus>;
 285                 };
 286
 287                 smpctrl@59801000 {
 288                         compatible = "socionext,uniphier-smpctrl";
 289                         reg = <0x59801000 0x400>;
 290                 };
 291
 292                 sdctrl@59810000 {
 293                         compatible = "socionext,uniphier-pro5-sdctrl",
 294                                      "simple-mfd", "syscon";
 295                         reg = <0x59810000 0x400>;
 296
 297                         sd_clk: clock {
 298                                 compatible = "socionext,uniphier-pro5-sd-clock";
 299                                 #clock-cells = <1>;
 300                         };
 301
 302                         sd_rst: reset {
 303                                 compatible = "socionext,uniphier-pro5-sd-reset";
 304                                 #reset-cells = <1>;
 305                         };
 306                 };
 307
 308                 perictrl@59820000 {
 309                         compatible = "socionext,uniphier-pro5-perictrl",
 310                                      "simple-mfd", "syscon";
 311                         reg = <0x59820000 0x200>;
 312
 313                         peri_clk: clock {
 314                                 compatible = "socionext,uniphier-pro5-peri-clock";
 315                                 #clock-cells = <1>;
 316                         };
 317
 318                         peri_rst: reset {
 319                                 compatible = "socionext,uniphier-pro5-peri-reset";
 320                                 #reset-cells = <1>;
 321                         };
 322                 };
 323
 324                 soc-glue@5f800000 {
 325                         compatible = "socionext,uniphier-pro5-soc-glue",
 326                                      "simple-mfd", "syscon";
 327                         reg = <0x5f800000 0x2000>;
 328
 329                         pinctrl: pinctrl {
 330                                 compatible = "socionext,uniphier-pro5-pinctrl";
 331                         };
 332                 };
 333
 334                 aidet: aidet@5fc20000 {
 335                         compatible = "socionext,uniphier-pro5-aidet";
 336                         reg = <0x5fc20000 0x200>;
 337                         interrupt-controller;
 338                         #interrupt-cells = <2>;
 339                 };
 340
 341                 timer@60000200 {
 342                         compatible = "arm,cortex-a9-global-timer";
 343                         reg = <0x60000200 0x20>;
 344                         interrupts = <1 11 0x304>;
 345                         clocks = <&arm_timer_clk>;
 346                 };
 347
 348                 timer@60000600 {
 349                         compatible = "arm,cortex-a9-twd-timer";
 350                         reg = <0x60000600 0x20>;
 351                         interrupts = <1 13 0x304>;
 352                         clocks = <&arm_timer_clk>;
 353                 };
 354
 355                 intc: interrupt-controller@60001000 {
 356                         compatible = "arm,cortex-a9-gic";
 357                         reg = <0x60001000 0x1000>,
 358                               <0x60000100 0x100>;
 359                         #interrupt-cells = <3>;
 360                         interrupt-controller;
 361                 };
 362
 363                 sysctrl@61840000 {
 364                         compatible = "socionext,uniphier-pro5-sysctrl",
 365                                      "simple-mfd", "syscon";
 366                         reg = <0x61840000 0x10000>;
 367
 368                         sys_clk: clock {
 369                                 compatible = "socionext,uniphier-pro5-clock";
 370                                 #clock-cells = <1>;
 371                         };
 372
 373                         sys_rst: reset {
 374                                 compatible = "socionext,uniphier-pro5-reset";
 375                                 #reset-cells = <1>;
 376                         };
 377                 };
 378
 379                 nand: nand@68000000 {
 380                         compatible = "socionext,uniphier-denali-nand-v5b";
 381                         status = "disabled";
 382                         reg-names = "nand_data", "denali_reg";
 383                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 384                         interrupts = <0 65 4>;
 385                         pinctrl-names = "default";
 386                         pinctrl-0 = <&pinctrl_nand2cs>;
 387                         clocks = <&sys_clk 2>;
 388                 };
 389         };
 390 };
 391
 392 #include "uniphier-pinctrl.dtsi"