2 * Device Tree Source for UniPhier Pro5 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
46 /include/ "uniphier-common32.dtsi"
49 compatible = "socionext,uniphier-pro5";
57 compatible = "arm,cortex-a9";
59 enable-method = "psci";
60 next-level-cache = <&l2>;
65 compatible = "arm,cortex-a9";
67 enable-method = "psci";
68 next-level-cache = <&l2>;
73 arm_timer_clk: arm_timer_clk {
75 compatible = "fixed-clock";
76 clock-frequency = <50000000>;
82 l2: l2-cache@500c0000 {
83 compatible = "socionext,uniphier-system-cache";
84 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
85 interrupts = <0 190 4>, <0 191 4>;
87 cache-size = <(2 * 1024 * 1024)>;
89 cache-line-size = <128>;
91 next-level-cache = <&l3>;
94 l3: l3-cache@500c8000 {
95 compatible = "socionext,uniphier-system-cache";
96 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
97 interrupts = <0 174 4>, <0 175 4>;
99 cache-size = <(2 * 1024 * 1024)>;
101 cache-line-size = <256>;
106 compatible = "socionext,uniphier-fi2c";
108 reg = <0x58780000 0x80>;
109 #address-cells = <1>;
111 interrupts = <0 41 4>;
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_i2c0>;
114 clocks = <&peri_clk 4>;
115 clock-frequency = <100000>;
119 compatible = "socionext,uniphier-fi2c";
121 reg = <0x58781000 0x80>;
122 #address-cells = <1>;
124 interrupts = <0 42 4>;
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_i2c1>;
127 clocks = <&peri_clk 5>;
128 clock-frequency = <100000>;
132 compatible = "socionext,uniphier-fi2c";
134 reg = <0x58782000 0x80>;
135 #address-cells = <1>;
137 interrupts = <0 43 4>;
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_i2c2>;
140 clocks = <&peri_clk 6>;
141 clock-frequency = <100000>;
145 compatible = "socionext,uniphier-fi2c";
147 reg = <0x58783000 0x80>;
148 #address-cells = <1>;
150 interrupts = <0 44 4>;
151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_i2c3>;
153 clocks = <&peri_clk 7>;
154 clock-frequency = <100000>;
157 /* i2c4 does not exist */
159 /* chip-internal connection for DMD */
161 compatible = "socionext,uniphier-fi2c";
162 reg = <0x58785000 0x80>;
163 #address-cells = <1>;
165 interrupts = <0 25 4>;
166 clocks = <&peri_clk 9>;
167 clock-frequency = <400000>;
170 /* chip-internal connection for HDMI */
172 compatible = "socionext,uniphier-fi2c";
173 reg = <0x58786000 0x80>;
174 #address-cells = <1>;
176 interrupts = <0 26 4>;
177 clocks = <&peri_clk 10>;
178 clock-frequency = <400000>;
183 clock-frequency = <20000000>;
187 compatible = "socionext,uniphier-pro5-sd-clock";
191 compatible = "socionext,uniphier-pro5-sd-reset";
195 compatible = "socionext,uniphier-pro5-peri-clock";
199 compatible = "socionext,uniphier-pro5-peri-reset";
203 compatible = "socionext,uniphier-pro5-pinctrl";
207 compatible = "socionext,uniphier-pro5-clock";
211 compatible = "socionext,uniphier-pro5-reset";