1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier Pro4 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "socionext,uniphier-pro4";
22 compatible = "arm,cortex-a9";
24 enable-method = "psci";
25 next-level-cache = <&l2>;
30 compatible = "arm,cortex-a9";
32 enable-method = "psci";
33 next-level-cache = <&l2>;
38 compatible = "arm,psci-0.2";
44 compatible = "fixed-clock";
46 clock-frequency = <25000000>;
49 arm_timer_clk: arm-timer {
51 compatible = "fixed-clock";
52 clock-frequency = <50000000>;
57 compatible = "simple-bus";
61 interrupt-parent = <&intc>;
63 l2: cache-controller@500c0000 {
64 compatible = "socionext,uniphier-system-cache";
65 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
67 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
70 cache-size = <(768 * 1024)>;
72 cache-line-size = <128>;
77 compatible = "socionext,uniphier-scssi";
79 reg = <0x54006000 0x100>;
82 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_spi0>;
85 clocks = <&peri_clk 11>;
86 resets = <&peri_rst 11>;
89 serial0: serial@54006800 {
90 compatible = "socionext,uniphier-uart";
92 reg = <0x54006800 0x40>;
93 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_uart0>;
96 clocks = <&peri_clk 0>;
97 resets = <&peri_rst 0>;
100 serial1: serial@54006900 {
101 compatible = "socionext,uniphier-uart";
103 reg = <0x54006900 0x40>;
104 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_uart1>;
107 clocks = <&peri_clk 1>;
108 resets = <&peri_rst 1>;
111 serial2: serial@54006a00 {
112 compatible = "socionext,uniphier-uart";
114 reg = <0x54006a00 0x40>;
115 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_uart2>;
118 clocks = <&peri_clk 2>;
119 resets = <&peri_rst 2>;
122 serial3: serial@54006b00 {
123 compatible = "socionext,uniphier-uart";
125 reg = <0x54006b00 0x40>;
126 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_uart3>;
129 clocks = <&peri_clk 3>;
130 resets = <&peri_rst 3>;
133 gpio: gpio@55000000 {
134 compatible = "socionext,uniphier-gpio";
135 reg = <0x55000000 0x200>;
136 interrupt-parent = <&aidet>;
137 interrupt-controller;
138 #interrupt-cells = <2>;
141 gpio-ranges = <&pinctrl 0 0 0>;
142 gpio-ranges-group-names = "gpio_range";
144 socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
148 compatible = "socionext,uniphier-fi2c";
150 reg = <0x58780000 0x80>;
151 #address-cells = <1>;
153 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_i2c0>;
156 clocks = <&peri_clk 4>;
157 resets = <&peri_rst 4>;
158 clock-frequency = <100000>;
162 compatible = "socionext,uniphier-fi2c";
164 reg = <0x58781000 0x80>;
165 #address-cells = <1>;
167 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_i2c1>;
170 clocks = <&peri_clk 5>;
171 resets = <&peri_rst 5>;
172 clock-frequency = <100000>;
176 compatible = "socionext,uniphier-fi2c";
178 reg = <0x58782000 0x80>;
179 #address-cells = <1>;
181 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
182 pinctrl-names = "default";
183 pinctrl-0 = <&pinctrl_i2c2>;
184 clocks = <&peri_clk 6>;
185 resets = <&peri_rst 6>;
186 clock-frequency = <100000>;
190 compatible = "socionext,uniphier-fi2c";
192 reg = <0x58783000 0x80>;
193 #address-cells = <1>;
195 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_i2c3>;
198 clocks = <&peri_clk 7>;
199 resets = <&peri_rst 7>;
200 clock-frequency = <100000>;
203 /* i2c4 does not exist */
205 /* chip-internal connection for DMD */
207 compatible = "socionext,uniphier-fi2c";
208 reg = <0x58785000 0x80>;
209 #address-cells = <1>;
211 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&peri_clk 9>;
213 resets = <&peri_rst 9>;
214 clock-frequency = <400000>;
217 /* chip-internal connection for HDMI */
219 compatible = "socionext,uniphier-fi2c";
220 reg = <0x58786000 0x80>;
221 #address-cells = <1>;
223 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&peri_clk 10>;
225 resets = <&peri_rst 10>;
226 clock-frequency = <400000>;
229 system_bus: system-bus@58c00000 {
230 compatible = "socionext,uniphier-system-bus";
232 reg = <0x58c00000 0x400>;
233 #address-cells = <2>;
235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_system_bus>;
240 compatible = "socionext,uniphier-smpctrl";
241 reg = <0x59801000 0x400>;
245 compatible = "socionext,uniphier-pro4-mioctrl",
246 "simple-mfd", "syscon";
247 reg = <0x59810000 0x800>;
250 compatible = "socionext,uniphier-pro4-mio-clock";
255 compatible = "socionext,uniphier-pro4-mio-reset";
261 compatible = "socionext,uniphier-pro4-perictrl",
262 "simple-mfd", "syscon";
263 reg = <0x59820000 0x200>;
266 compatible = "socionext,uniphier-pro4-peri-clock";
271 compatible = "socionext,uniphier-pro4-peri-reset";
276 dmac: dma-controller@5a000000 {
277 compatible = "socionext,uniphier-mio-dmac";
278 reg = <0x5a000000 0x1000>;
279 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&mio_clk 7>;
288 resets = <&mio_rst 7>;
293 compatible = "socionext,uniphier-sd-v2.91";
295 reg = <0x5a400000 0x200>;
296 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
297 pinctrl-names = "default", "uhs";
298 pinctrl-0 = <&pinctrl_sd>;
299 pinctrl-1 = <&pinctrl_sd_uhs>;
300 clocks = <&mio_clk 0>;
301 reset-names = "host", "bridge";
302 resets = <&mio_rst 0>, <&mio_rst 3>;
313 compatible = "socionext,uniphier-sd-v2.91";
315 reg = <0x5a500000 0x200>;
316 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
317 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_emmc>;
319 clocks = <&mio_clk 1>;
320 reset-names = "host", "bridge", "hw";
321 resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
331 compatible = "socionext,uniphier-sd-v2.91";
333 reg = <0x5a600000 0x200>;
334 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&pinctrl_sd1>;
337 clocks = <&mio_clk 2>;
338 reset-names = "host", "bridge";
339 resets = <&mio_rst 2>, <&mio_rst 5>;
347 compatible = "socionext,uniphier-ehci", "generic-ehci";
349 reg = <0x5a800100 0x100>;
350 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
351 pinctrl-names = "default";
352 pinctrl-0 = <&pinctrl_usb2>;
353 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
355 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
359 has-transaction-translator;
363 compatible = "socionext,uniphier-ehci", "generic-ehci";
365 reg = <0x5a810100 0x100>;
366 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
367 pinctrl-names = "default";
368 pinctrl-0 = <&pinctrl_usb3>;
369 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
371 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
375 has-transaction-translator;
378 soc_glue: soc-glue@5f800000 {
379 compatible = "socionext,uniphier-pro4-soc-glue",
380 "simple-mfd", "syscon";
381 reg = <0x5f800000 0x2000>;
384 compatible = "socionext,uniphier-pro4-pinctrl";
388 compatible = "socionext,uniphier-pro4-usb2-phy";
389 #address-cells = <1>;
405 vbus-supply = <&usb0_vbus>;
411 vbus-supply = <&usb1_vbus>;
416 compatible = "socionext,uniphier-pro4-sg-clock";
422 compatible = "socionext,uniphier-pro4-soc-glue-debug",
424 #address-cells = <1>;
426 ranges = <0 0x5f900000 0x2000>;
429 compatible = "socionext,uniphier-efuse";
434 compatible = "socionext,uniphier-efuse";
439 compatible = "socionext,uniphier-efuse";
444 xdmac: dma-controller@5fc10000 {
445 compatible = "socionext,uniphier-xdmac";
446 reg = <0x5fc10000 0x5300>;
447 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
452 aidet: interrupt-controller@5fc20000 {
453 compatible = "socionext,uniphier-pro4-aidet";
454 reg = <0x5fc20000 0x200>;
455 interrupt-controller;
456 #interrupt-cells = <2>;
460 compatible = "arm,cortex-a9-global-timer";
461 reg = <0x60000200 0x20>;
462 interrupts = <GIC_PPI 11
463 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
464 clocks = <&arm_timer_clk>;
468 compatible = "arm,cortex-a9-twd-timer";
469 reg = <0x60000600 0x20>;
470 interrupts = <GIC_PPI 13
471 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
472 clocks = <&arm_timer_clk>;
475 intc: interrupt-controller@60001000 {
476 compatible = "arm,cortex-a9-gic";
477 reg = <0x60001000 0x1000>,
479 #interrupt-cells = <3>;
480 interrupt-controller;
484 compatible = "socionext,uniphier-pro4-sysctrl",
485 "simple-mfd", "syscon";
486 reg = <0x61840000 0x10000>;
489 compatible = "socionext,uniphier-pro4-clock";
494 compatible = "socionext,uniphier-pro4-reset";
499 eth: ethernet@65000000 {
500 compatible = "socionext,uniphier-pro4-ave4";
502 reg = <0x65000000 0x8500>;
503 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
504 pinctrl-names = "default";
505 pinctrl-0 = <&pinctrl_ether_rgmii>;
506 clock-names = "gio", "ether", "ether-gb", "ether-phy";
507 clocks = <&sys_clk 12>, <&sys_clk 6>, <&sys_clk 7>,
509 reset-names = "gio", "ether";
510 resets = <&sys_rst 12>, <&sys_rst 6>;
512 local-mac-address = [00 00 00 00 00 00];
513 socionext,syscon-phy-mode = <&soc_glue 0>;
516 #address-cells = <1>;
521 ahci0: sata@65600000 {
522 compatible = "socionext,uniphier-pro4-ahci",
525 reg = <0x65600000 0x10000>;
526 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
527 clocks = <&sys_clk 12>, <&sys_clk 28>;
528 resets = <&sys_rst 12>, <&sys_rst 28>, <&ahci0_rst 3>;
529 ports-implemented = <1>;
531 assigned-clocks = <&sg_clk 0>;
532 assigned-clock-rates = <25000000>;
535 sata-controller@65700000 {
536 compatible = "socionext,uniphier-pxs2-ahci-glue",
538 #address-cells = <1>;
540 ranges = <0 0x65700000 0x100>;
542 ahci0_rst: reset-controller@0 {
543 compatible = "socionext,uniphier-pro4-ahci-reset";
545 clock-names = "gio", "link";
546 clocks = <&sys_clk 12>, <&sys_clk 28>;
547 reset-names = "gio", "link";
548 resets = <&sys_rst 12>, <&sys_rst 28>;
552 ahci0_phy: sata-phy@10 {
553 compatible = "socionext,uniphier-pro4-ahci-phy";
555 clock-names = "link", "gio";
556 clocks = <&sys_clk 28>, <&sys_clk 12>;
557 reset-names = "link", "gio", "phy",
559 resets = <&sys_rst 28>, <&sys_rst 12>,
561 <&ahci0_rst 0>, <&ahci0_rst 1>,
567 ahci1: sata@65800000 {
568 compatible = "socionext,uniphier-pro4-ahci",
571 reg = <0x65800000 0x10000>;
572 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&sys_clk 12>, <&sys_clk 29>;
574 resets = <&sys_rst 12>, <&sys_rst 29>, <&ahci1_rst 3>;
575 ports-implemented = <1>;
577 assigned-clocks = <&sg_clk 0>;
578 assigned-clock-rates = <25000000>;
581 sata-controller@65900000 {
582 compatible = "socionext,uniphier-pro4-ahci-glue",
584 #address-cells = <1>;
586 ranges = <0 0x65900000 0x100>;
588 ahci1_rst: reset-controller@0 {
589 compatible = "socionext,uniphier-pro4-ahci-reset";
591 clock-names = "gio", "link";
592 clocks = <&sys_clk 12>, <&sys_clk 29>;
593 reset-names = "gio", "link";
594 resets = <&sys_rst 12>, <&sys_rst 29>;
598 ahci1_phy: sata-phy@10 {
599 compatible = "socionext,uniphier-pro4-ahci-phy";
601 clock-names = "link", "gio";
602 clocks = <&sys_clk 29>, <&sys_clk 12>;
603 reset-names = "link", "gio", "phy",
605 resets = <&sys_rst 29>, <&sys_rst 12>,
607 <&ahci1_rst 0>, <&ahci1_rst 1>,
614 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
616 reg = <0x65a00000 0xcd00>;
617 interrupt-names = "host", "peripheral";
618 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
620 pinctrl-names = "default";
621 pinctrl-0 = <&pinctrl_usb0>;
622 clock-names = "ref", "bus_early", "suspend";
623 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
624 resets = <&usb0_rst 4>;
625 phys = <&usb_phy2>, <&usb0_ssphy>;
629 usb-controller@65b00000 {
630 compatible = "socionext,uniphier-pro4-dwc3-glue",
632 #address-cells = <1>;
634 ranges = <0 0x65b00000 0x100>;
636 usb0_vbus: regulator@0 {
637 compatible = "socionext,uniphier-pro4-usb3-regulator";
639 clock-names = "gio", "link";
640 clocks = <&sys_clk 12>, <&sys_clk 14>;
641 reset-names = "gio", "link";
642 resets = <&sys_rst 12>, <&sys_rst 14>;
645 usb0_ssphy: ss-phy@10 {
646 compatible = "socionext,uniphier-pro4-usb3-ssphy";
649 clock-names = "gio", "link";
650 clocks = <&sys_clk 12>, <&sys_clk 14>;
651 reset-names = "gio", "link";
652 resets = <&sys_rst 12>, <&sys_rst 14>;
653 vbus-supply = <&usb0_vbus>;
657 compatible = "socionext,uniphier-pro4-usb3-reset";
660 clock-names = "gio", "link";
661 clocks = <&sys_clk 12>, <&sys_clk 14>;
662 reset-names = "gio", "link";
663 resets = <&sys_rst 12>, <&sys_rst 14>;
668 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
670 reg = <0x65c00000 0xcd00>;
671 interrupt-names = "host", "peripheral";
672 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
673 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
674 pinctrl-names = "default";
675 pinctrl-0 = <&pinctrl_usb1>;
676 clock-names = "ref", "bus_early", "suspend";
677 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
678 resets = <&usb1_rst 4>;
683 usb-controller@65d00000 {
684 compatible = "socionext,uniphier-pro4-dwc3-glue",
686 #address-cells = <1>;
688 ranges = <0 0x65d00000 0x100>;
690 usb1_vbus: regulator@0 {
691 compatible = "socionext,uniphier-pro4-usb3-regulator";
693 clock-names = "gio", "link";
694 clocks = <&sys_clk 12>, <&sys_clk 15>;
695 reset-names = "gio", "link";
696 resets = <&sys_rst 12>, <&sys_rst 15>;
700 compatible = "socionext,uniphier-pro4-usb3-reset";
703 clock-names = "gio", "link";
704 clocks = <&sys_clk 12>, <&sys_clk 15>;
705 reset-names = "gio", "link";
706 resets = <&sys_rst 12>, <&sys_rst 15>;
710 nand: nand-controller@68000000 {
711 compatible = "socionext,uniphier-denali-nand-v5a";
713 reg-names = "nand_data", "denali_reg";
714 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
715 #address-cells = <1>;
717 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
718 pinctrl-names = "default";
719 pinctrl-0 = <&pinctrl_nand>;
720 clock-names = "nand", "nand_x", "ecc";
721 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
722 reset-names = "nand", "reg";
723 resets = <&sys_rst 2>, <&sys_rst 2>;
728 #include "uniphier-pinctrl.dtsi"