2 * Device Tree Source for UniPhier Pro4 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
46 /include/ "uniphier-common32.dtsi"
49 compatible = "socionext,uniphier-pro4";
57 compatible = "arm,cortex-a9";
59 enable-method = "psci";
60 next-level-cache = <&l2>;
65 compatible = "arm,cortex-a9";
67 enable-method = "psci";
68 next-level-cache = <&l2>;
73 arm_timer_clk: arm_timer_clk {
75 compatible = "fixed-clock";
76 clock-frequency = <50000000>;
82 l2: l2-cache@500c0000 {
83 compatible = "socionext,uniphier-system-cache";
84 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
85 interrupts = <0 174 4>, <0 175 4>;
87 cache-size = <(768 * 1024)>;
89 cache-line-size = <128>;
94 compatible = "socionext,uniphier-fi2c";
96 reg = <0x58780000 0x80>;
99 interrupts = <0 41 4>;
100 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_i2c0>;
102 clocks = <&peri_clk 4>;
103 clock-frequency = <100000>;
107 compatible = "socionext,uniphier-fi2c";
109 reg = <0x58781000 0x80>;
110 #address-cells = <1>;
112 interrupts = <0 42 4>;
113 pinctrl-names = "default";
114 pinctrl-0 = <&pinctrl_i2c1>;
115 clocks = <&peri_clk 5>;
116 clock-frequency = <100000>;
120 compatible = "socionext,uniphier-fi2c";
122 reg = <0x58782000 0x80>;
123 #address-cells = <1>;
125 interrupts = <0 43 4>;
126 pinctrl-names = "default";
127 pinctrl-0 = <&pinctrl_i2c2>;
128 clocks = <&peri_clk 6>;
129 clock-frequency = <100000>;
133 compatible = "socionext,uniphier-fi2c";
135 reg = <0x58783000 0x80>;
136 #address-cells = <1>;
138 interrupts = <0 44 4>;
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_i2c3>;
141 clocks = <&peri_clk 7>;
142 clock-frequency = <100000>;
145 /* i2c4 does not exist */
147 /* chip-internal connection for DMD */
149 compatible = "socionext,uniphier-fi2c";
150 reg = <0x58785000 0x80>;
151 #address-cells = <1>;
153 interrupts = <0 25 4>;
154 clocks = <&peri_clk 9>;
155 clock-frequency = <400000>;
158 /* chip-internal connection for HDMI */
160 compatible = "socionext,uniphier-fi2c";
161 reg = <0x58786000 0x80>;
162 #address-cells = <1>;
164 interrupts = <0 26 4>;
165 clocks = <&peri_clk 10>;
166 clock-frequency = <400000>;
170 compatible = "socionext,uniphier-ehci", "generic-ehci";
172 reg = <0x5a800100 0x100>;
173 interrupts = <0 80 4>;
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_usb2>;
176 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
177 resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>;
181 compatible = "socionext,uniphier-ehci", "generic-ehci";
183 reg = <0x5a810100 0x100>;
184 interrupts = <0 81 4>;
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_usb3>;
187 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
188 resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>;
193 clock-frequency = <25000000>;
197 compatible = "socionext,uniphier-pro4-mio-clock";
201 compatible = "socionext,uniphier-pro4-mio-reset";
202 resets = <&sys_rst 7>;
206 compatible = "socionext,uniphier-pro4-peri-clock";
210 compatible = "socionext,uniphier-pro4-peri-reset";
214 compatible = "socionext,uniphier-pro4-pinctrl";
218 compatible = "socionext,uniphier-pro4-clock";
222 compatible = "socionext,uniphier-pro4-reset";