1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD4 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "socionext,uniphier-ld4";
22 compatible = "arm,cortex-a9";
24 enable-method = "psci";
25 next-level-cache = <&l2>;
30 compatible = "arm,psci-0.2";
36 compatible = "fixed-clock";
38 clock-frequency = <24576000>;
41 arm_timer_clk: arm-timer {
43 compatible = "fixed-clock";
44 clock-frequency = <50000000>;
49 compatible = "simple-bus";
53 interrupt-parent = <&intc>;
55 l2: cache-controller@500c0000 {
56 compatible = "socionext,uniphier-system-cache";
57 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
59 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
62 cache-size = <(512 * 1024)>;
64 cache-line-size = <128>;
69 compatible = "socionext,uniphier-scssi";
71 reg = <0x54006000 0x100>;
74 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_spi0>;
77 clocks = <&peri_clk 11>;
78 resets = <&peri_rst 11>;
81 serial0: serial@54006800 {
82 compatible = "socionext,uniphier-uart";
84 reg = <0x54006800 0x40>;
85 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_uart0>;
88 clocks = <&peri_clk 0>;
89 resets = <&peri_rst 0>;
92 serial1: serial@54006900 {
93 compatible = "socionext,uniphier-uart";
95 reg = <0x54006900 0x40>;
96 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_uart1>;
99 clocks = <&peri_clk 1>;
100 resets = <&peri_rst 1>;
103 serial2: serial@54006a00 {
104 compatible = "socionext,uniphier-uart";
106 reg = <0x54006a00 0x40>;
107 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_uart2>;
110 clocks = <&peri_clk 2>;
111 resets = <&peri_rst 2>;
114 serial3: serial@54006b00 {
115 compatible = "socionext,uniphier-uart";
117 reg = <0x54006b00 0x40>;
118 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_uart3>;
121 clocks = <&peri_clk 3>;
122 resets = <&peri_rst 3>;
125 gpio: gpio@55000000 {
126 compatible = "socionext,uniphier-gpio";
127 reg = <0x55000000 0x200>;
128 interrupt-parent = <&aidet>;
129 interrupt-controller;
130 #interrupt-cells = <2>;
133 gpio-ranges = <&pinctrl 0 0 0>;
134 gpio-ranges-group-names = "gpio_range";
136 socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
140 compatible = "socionext,uniphier-i2c";
142 reg = <0x58400000 0x40>;
143 #address-cells = <1>;
145 interrupts = <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>;
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_i2c0>;
148 clocks = <&peri_clk 4>;
149 resets = <&peri_rst 4>;
150 clock-frequency = <100000>;
154 compatible = "socionext,uniphier-i2c";
156 reg = <0x58480000 0x40>;
157 #address-cells = <1>;
159 interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>;
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_i2c1>;
162 clocks = <&peri_clk 5>;
163 resets = <&peri_rst 5>;
164 clock-frequency = <100000>;
167 /* chip-internal connection for DMD */
169 compatible = "socionext,uniphier-i2c";
170 reg = <0x58500000 0x40>;
171 #address-cells = <1>;
173 interrupts = <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>;
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_i2c2>;
176 clocks = <&peri_clk 6>;
177 resets = <&peri_rst 6>;
178 clock-frequency = <400000>;
182 compatible = "socionext,uniphier-i2c";
184 reg = <0x58580000 0x40>;
185 #address-cells = <1>;
187 interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>;
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_i2c3>;
190 clocks = <&peri_clk 7>;
191 resets = <&peri_rst 7>;
192 clock-frequency = <100000>;
195 system_bus: system-bus@58c00000 {
196 compatible = "socionext,uniphier-system-bus";
198 reg = <0x58c00000 0x400>;
199 #address-cells = <2>;
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_system_bus>;
206 compatible = "socionext,uniphier-smpctrl";
207 reg = <0x59801000 0x400>;
211 compatible = "socionext,uniphier-ld4-mioctrl",
212 "simple-mfd", "syscon";
213 reg = <0x59810000 0x800>;
216 compatible = "socionext,uniphier-ld4-mio-clock";
221 compatible = "socionext,uniphier-ld4-mio-reset";
227 compatible = "socionext,uniphier-ld4-perictrl",
228 "simple-mfd", "syscon";
229 reg = <0x59820000 0x200>;
232 compatible = "socionext,uniphier-ld4-peri-clock";
237 compatible = "socionext,uniphier-ld4-peri-reset";
242 dmac: dma-controller@5a000000 {
243 compatible = "socionext,uniphier-mio-dmac";
244 reg = <0x5a000000 0x1000>;
245 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&mio_clk 7>;
253 resets = <&mio_rst 7>;
258 compatible = "socionext,uniphier-sd-v2.91";
260 reg = <0x5a400000 0x200>;
261 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
262 pinctrl-names = "default", "uhs";
263 pinctrl-0 = <&pinctrl_sd>;
264 pinctrl-1 = <&pinctrl_sd_uhs>;
265 clocks = <&mio_clk 0>;
266 reset-names = "host", "bridge";
267 resets = <&mio_rst 0>, <&mio_rst 3>;
278 compatible = "socionext,uniphier-sd-v2.91";
280 reg = <0x5a500000 0x200>;
281 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
282 pinctrl-names = "default";
283 pinctrl-0 = <&pinctrl_emmc>;
284 clocks = <&mio_clk 1>;
285 reset-names = "host", "bridge", "hw";
286 resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
296 compatible = "socionext,uniphier-ehci", "generic-ehci";
298 reg = <0x5a800100 0x100>;
299 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
300 pinctrl-names = "default";
301 pinctrl-0 = <&pinctrl_usb0>;
302 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
304 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
306 has-transaction-translator;
310 compatible = "socionext,uniphier-ehci", "generic-ehci";
312 reg = <0x5a810100 0x100>;
313 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_usb1>;
316 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
318 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
320 has-transaction-translator;
324 compatible = "socionext,uniphier-ehci", "generic-ehci";
326 reg = <0x5a820100 0x100>;
327 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
328 pinctrl-names = "default";
329 pinctrl-0 = <&pinctrl_usb2>;
330 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
332 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
334 has-transaction-translator;
338 compatible = "socionext,uniphier-ld4-soc-glue",
339 "simple-mfd", "syscon";
340 reg = <0x5f800000 0x2000>;
343 compatible = "socionext,uniphier-ld4-pinctrl";
348 compatible = "socionext,uniphier-ld4-soc-glue-debug",
350 #address-cells = <1>;
352 ranges = <0 0x5f900000 0x2000>;
355 compatible = "socionext,uniphier-efuse";
360 compatible = "socionext,uniphier-efuse";
366 compatible = "arm,cortex-a9-global-timer";
367 reg = <0x60000200 0x20>;
368 interrupts = <GIC_PPI 11
369 (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
370 clocks = <&arm_timer_clk>;
374 compatible = "arm,cortex-a9-twd-timer";
375 reg = <0x60000600 0x20>;
376 interrupts = <GIC_PPI 13
377 (GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
378 clocks = <&arm_timer_clk>;
381 intc: interrupt-controller@60001000 {
382 compatible = "arm,cortex-a9-gic";
383 reg = <0x60001000 0x1000>,
385 #interrupt-cells = <3>;
386 interrupt-controller;
389 aidet: interrupt-controller@61830000 {
390 compatible = "socionext,uniphier-ld4-aidet";
391 reg = <0x61830000 0x200>;
392 interrupt-controller;
393 #interrupt-cells = <2>;
397 compatible = "socionext,uniphier-ld4-sysctrl",
398 "simple-mfd", "syscon";
399 reg = <0x61840000 0x10000>;
402 compatible = "socionext,uniphier-ld4-clock";
407 compatible = "socionext,uniphier-ld4-reset";
412 nand: nand-controller@68000000 {
413 compatible = "socionext,uniphier-denali-nand-v5a";
415 reg-names = "nand_data", "denali_reg";
416 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
417 #address-cells = <1>;
419 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
420 pinctrl-names = "default";
421 pinctrl-0 = <&pinctrl_nand>;
422 clock-names = "nand", "nand_x", "ecc";
423 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
424 reset-names = "nand", "reg";
425 resets = <&sys_rst 2>, <&sys_rst 2>;
430 #include "uniphier-pinctrl.dtsi"