2 * Device Tree Source for UniPhier LD4 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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43 * OTHER DEALINGS IN THE SOFTWARE.
46 /include/ "uniphier-common32.dtsi"
49 compatible = "socionext,uniphier-ld4";
57 compatible = "arm,cortex-a9";
59 enable-method = "psci";
60 next-level-cache = <&l2>;
65 arm_timer_clk: arm_timer_clk {
67 compatible = "fixed-clock";
68 clock-frequency = <50000000>;
74 l2: l2-cache@500c0000 {
75 compatible = "socionext,uniphier-system-cache";
76 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
77 interrupts = <0 174 4>, <0 175 4>;
79 cache-size = <(512 * 1024)>;
81 cache-line-size = <128>;
86 compatible = "socionext,uniphier-i2c";
88 reg = <0x58400000 0x40>;
91 interrupts = <0 41 1>;
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_i2c0>;
94 clocks = <&peri_clk 4>;
95 clock-frequency = <100000>;
99 compatible = "socionext,uniphier-i2c";
101 reg = <0x58480000 0x40>;
102 #address-cells = <1>;
104 interrupts = <0 42 1>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_i2c1>;
107 clocks = <&peri_clk 5>;
108 clock-frequency = <100000>;
111 /* chip-internal connection for DMD */
113 compatible = "socionext,uniphier-i2c";
114 reg = <0x58500000 0x40>;
115 #address-cells = <1>;
117 interrupts = <0 43 1>;
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_i2c2>;
120 clocks = <&peri_clk 6>;
121 clock-frequency = <400000>;
125 compatible = "socionext,uniphier-i2c";
127 reg = <0x58580000 0x40>;
128 #address-cells = <1>;
130 interrupts = <0 44 1>;
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_i2c3>;
133 clocks = <&peri_clk 7>;
134 clock-frequency = <100000>;
138 compatible = "socionext,uniphier-ehci", "generic-ehci";
140 reg = <0x5a800100 0x100>;
141 interrupts = <0 80 4>;
142 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_usb0>;
144 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
145 resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>;
149 compatible = "socionext,uniphier-ehci", "generic-ehci";
151 reg = <0x5a810100 0x100>;
152 interrupts = <0 81 4>;
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_usb1>;
155 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
156 resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>;
160 compatible = "socionext,uniphier-ehci", "generic-ehci";
162 reg = <0x5a820100 0x100>;
163 interrupts = <0 82 4>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_usb2>;
166 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
167 resets = <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>, <&sys_rst 8>;
173 clock-frequency = <24576000>;
177 interrupts = <0 29 4>;
181 compatible = "socionext,uniphier-ld4-mio-clock";
185 compatible = "socionext,uniphier-ld4-mio-reset";
186 resets = <&sys_rst 7>;
190 compatible = "socionext,uniphier-ld4-peri-clock";
194 compatible = "socionext,uniphier-ld4-peri-reset";
198 compatible = "socionext,uniphier-ld4-pinctrl";
202 compatible = "socionext,uniphier-ld4-clock";
206 compatible = "socionext,uniphier-ld4-reset";