1 #include <dt-bindings/input/input.h>
2 #include "tegra30.dtsi"
5 * This file contains common DT entry for all fab version of Cardhu.
6 * There is multiple fab version of Cardhu starting from A01 to A07.
7 * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
8 * A02 will have different sets of GPIOs for fixed regulator compare to
9 * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
10 * compatible with fab version A04. Based on Cardhu fab version, the
11 * related dts file need to be chosen like for Cardhu fab version A02,
12 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
13 * tegra30-cardhu-a04.dts.
14 * The identification of board is done in two ways, by looking the sticker
15 * on PCB and by reading board id eeprom.
16 * The sticker will have number like 600-81291-1000-002 C.3. In this 4th
17 * number is the fab version like here it is 002 and hence fab version A02.
18 * The (downstream internal) U-Boot of Cardhu display the board-id as
20 * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
21 * In this Fab version is 02 i.e. A02.
22 * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
23 * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
28 model = "NVIDIA Tegra30 Cardhu evaluation board";
29 compatible = "nvidia,cardhu", "nvidia,tegra30";
32 rtc0 = "/i2c@7000d000/tps65911@2d";
33 rtc1 = "/rtc@7000e000";
39 reg = <0x80000000 0x40000000>;
42 pcie-controller@00003000 {
45 /* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */
46 avdd-pexb-supply = <&ldo1_reg>;
47 vdd-pexb-supply = <&ldo1_reg>;
48 avdd-pex-pll-supply = <&ldo1_reg>;
49 hvdd-pex-supply = <&pex_hvdd_3v3_reg>;
50 vddio-pex-ctl-supply = <&sys_3v3_reg>;
51 avdd-plle-supply = <&ldo2_reg>;
54 nvidia,num-lanes = <4>;
58 nvidia,num-lanes = <1>;
63 nvidia,num-lanes = <1>;
72 nvidia,panel = <&panel>;
78 pinctrl-names = "default";
79 pinctrl-0 = <&state_default>;
81 state_default: pinmux {
83 nvidia,pins = "sdmmc1_clk_pz0";
84 nvidia,function = "sdmmc1";
85 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
86 nvidia,tristate = <TEGRA_PIN_DISABLE>;
89 nvidia,pins = "sdmmc1_cmd_pz1",
94 nvidia,function = "sdmmc1";
95 nvidia,pull = <TEGRA_PIN_PULL_UP>;
96 nvidia,tristate = <TEGRA_PIN_DISABLE>;
99 nvidia,pins = "sdmmc3_clk_pa6";
100 nvidia,function = "sdmmc3";
101 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
102 nvidia,tristate = <TEGRA_PIN_DISABLE>;
105 nvidia,pins = "sdmmc3_cmd_pa7",
110 nvidia,function = "sdmmc3";
111 nvidia,pull = <TEGRA_PIN_PULL_UP>;
112 nvidia,tristate = <TEGRA_PIN_DISABLE>;
115 nvidia,pins = "sdmmc4_clk_pcc4",
117 nvidia,function = "sdmmc4";
118 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
119 nvidia,tristate = <TEGRA_PIN_DISABLE>;
122 nvidia,pins = "sdmmc4_dat0_paa0",
130 nvidia,function = "sdmmc4";
131 nvidia,pull = <TEGRA_PIN_PULL_UP>;
132 nvidia,tristate = <TEGRA_PIN_DISABLE>;
135 nvidia,pins = "dap2_fs_pa2",
139 nvidia,function = "i2s1";
140 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
141 nvidia,tristate = <TEGRA_PIN_DISABLE>;
144 nvidia,pins = "drive_sdio3";
145 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
146 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
147 nvidia,pull-down-strength = <46>;
148 nvidia,pull-up-strength = <42>;
149 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
150 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
153 nvidia,pins = "uart3_txd_pw6",
157 nvidia,function = "uartc";
158 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
159 nvidia,tristate = <TEGRA_PIN_DISABLE>;
169 compatible = "nvidia,tegra30-hsuart";
177 panelddc: i2c@7000c000 {
179 clock-frequency = <100000>;
184 clock-frequency = <100000>;
189 clock-frequency = <100000>;
191 /* ALS and Proximity sensor */
193 compatible = "isil,isl29028";
195 interrupt-parent = <&gpio>;
196 interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
200 compatible = "nxp,pca9546";
201 #address-cells = <1>;
204 reset-gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_LOW>;
210 clock-frequency = <100000>;
215 clock-frequency = <100000>;
218 compatible = "wlf,wm8903";
220 interrupt-parent = <&gpio>;
221 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
227 micdet-delay = <100>;
228 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
232 compatible = "ti,tps65911";
235 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
236 #interrupt-cells = <2>;
237 interrupt-controller;
239 ti,system-power-controller;
244 vcc1-supply = <&vdd_ac_bat_reg>;
245 vcc2-supply = <&vdd_ac_bat_reg>;
246 vcc3-supply = <&vio_reg>;
247 vcc4-supply = <&vdd_5v0_reg>;
248 vcc5-supply = <&vdd_ac_bat_reg>;
249 vcc6-supply = <&vdd2_reg>;
250 vcc7-supply = <&vdd_ac_bat_reg>;
251 vccio-supply = <&vdd_ac_bat_reg>;
255 regulator-name = "vddio_ddr_1v2";
256 regulator-min-microvolt = <1200000>;
257 regulator-max-microvolt = <1200000>;
262 regulator-name = "vdd_1v5_gen";
263 regulator-min-microvolt = <1500000>;
264 regulator-max-microvolt = <1500000>;
268 vddctrl_reg: vddctrl {
269 regulator-name = "vdd_cpu,vdd_sys";
270 regulator-min-microvolt = <1000000>;
271 regulator-max-microvolt = <1000000>;
276 regulator-name = "vdd_1v8_gen";
277 regulator-min-microvolt = <1800000>;
278 regulator-max-microvolt = <1800000>;
283 regulator-name = "vdd_pexa,vdd_pexb";
284 regulator-min-microvolt = <1050000>;
285 regulator-max-microvolt = <1050000>;
289 regulator-name = "vdd_sata,avdd_plle";
290 regulator-min-microvolt = <1050000>;
291 regulator-max-microvolt = <1050000>;
294 /* LDO3 is not connected to anything */
297 regulator-name = "vdd_rtc";
298 regulator-min-microvolt = <1200000>;
299 regulator-max-microvolt = <1200000>;
304 regulator-name = "vddio_sdmmc,avdd_vdac";
305 regulator-min-microvolt = <3300000>;
306 regulator-max-microvolt = <3300000>;
311 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
312 regulator-min-microvolt = <1200000>;
313 regulator-max-microvolt = <1200000>;
317 regulator-name = "vdd_pllm,x,u,a_p_c_s";
318 regulator-min-microvolt = <1200000>;
319 regulator-max-microvolt = <1200000>;
324 regulator-name = "vdd_ddr_hs";
325 regulator-min-microvolt = <1000000>;
326 regulator-max-microvolt = <1000000>;
332 temperature-sensor@4c {
333 compatible = "onnn,nct1008";
335 vcc-supply = <&sys_3v3_reg>;
336 interrupt-parent = <&gpio>;
337 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
341 compatible = "ti,tps62361";
344 regulator-name = "tps62361-vout";
345 regulator-min-microvolt = <500000>;
346 regulator-max-microvolt = <1500000>;
356 spi-max-frequency = <25000000>;
358 compatible = "winbond,w25q32";
360 spi-max-frequency = <20000000>;
366 nvidia,invert-interrupt;
367 nvidia,suspend-mode = <1>;
368 nvidia,cpu-pwr-good-time = <2000>;
369 nvidia,cpu-pwr-off-time = <200>;
370 nvidia,core-pwr-good-time = <3845 3845>;
371 nvidia,core-pwr-off-time = <0>;
372 nvidia,core-power-req-active-high;
373 nvidia,sys-clock-req-active-high;
384 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
385 wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
386 power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
401 vbus-supply = <&usb3_vbus_reg>;
405 backlight: backlight {
406 compatible = "pwm-backlight";
408 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
409 power-supply = <&vdd_bl_reg>;
410 pwms = <&pwm 0 5000000>;
412 brightness-levels = <0 4 8 16 32 64 128 255>;
413 default-brightness-level = <6>;
417 compatible = "simple-bus";
418 #address-cells = <1>;
422 compatible = "fixed-clock";
425 clock-frequency = <32768>;
430 compatible = "chunghwa,claa101wb01", "simple-panel";
431 ddc-i2c-bus = <&panelddc>;
433 power-supply = <&vdd_pnl1_reg>;
434 enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>;
436 backlight = <&backlight>;
440 compatible = "simple-bus";
441 #address-cells = <1>;
444 vdd_ac_bat_reg: regulator@0 {
445 compatible = "regulator-fixed";
447 regulator-name = "vdd_ac_bat";
448 regulator-min-microvolt = <5000000>;
449 regulator-max-microvolt = <5000000>;
453 cam_1v8_reg: regulator@1 {
454 compatible = "regulator-fixed";
456 regulator-name = "cam_1v8";
457 regulator-min-microvolt = <1800000>;
458 regulator-max-microvolt = <1800000>;
460 gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
461 vin-supply = <&vio_reg>;
464 cp_5v_reg: regulator@2 {
465 compatible = "regulator-fixed";
467 regulator-name = "cp_5v";
468 regulator-min-microvolt = <5000000>;
469 regulator-max-microvolt = <5000000>;
473 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
476 emmc_3v3_reg: regulator@3 {
477 compatible = "regulator-fixed";
479 regulator-name = "emmc_3v3";
480 regulator-min-microvolt = <3300000>;
481 regulator-max-microvolt = <3300000>;
485 gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
486 vin-supply = <&sys_3v3_reg>;
489 modem_3v3_reg: regulator@4 {
490 compatible = "regulator-fixed";
492 regulator-name = "modem_3v3";
493 regulator-min-microvolt = <3300000>;
494 regulator-max-microvolt = <3300000>;
496 gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
499 pex_hvdd_3v3_reg: regulator@5 {
500 compatible = "regulator-fixed";
502 regulator-name = "pex_hvdd_3v3";
503 regulator-min-microvolt = <3300000>;
504 regulator-max-microvolt = <3300000>;
506 gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
507 vin-supply = <&sys_3v3_reg>;
510 vdd_cam1_ldo_reg: regulator@6 {
511 compatible = "regulator-fixed";
513 regulator-name = "vdd_cam1_ldo";
514 regulator-min-microvolt = <2800000>;
515 regulator-max-microvolt = <2800000>;
517 gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
518 vin-supply = <&sys_3v3_reg>;
521 vdd_cam2_ldo_reg: regulator@7 {
522 compatible = "regulator-fixed";
524 regulator-name = "vdd_cam2_ldo";
525 regulator-min-microvolt = <2800000>;
526 regulator-max-microvolt = <2800000>;
528 gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
529 vin-supply = <&sys_3v3_reg>;
532 vdd_cam3_ldo_reg: regulator@8 {
533 compatible = "regulator-fixed";
535 regulator-name = "vdd_cam3_ldo";
536 regulator-min-microvolt = <3300000>;
537 regulator-max-microvolt = <3300000>;
539 gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
540 vin-supply = <&sys_3v3_reg>;
543 vdd_com_reg: regulator@9 {
544 compatible = "regulator-fixed";
546 regulator-name = "vdd_com";
547 regulator-min-microvolt = <3300000>;
548 regulator-max-microvolt = <3300000>;
552 gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
553 vin-supply = <&sys_3v3_reg>;
556 vdd_fuse_3v3_reg: regulator@10 {
557 compatible = "regulator-fixed";
559 regulator-name = "vdd_fuse_3v3";
560 regulator-min-microvolt = <3300000>;
561 regulator-max-microvolt = <3300000>;
563 gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
564 vin-supply = <&sys_3v3_reg>;
567 vdd_pnl1_reg: regulator@11 {
568 compatible = "regulator-fixed";
570 regulator-name = "vdd_pnl1";
571 regulator-min-microvolt = <3300000>;
572 regulator-max-microvolt = <3300000>;
576 gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
577 vin-supply = <&sys_3v3_reg>;
580 vdd_vid_reg: regulator@12 {
581 compatible = "regulator-fixed";
583 regulator-name = "vddio_vid";
584 regulator-min-microvolt = <5000000>;
585 regulator-max-microvolt = <5000000>;
587 gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
589 vin-supply = <&vdd_5v0_reg>;
594 compatible = "nvidia,tegra-audio-wm8903-cardhu",
595 "nvidia,tegra-audio-wm8903";
596 nvidia,model = "NVIDIA Tegra Cardhu";
598 nvidia,audio-routing =
599 "Headphone Jack", "HPOUTR",
600 "Headphone Jack", "HPOUTL",
605 "Mic Jack", "MICBIAS",
608 nvidia,i2s-controller = <&tegra_i2s1>;
609 nvidia,audio-codec = <&wm8903>;
611 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
612 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
615 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
616 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
617 <&tegra_car TEGRA30_CLK_EXTERN1>;
618 clock-names = "pll_a", "pll_a_out0", "mclk";
622 compatible = "gpio-keys";
626 interrupt-parent = <&pmic>;
628 linux,code = <KEY_POWER>;
629 debounce-interval = <100>;
634 label = "Volume Down";
635 gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>;
636 linux,code = <KEY_VOLUMEDOWN>;
637 debounce-interval = <10>;
642 gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
643 linux,code = <KEY_VOLUMEUP>;
644 debounce-interval = <10>;