arch/arm/boot/dts/tegra30-apalis.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include "tegra30.dtsi"
   3
   4 /*
   5  * Toradex Apalis T30 Module Device Tree
   6  * Compatible for Revisions 1GB: V1.0A, V1.1A; 1GB IT: V1.1A;
   7  * 2GB: V1.0B, V1.0C, V1.0E, V1.1A
   8  */
   9 / {
  10         model = "Toradex Apalis T30";
  11         compatible = "toradex,apalis_t30", "nvidia,tegra30";
  12
  13         memory@80000000 {
  14                 reg = <0x80000000 0x40000000>;
  15         };
  16
  17         pcie@3000 {
  18                 avdd-pexa-supply = <&vdd2_reg>;
  19                 vdd-pexa-supply = <&vdd2_reg>;
  20                 avdd-pexb-supply = <&vdd2_reg>;
  21                 vdd-pexb-supply = <&vdd2_reg>;
  22                 avdd-pex-pll-supply = <&vdd2_reg>;
  23                 avdd-plle-supply = <&ldo6_reg>;
  24                 vddio-pex-ctl-supply = <&sys_3v3_reg>;
  25                 hvdd-pex-supply = <&sys_3v3_reg>;
  26
  27                 pci@1,0 {
  28                         nvidia,num-lanes = <4>;
  29                 };
  30
  31                 pci@2,0 {
  32                         nvidia,num-lanes = <1>;
  33                 };
  34
  35                 pci@3,0 {
  36                         nvidia,num-lanes = <1>;
  37                 };
  38         };
  39
  40         host1x@50000000 {
  41                 hdmi@54280000 {
  42                         vdd-supply = <&avdd_hdmi_3v3_reg>;
  43                         pll-supply = <&avdd_hdmi_pll_1v8_reg>;
  44
  45                         nvidia,hpd-gpio =
  46                                 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  47                         nvidia,ddc-i2c-bus = <&hdmiddc>;
  48                 };
  49         };
  50
  51         pinmux@70000868 {
  52                 pinctrl-names = "default";
  53                 pinctrl-0 = <&state_default>;
  54
  55                 state_default: pinmux {
  56                         /* Analogue Audio (On-module) */
  57                         clk1_out_pw4 {
  58                                 nvidia,pins = "clk1_out_pw4";
  59                                 nvidia,function = "extperiph1";
  60                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  61                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  62                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  63                         };
  64                         dap3_fs_pp0 {
  65                                 nvidia,pins =   "dap3_fs_pp0",
  66                                                 "dap3_sclk_pp3",
  67                                                 "dap3_din_pp1",
  68                                                 "dap3_dout_pp2";
  69                                 nvidia,function = "i2s2";
  70                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  71                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  72                         };
  73
  74                         /* Apalis BKL1_ON */
  75                         pv2 {
  76                                 nvidia,pins = "pv2";
  77                                 nvidia,function = "rsvd4";
  78                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  79                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  80                         };
  81
  82                         /* Apalis BKL1_PWM */
  83                         uart3_rts_n_pc0 {
  84                                 nvidia,pins = "uart3_rts_n_pc0";
  85                                 nvidia,function = "pwm0";
  86                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  87                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  88                         };
  89                         /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */
  90                         uart3_cts_n_pa1 {
  91                                 nvidia,pins = "uart3_cts_n_pa1";
  92                                 nvidia,function = "rsvd2";
  93                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
  94                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  95                         };
  96
  97                         /* Apalis CAN1 on SPI6 */
  98                         spi2_cs0_n_px3 {
  99                                 nvidia,pins = "spi2_cs0_n_px3",
 100                                               "spi2_miso_px1",
 101                                               "spi2_mosi_px0",
 102                                               "spi2_sck_px2";
 103                                 nvidia,function = "spi6";
 104                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 105                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 106                         };
 107                         /* CAN_INT1 */
 108                         spi2_cs1_n_pw2 {
 109                                 nvidia,pins = "spi2_cs1_n_pw2";
 110                                 nvidia,function = "spi3";
 111                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 112                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 113                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 114                         };
 115
 116                         /* Apalis CAN2 on SPI4 */
 117                         gmi_a16_pj7 {
 118                                 nvidia,pins = "gmi_a16_pj7",
 119                                               "gmi_a17_pb0",
 120                                               "gmi_a18_pb1",
 121                                               "gmi_a19_pk7";
 122                                 nvidia,function = "spi4";
 123                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 124                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 125                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 126                         };
 127                         /* CAN_INT2 */
 128                         spi2_cs2_n_pw3 {
 129                                 nvidia,pins = "spi2_cs2_n_pw3";
 130                                 nvidia,function = "spi3";
 131                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 132                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 133                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 134                         };
 135
 136                         /* Apalis Digital Audio */
 137                         clk1_req_pee2 {
 138                                 nvidia,pins = "clk1_req_pee2";
 139                                 nvidia,function = "hda";
 140                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 141                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 142                         };
 143                         clk2_out_pw5 {
 144                                 nvidia,pins = "clk2_out_pw5";
 145                                 nvidia,function = "extperiph2";
 146                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 147                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 148                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 149                         };
 150                         dap1_fs_pn0 {
 151                                 nvidia,pins = "dap1_fs_pn0",
 152                                               "dap1_din_pn1",
 153                                               "dap1_dout_pn2",
 154                                               "dap1_sclk_pn3";
 155                                 nvidia,function = "hda";
 156                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 157                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 158                         };
 159
 160                         /* Apalis I2C3 */
 161                         cam_i2c_scl_pbb1 {
 162                                 nvidia,pins = "cam_i2c_scl_pbb1",
 163                                               "cam_i2c_sda_pbb2";
 164                                 nvidia,function = "i2c3";
 165                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 166                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 167                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 168                                 nvidia,lock = <TEGRA_PIN_DISABLE>;
 169                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 170                         };
 171
 172                         /* Apalis MMC1 */
 173                         sdmmc3_clk_pa6 {
 174                                 nvidia,pins = "sdmmc3_clk_pa6";
 175                                 nvidia,function = "sdmmc3";
 176                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 177                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 178                         };
 179                         sdmmc3_dat0_pb7 {
 180                                 nvidia,pins = "sdmmc3_cmd_pa7",
 181                                               "sdmmc3_dat0_pb7",
 182                                               "sdmmc3_dat1_pb6",
 183                                               "sdmmc3_dat2_pb5",
 184                                               "sdmmc3_dat3_pb4",
 185                                               "sdmmc3_dat4_pd1",
 186                                               "sdmmc3_dat5_pd0",
 187                                               "sdmmc3_dat6_pd3",
 188                                               "sdmmc3_dat7_pd4";
 189                                 nvidia,function = "sdmmc3";
 190                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 191                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 192                         };
 193                         /* Apalis MMC1_CD# */
 194                         pv3 {
 195                                 nvidia,pins = "pv3";
 196                                 nvidia,function = "rsvd2";
 197                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 198                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 199                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 200                         };
 201
 202                         /* Apalis PWM1 */
 203                         pu6 {
 204                                 nvidia,pins = "pu6";
 205                                 nvidia,function = "pwm3";
 206                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 207                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 208                         };
 209
 210                         /* Apalis PWM2 */
 211                         pu5 {
 212                                 nvidia,pins = "pu5";
 213                                 nvidia,function = "pwm2";
 214                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 215                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 216                         };
 217
 218                         /* Apalis PWM3 */
 219                         pu4 {
 220                                 nvidia,pins = "pu4";
 221                                 nvidia,function = "pwm1";
 222                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 223                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 224                         };
 225
 226                         /* Apalis PWM4 */
 227                         pu3 {
 228                                 nvidia,pins = "pu3";
 229                                 nvidia,function = "pwm0";
 230                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 231                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 232                         };
 233
 234                         /* Apalis RESET_MOCI# */
 235                         gmi_rst_n_pi4 {
 236                                 nvidia,pins = "gmi_rst_n_pi4";
 237                                 nvidia,function = "gmi";
 238                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 239                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 240                         };
 241
 242                         /* Apalis SD1 */
 243                         sdmmc1_clk_pz0 {
 244                                 nvidia,pins = "sdmmc1_clk_pz0";
 245                                 nvidia,function = "sdmmc1";
 246                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 247                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 248                         };
 249                         sdmmc1_cmd_pz1 {
 250                                 nvidia,pins = "sdmmc1_cmd_pz1",
 251                                               "sdmmc1_dat0_py7",
 252                                               "sdmmc1_dat1_py6",
 253                                               "sdmmc1_dat2_py5",
 254                                               "sdmmc1_dat3_py4";
 255                                 nvidia,function = "sdmmc1";
 256                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 257                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 258                         };
 259                         /* Apalis SD1_CD# */
 260                         clk2_req_pcc5 {
 261                                 nvidia,pins = "clk2_req_pcc5";
 262                                 nvidia,function = "rsvd2";
 263                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 264                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 265                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 266                         };
 267
 268                         /* Apalis SPI1 */
 269                         spi1_sck_px5 {
 270                                 nvidia,pins = "spi1_sck_px5",
 271                                               "spi1_mosi_px4",
 272                                               "spi1_miso_px7",
 273                                               "spi1_cs0_n_px6";
 274                                 nvidia,function = "spi1";
 275                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 276                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 277                         };
 278
 279                         /* Apalis SPI2 */
 280                         lcd_sck_pz4 {
 281                                 nvidia,pins = "lcd_sck_pz4",
 282                                               "lcd_sdout_pn5",
 283                                               "lcd_sdin_pz2",
 284                                               "lcd_cs0_n_pn4";
 285                                 nvidia,function = "spi5";
 286                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 287                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 288                         };
 289
 290                         /* Apalis UART1 */
 291                         ulpi_data0 {
 292                                 nvidia,pins = "ulpi_data0_po1",
 293                                               "ulpi_data1_po2",
 294                                               "ulpi_data2_po3",
 295                                               "ulpi_data3_po4",
 296                                               "ulpi_data4_po5",
 297                                               "ulpi_data5_po6",
 298                                               "ulpi_data6_po7",
 299                                               "ulpi_data7_po0";
 300                                 nvidia,function = "uarta";
 301                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 302                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 303                         };
 304
 305                         /* Apalis UART2 */
 306                         ulpi_clk_py0 {
 307                                 nvidia,pins = "ulpi_clk_py0",
 308                                               "ulpi_dir_py1",
 309                                               "ulpi_nxt_py2",
 310                                               "ulpi_stp_py3";
 311                                 nvidia,function = "uartd";
 312                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 313                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 314                         };
 315
 316                         /* Apalis UART3 */
 317                         uart2_rxd_pc3 {
 318                                 nvidia,pins = "uart2_rxd_pc3",
 319                                               "uart2_txd_pc2";
 320                                 nvidia,function = "uartb";
 321                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 322                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 323                         };
 324
 325                         /* Apalis UART4 */
 326                         uart3_rxd_pw7 {
 327                                 nvidia,pins = "uart3_rxd_pw7",
 328                                               "uart3_txd_pw6";
 329                                 nvidia,function = "uartc";
 330                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 331                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 332                         };
 333
 334                         /* Apalis USBO1_EN */
 335                         gen2_i2c_scl_pt5 {
 336                                 nvidia,pins = "gen2_i2c_scl_pt5";
 337                                 nvidia,function = "rsvd4";
 338                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 339                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 340                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 341                         };
 342
 343                         /* Apalis USBO1_OC# */
 344                         gen2_i2c_sda_pt6 {
 345                                 nvidia,pins = "gen2_i2c_sda_pt6";
 346                                 nvidia,function = "rsvd4";
 347                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 348                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 349                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 350                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 351                         };
 352
 353                         /* Apalis WAKE1_MICO */
 354                         pv1 {
 355                                 nvidia,pins = "pv1";
 356                                 nvidia,function = "rsvd1";
 357                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 358                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 359                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 360                         };
 361
 362                         /* eMMC (On-module) */
 363                         sdmmc4_clk_pcc4 {
 364                                 nvidia,pins = "sdmmc4_clk_pcc4",
 365                                               "sdmmc4_rst_n_pcc3";
 366                                 nvidia,function = "sdmmc4";
 367                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 368                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 369                         };
 370                         sdmmc4_dat0_paa0 {
 371                                 nvidia,pins = "sdmmc4_dat0_paa0",
 372                                               "sdmmc4_dat1_paa1",
 373                                               "sdmmc4_dat2_paa2",
 374                                               "sdmmc4_dat3_paa3",
 375                                               "sdmmc4_dat4_paa4",
 376                                               "sdmmc4_dat5_paa5",
 377                                               "sdmmc4_dat6_paa6",
 378                                               "sdmmc4_dat7_paa7";
 379                                 nvidia,function = "sdmmc4";
 380                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 381                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 382                         };
 383
 384                         /* LVDS Transceiver Configuration */
 385                         pbb0 {
 386                                 nvidia,pins = "pbb0",
 387                                               "pbb7",
 388                                               "pcc1",
 389                                               "pcc2";
 390                                 nvidia,function = "rsvd2";
 391                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 392                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 393                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 394                                 nvidia,lock = <TEGRA_PIN_DISABLE>;
 395                         };
 396                         pbb3 {
 397                                 nvidia,pins = "pbb3",
 398                                               "pbb4",
 399                                               "pbb5",
 400                                               "pbb6";
 401                                 nvidia,function = "displayb";
 402                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 403                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 404                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 405                                 nvidia,lock = <TEGRA_PIN_DISABLE>;
 406                         };
 407
 408                         /* Power I2C (On-module) */
 409                         pwr_i2c_scl_pz6 {
 410                                 nvidia,pins = "pwr_i2c_scl_pz6",
 411                                               "pwr_i2c_sda_pz7";
 412                                 nvidia,function = "i2cpwr";
 413                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 414                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 415                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 416                                 nvidia,lock = <TEGRA_PIN_DISABLE>;
 417                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 418                         };
 419
 420                         /*
 421                          * THERMD_ALERT#, unlatched I2C address pin of LM95245
 422                          * temperature sensor therefore requires disabling for
 423                          * now
 424                          */
 425                         lcd_dc1_pd2 {
 426                                 nvidia,pins = "lcd_dc1_pd2";
 427                                 nvidia,function = "rsvd3";
 428                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 429                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 430                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 431                         };
 432
 433                         /* TOUCH_PEN_INT# */
 434                         pv0 {
 435                                 nvidia,pins = "pv0";
 436                                 nvidia,function = "rsvd1";
 437                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 438                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 439                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 440                         };
 441                 };
 442         };
 443
 444         hdmiddc: i2c@7000c700 {
 445                 clock-frequency = <10000>;
 446         };
 447
 448         /*
 449          * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
 450          * touch screen controller
 451          */
 452         i2c@7000d000 {
 453                 status = "okay";
 454                 clock-frequency = <100000>;
 455
 456                 /* SGTL5000 audio codec */
 457                 sgtl5000: codec@a {
 458                         compatible = "fsl,sgtl5000";
 459                         reg = <0x0a>;
 460                         VDDA-supply = <&sys_3v3_reg>;
 461                         VDDIO-supply = <&sys_3v3_reg>;
 462                         clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
 463                 };
 464
 465                 pmic: tps65911@2d {
 466                         compatible = "ti,tps65911";
 467                         reg = <0x2d>;
 468
 469                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 470                         #interrupt-cells = <2>;
 471                         interrupt-controller;
 472
 473                         ti,system-power-controller;
 474
 475                         #gpio-cells = <2>;
 476                         gpio-controller;
 477
 478                         vcc1-supply = <&sys_3v3_reg>;
 479                         vcc2-supply = <&sys_3v3_reg>;
 480                         vcc3-supply = <&vio_reg>;
 481                         vcc4-supply = <&sys_3v3_reg>;
 482                         vcc5-supply = <&sys_3v3_reg>;
 483                         vcc6-supply = <&vio_reg>;
 484                         vcc7-supply = <&charge_pump_5v0_reg>;
 485                         vccio-supply = <&sys_3v3_reg>;
 486
 487                         regulators {
 488                                 /* SW1: +V1.35_VDDIO_DDR */
 489                                 vdd1_reg: vdd1 {
 490                                         regulator-name = "vddio_ddr_1v35";
 491                                         regulator-min-microvolt = <1350000>;
 492                                         regulator-max-microvolt = <1350000>;
 493                                         regulator-always-on;
 494                                 };
 495
 496                                 /* SW2: +V1.05 */
 497                                 vdd2_reg: vdd2 {
 498                                         regulator-name =
 499                                                 "vdd_pexa,vdd_pexb,vdd_sata";
 500                                         regulator-min-microvolt = <1050000>;
 501                                         regulator-max-microvolt = <1050000>;
 502                                 };
 503
 504                                 /* SW CTRL: +V1.0_VDD_CPU */
 505                                 vddctrl_reg: vddctrl {
 506                                         regulator-name = "vdd_cpu,vdd_sys";
 507                                         regulator-min-microvolt = <1150000>;
 508                                         regulator-max-microvolt = <1150000>;
 509                                         regulator-always-on;
 510                                 };
 511
 512                                 /* SWIO: +V1.8 */
 513                                 vio_reg: vio {
 514                                         regulator-name = "vdd_1v8_gen";
 515                                         regulator-min-microvolt = <1800000>;
 516                                         regulator-max-microvolt = <1800000>;
 517                                         regulator-always-on;
 518                                 };
 519
 520                                 /* LDO1: unused */
 521
 522                                 /*
 523                                  * EN_+V3.3 switching via FET:
 524                                  * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
 525                                  * see also v3_3 fixed supply
 526                                  */
 527                                 ldo2_reg: ldo2 {
 528                                         regulator-name = "en_3v3";
 529                                         regulator-min-microvolt = <3300000>;
 530                                         regulator-max-microvolt = <3300000>;
 531                                         regulator-always-on;
 532                                 };
 533
 534                                 /* +V1.2_CSI */
 535                                 ldo3_reg: ldo3 {
 536                                         regulator-name =
 537                                                 "avdd_dsi_csi,pwrdet_mipi";
 538                                         regulator-min-microvolt = <1200000>;
 539                                         regulator-max-microvolt = <1200000>;
 540                                 };
 541
 542                                 /* +V1.2_VDD_RTC */
 543                                 ldo4_reg: ldo4 {
 544                                         regulator-name = "vdd_rtc";
 545                                         regulator-min-microvolt = <1200000>;
 546                                         regulator-max-microvolt = <1200000>;
 547                                         regulator-always-on;
 548                                 };
 549
 550                                 /*
 551                                  * +V2.8_AVDD_VDAC:
 552                                  * only required for analog RGB
 553                                  */
 554                                 ldo5_reg: ldo5 {
 555                                         regulator-name = "avdd_vdac";
 556                                         regulator-min-microvolt = <2800000>;
 557                                         regulator-max-microvolt = <2800000>;
 558                                         regulator-always-on;
 559                                 };
 560
 561                                 /*
 562                                  * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
 563                                  * but LDO6 can't set voltage in 50mV
 564                                  * granularity
 565                                  */
 566                                 ldo6_reg: ldo6 {
 567                                         regulator-name = "avdd_plle";
 568                                         regulator-min-microvolt = <1100000>;
 569                                         regulator-max-microvolt = <1100000>;
 570                                 };
 571
 572                                 /* +V1.2_AVDD_PLL */
 573                                 ldo7_reg: ldo7 {
 574                                         regulator-name = "avdd_pll";
 575                                         regulator-min-microvolt = <1200000>;
 576                                         regulator-max-microvolt = <1200000>;
 577                                         regulator-always-on;
 578                                 };
 579
 580                                 /* +V1.0_VDD_DDR_HS */
 581                                 ldo8_reg: ldo8 {
 582                                         regulator-name = "vdd_ddr_hs";
 583                                         regulator-min-microvolt = <1000000>;
 584                                         regulator-max-microvolt = <1000000>;
 585                                         regulator-always-on;
 586                                 };
 587                         };
 588                 };
 589
 590                 /* STMPE811 touch screen controller */
 591                 stmpe811@41 {
 592                         compatible = "st,stmpe811";
 593                         reg = <0x41>;
 594                         interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
 595                         interrupt-parent = <&gpio>;
 596                         interrupt-controller;
 597                         id = <0>;
 598                         blocks = <0x5>;
 599                         irq-trigger = <0x1>;
 600
 601                         stmpe_touchscreen {
 602                                 compatible = "st,stmpe-ts";
 603                                 /* 3.25 MHz ADC clock speed */
 604                                 st,adc-freq = <1>;
 605                                 /* 8 sample average control */
 606                                 st,ave-ctrl = <3>;
 607                                 /* 7 length fractional part in z */
 608                                 st,fraction-z = <7>;
 609                                 /*
 610                                  * 50 mA typical 80 mA max touchscreen drivers
 611                                  * current limit value
 612                                  */
 613                                 st,i-drive = <1>;
 614                                 /* 12-bit ADC */
 615                                 st,mod-12b = <1>;
 616                                 /* internal ADC reference */
 617                                 st,ref-sel = <0>;
 618                                 /* ADC converstion time: 80 clocks */
 619                                 st,sample-time = <4>;
 620                                 /* 1 ms panel driver settling time */
 621                                 st,settling = <3>;
 622                                 /* 5 ms touch detect interrupt delay */
 623                                 st,touch-det-delay = <5>;
 624                         };
 625                 };
 626
 627                 /*
 628                  * LM95245 temperature sensor
 629                  * Note: OVERT_N directly connected to PMIC PWRDN
 630                  */
 631                 temp-sensor@4c {
 632                         compatible = "national,lm95245";
 633                         reg = <0x4c>;
 634                 };
 635
 636                 /* SW: +V1.2_VDD_CORE */
 637                 tps62362@60 {
 638                         compatible = "ti,tps62362";
 639                         reg = <0x60>;
 640
 641                         regulator-name = "tps62362-vout";
 642                         regulator-min-microvolt = <900000>;
 643                         regulator-max-microvolt = <1400000>;
 644                         regulator-boot-on;
 645                         regulator-always-on;
 646                         ti,vsel0-state-low;
 647                         /* VSEL1: EN_CORE_DVFS_N low for DVFS */
 648                         ti,vsel1-state-low;
 649                 };
 650         };
 651
 652         /* SPI4: CAN2 */
 653         spi@7000da00 {
 654                 status = "okay";
 655                 spi-max-frequency = <10000000>;
 656
 657                 can@1 {
 658                         compatible = "microchip,mcp2515";
 659                         reg = <1>;
 660                         clocks = <&clk16m>;
 661                         interrupt-parent = <&gpio>;
 662                         interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>;
 663                         spi-max-frequency = <10000000>;
 664                 };
 665         };
 666
 667         /* SPI6: CAN1 */
 668         spi@7000de00 {
 669                 status = "okay";
 670                 spi-max-frequency = <10000000>;
 671
 672                 can@0 {
 673                         compatible = "microchip,mcp2515";
 674                         reg = <0>;
 675                         clocks = <&clk16m>;
 676                         interrupt-parent = <&gpio>;
 677                         interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_FALLING>;
 678                         spi-max-frequency = <10000000>;
 679                 };
 680         };
 681
 682         pmc@7000e400 {
 683                 nvidia,invert-interrupt;
 684                 nvidia,suspend-mode = <1>;
 685                 nvidia,cpu-pwr-good-time = <5000>;
 686                 nvidia,cpu-pwr-off-time = <5000>;
 687                 nvidia,core-pwr-good-time = <3845 3845>;
 688                 nvidia,core-pwr-off-time = <0>;
 689                 nvidia,core-power-req-active-high;
 690                 nvidia,sys-clock-req-active-high;
 691         };
 692
 693         ahub@70080000 {
 694                 i2s@70080500 {
 695                         status = "okay";
 696                 };
 697         };
 698
 699         /* eMMC */
 700         sdhci@78000600 {
 701                 status = "okay";
 702                 bus-width = <8>;
 703                 non-removable;
 704         };
 705
 706         clocks {
 707                 compatible = "simple-bus";
 708                 #address-cells = <1>;
 709                 #size-cells = <0>;
 710
 711                 clk32k_in: clk@0 {
 712                         compatible = "fixed-clock";
 713                         reg = <0>;
 714                         #clock-cells = <0>;
 715                         clock-frequency = <32768>;
 716                 };
 717
 718                 clk16m: clk@1 {
 719                         compatible = "fixed-clock";
 720                         reg = <1>;
 721                         #clock-cells = <0>;
 722                         clock-frequency = <16000000>;
 723                         clock-output-names = "clk16m";
 724                 };
 725         };
 726
 727         regulators {
 728                 compatible = "simple-bus";
 729                 #address-cells = <1>;
 730                 #size-cells = <0>;
 731
 732                 avdd_hdmi_pll_1v8_reg: regulator@100 {
 733                         compatible = "regulator-fixed";
 734                         reg = <100>;
 735                         regulator-name = "+V1.8_AVDD_HDMI_PLL";
 736                         regulator-min-microvolt = <1800000>;
 737                         regulator-max-microvolt = <1800000>;
 738                         enable-active-high;
 739                         gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
 740                         vin-supply = <&vio_reg>;
 741                 };
 742
 743                 sys_3v3_reg: regulator@101 {
 744                         compatible = "regulator-fixed";
 745                         reg = <101>;
 746                         regulator-name = "3v3";
 747                         regulator-min-microvolt = <3300000>;
 748                         regulator-max-microvolt = <3300000>;
 749                         regulator-always-on;
 750                 };
 751
 752                 avdd_hdmi_3v3_reg: regulator@102 {
 753                         compatible = "regulator-fixed";
 754                         reg = <102>;
 755                         regulator-name = "+V3.3_AVDD_HDMI";
 756                         regulator-min-microvolt = <3300000>;
 757                         regulator-max-microvolt = <3300000>;
 758                         enable-active-high;
 759                         gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
 760                         vin-supply = <&sys_3v3_reg>;
 761                 };
 762
 763                 charge_pump_5v0_reg: regulator@103 {
 764                         compatible = "regulator-fixed";
 765                         reg = <103>;
 766                         regulator-name = "5v0";
 767                         regulator-min-microvolt = <5000000>;
 768                         regulator-max-microvolt = <5000000>;
 769                         regulator-always-on;
 770                 };
 771         };
 772
 773         sound {
 774                 compatible = "toradex,tegra-audio-sgtl5000-apalis_t30",
 775                              "nvidia,tegra-audio-sgtl5000";
 776                 nvidia,model = "Toradex Apalis T30";
 777                 nvidia,audio-routing =
 778                         "Headphone Jack", "HP_OUT",
 779                         "LINE_IN", "Line In Jack",
 780                         "MIC_IN", "Mic Jack";
 781                 nvidia,i2s-controller = <&tegra_i2s2>;
 782                 nvidia,audio-codec = <&sgtl5000>;
 783                 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
 784                          <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
 785                          <&tegra_car TEGRA30_CLK_EXTERN1>;
 786                 clock-names = "pll_a", "pll_a_out0", "mclk";
 787         };
 788 };