arch/arm/boot/dts/tegra20.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra20-car.h>
   3 #include <dt-bindings/gpio/tegra-gpio.h>
   4 #include <dt-bindings/memory/tegra20-mc.h>
   5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/soc/tegra-pmc.h>
   8
   9 #include "tegra20-peripherals-opp.dtsi"
  10
  11 / {
  12         compatible = "nvidia,tegra20";
  13         interrupt-parent = <&lic>;
  14         #address-cells = <1>;
  15         #size-cells = <1>;
  16
  17         memory@0 {
  18                 device_type = "memory";
  19                 reg = <0 0>;
  20         };
  21
  22         sram@40000000 {
  23                 compatible = "mmio-sram";
  24                 reg = <0x40000000 0x40000>;
  25                 #address-cells = <1>;
  26                 #size-cells = <1>;
  27                 ranges = <0 0x40000000 0x40000>;
  28
  29                 vde_pool: sram@400 {
  30                         reg = <0x400 0x3fc00>;
  31                         pool;
  32                 };
  33         };
  34
  35         host1x@50000000 {
  36                 compatible = "nvidia,tegra20-host1x";
  37                 reg = <0x50000000 0x00024000>;
  38                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  39                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  40                 interrupt-names = "syncpt", "host1x";
  41                 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
  42                 clock-names = "host1x";
  43                 resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>;
  44                 reset-names = "host1x", "mc";
  45                 power-domains = <&pd_core>;
  46                 operating-points-v2 = <&host1x_dvfs_opp_table>;
  47
  48                 #address-cells = <1>;
  49                 #size-cells = <1>;
  50
  51                 ranges = <0x54000000 0x54000000 0x04000000>;
  52
  53                 mpe@54040000 {
  54                         compatible = "nvidia,tegra20-mpe";
  55                         reg = <0x54040000 0x00040000>;
  56                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
  57                         clocks = <&tegra_car TEGRA20_CLK_MPE>;
  58                         resets = <&tegra_car 60>;
  59                         reset-names = "mpe";
  60                         power-domains = <&pd_mpe>;
  61                         operating-points-v2 = <&mpe_dvfs_opp_table>;
  62                         status = "disabled";
  63                 };
  64
  65                 vi@54080000 {
  66                         compatible = "nvidia,tegra20-vi";
  67                         reg = <0x54080000 0x00040000>;
  68                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
  69                         clocks = <&tegra_car TEGRA20_CLK_VI>;
  70                         resets = <&tegra_car 20>;
  71                         reset-names = "vi";
  72                         power-domains = <&pd_venc>;
  73                         operating-points-v2 = <&vi_dvfs_opp_table>;
  74                         status = "disabled";
  75                 };
  76
  77                 epp@540c0000 {
  78                         compatible = "nvidia,tegra20-epp";
  79                         reg = <0x540c0000 0x00040000>;
  80                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
  81                         clocks = <&tegra_car TEGRA20_CLK_EPP>;
  82                         resets = <&tegra_car 19>;
  83                         reset-names = "epp";
  84                         power-domains = <&pd_core>;
  85                         operating-points-v2 = <&epp_dvfs_opp_table>;
  86                         status = "disabled";
  87                 };
  88
  89                 isp@54100000 {
  90                         compatible = "nvidia,tegra20-isp";
  91                         reg = <0x54100000 0x00040000>;
  92                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  93                         clocks = <&tegra_car TEGRA20_CLK_ISP>;
  94                         resets = <&tegra_car 23>;
  95                         reset-names = "isp";
  96                         power-domains = <&pd_venc>;
  97                         status = "disabled";
  98                 };
  99
 100                 gr2d@54140000 {
 101                         compatible = "nvidia,tegra20-gr2d";
 102                         reg = <0x54140000 0x00040000>;
 103                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 104                         clocks = <&tegra_car TEGRA20_CLK_GR2D>;
 105                         resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>;
 106                         reset-names = "2d", "mc";
 107                         power-domains = <&pd_core>;
 108                         operating-points-v2 = <&gr2d_dvfs_opp_table>;
 109                 };
 110
 111                 gr3d@54180000 {
 112                         compatible = "nvidia,tegra20-gr3d";
 113                         reg = <0x54180000 0x00040000>;
 114                         clocks = <&tegra_car TEGRA20_CLK_GR3D>;
 115                         resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>;
 116                         reset-names = "3d", "mc";
 117                         power-domains = <&pd_3d>;
 118                         operating-points-v2 = <&gr3d_dvfs_opp_table>;
 119                 };
 120
 121                 dc@54200000 {
 122                         compatible = "nvidia,tegra20-dc";
 123                         reg = <0x54200000 0x00040000>;
 124                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 125                         clocks = <&tegra_car TEGRA20_CLK_DISP1>,
 126                                  <&tegra_car TEGRA20_CLK_PLL_P>;
 127                         clock-names = "dc", "parent";
 128                         resets = <&tegra_car 27>;
 129                         reset-names = "dc";
 130                         power-domains = <&pd_core>;
 131                         operating-points-v2 = <&disp1_dvfs_opp_table>;
 132
 133                         nvidia,head = <0>;
 134
 135                         interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>,
 136                                         <&mc TEGRA20_MC_DISPLAY0B &emc>,
 137                                         <&mc TEGRA20_MC_DISPLAY1B &emc>,
 138                                         <&mc TEGRA20_MC_DISPLAY0C &emc>,
 139                                         <&mc TEGRA20_MC_DISPLAYHC &emc>;
 140                         interconnect-names = "wina",
 141                                              "winb",
 142                                              "winb-vfilter",
 143                                              "winc",
 144                                              "cursor";
 145
 146                         rgb {
 147                                 status = "disabled";
 148                         };
 149                 };
 150
 151                 dc@54240000 {
 152                         compatible = "nvidia,tegra20-dc";
 153                         reg = <0x54240000 0x00040000>;
 154                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 155                         clocks = <&tegra_car TEGRA20_CLK_DISP2>,
 156                                  <&tegra_car TEGRA20_CLK_PLL_P>;
 157                         clock-names = "dc", "parent";
 158                         resets = <&tegra_car 26>;
 159                         reset-names = "dc";
 160                         power-domains = <&pd_core>;
 161                         operating-points-v2 = <&disp2_dvfs_opp_table>;
 162
 163                         nvidia,head = <1>;
 164
 165                         interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>,
 166                                         <&mc TEGRA20_MC_DISPLAY0BB &emc>,
 167                                         <&mc TEGRA20_MC_DISPLAY1BB &emc>,
 168                                         <&mc TEGRA20_MC_DISPLAY0CB &emc>,
 169                                         <&mc TEGRA20_MC_DISPLAYHCB &emc>;
 170                         interconnect-names = "wina",
 171                                              "winb",
 172                                              "winb-vfilter",
 173                                              "winc",
 174                                              "cursor";
 175
 176                         rgb {
 177                                 status = "disabled";
 178                         };
 179                 };
 180
 181                 tegra_hdmi: hdmi@54280000 {
 182                         compatible = "nvidia,tegra20-hdmi";
 183                         reg = <0x54280000 0x00040000>;
 184                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 185                         clocks = <&tegra_car TEGRA20_CLK_HDMI>,
 186                                  <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
 187                         clock-names = "hdmi", "parent";
 188                         resets = <&tegra_car 51>;
 189                         reset-names = "hdmi";
 190                         power-domains = <&pd_core>;
 191                         operating-points-v2 = <&hdmi_dvfs_opp_table>;
 192                         #sound-dai-cells = <0>;
 193                         status = "disabled";
 194                 };
 195
 196                 tvo@542c0000 {
 197                         compatible = "nvidia,tegra20-tvo";
 198                         reg = <0x542c0000 0x00040000>;
 199                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 200                         clocks = <&tegra_car TEGRA20_CLK_TVO>;
 201                         power-domains = <&pd_core>;
 202                         operating-points-v2 = <&tvo_dvfs_opp_table>;
 203                         status = "disabled";
 204                 };
 205
 206                 dsi@54300000 {
 207                         compatible = "nvidia,tegra20-dsi";
 208                         reg = <0x54300000 0x00040000>;
 209                         clocks = <&tegra_car TEGRA20_CLK_DSI>,
 210                                  <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
 211                         clock-names = "dsi", "parent";
 212                         resets = <&tegra_car 48>;
 213                         reset-names = "dsi";
 214                         power-domains = <&pd_core>;
 215                         operating-points-v2 = <&dsi_dvfs_opp_table>;
 216                         status = "disabled";
 217                 };
 218         };
 219
 220         timer@50040600 {
 221                 compatible = "arm,cortex-a9-twd-timer";
 222                 interrupt-parent = <&intc>;
 223                 reg = <0x50040600 0x20>;
 224                 interrupts = <GIC_PPI 13
 225                         (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
 226                 clocks = <&tegra_car TEGRA20_CLK_TWD>;
 227         };
 228
 229         intc: interrupt-controller@50041000 {
 230                 compatible = "arm,cortex-a9-gic";
 231                 reg = <0x50041000 0x1000>,
 232                       <0x50040100 0x0100>;
 233                 interrupt-controller;
 234                 #interrupt-cells = <3>;
 235                 interrupt-parent = <&intc>;
 236         };
 237
 238         cache-controller@50043000 {
 239                 compatible = "arm,pl310-cache";
 240                 reg = <0x50043000 0x1000>;
 241                 arm,data-latency = <5 5 2>;
 242                 arm,tag-latency = <4 4 2>;
 243                 cache-unified;
 244                 cache-level = <2>;
 245         };
 246
 247         lic: interrupt-controller@60004000 {
 248                 compatible = "nvidia,tegra20-ictlr";
 249                 reg = <0x60004000 0x100>,
 250                       <0x60004100 0x50>,
 251                       <0x60004200 0x50>,
 252                       <0x60004300 0x50>;
 253                 interrupt-controller;
 254                 #interrupt-cells = <3>;
 255                 interrupt-parent = <&intc>;
 256         };
 257
 258         timer@60005000 {
 259                 compatible = "nvidia,tegra20-timer";
 260                 reg = <0x60005000 0x60>;
 261                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 262                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 263                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 264                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 265                 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
 266         };
 267
 268         tegra_car: clock@60006000 {
 269                 compatible = "nvidia,tegra20-car";
 270                 reg = <0x60006000 0x1000>;
 271                 #clock-cells = <1>;
 272                 #reset-cells = <1>;
 273
 274                 sclk {
 275                         compatible = "nvidia,tegra20-sclk";
 276                         clocks = <&tegra_car TEGRA20_CLK_SCLK>;
 277                         power-domains = <&pd_core>;
 278                         operating-points-v2 = <&sclk_dvfs_opp_table>;
 279                 };
 280         };
 281
 282         flow-controller@60007000 {
 283                 compatible = "nvidia,tegra20-flowctrl";
 284                 reg = <0x60007000 0x1000>;
 285         };
 286
 287         apbdma: dma@6000a000 {
 288                 compatible = "nvidia,tegra20-apbdma";
 289                 reg = <0x6000a000 0x1200>;
 290                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 291                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 292                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 293                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 294                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 295                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 296                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 297                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 298                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 299                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 300                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 301                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 302                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 303                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 304                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 305                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 306                 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
 307                 resets = <&tegra_car 34>;
 308                 reset-names = "dma";
 309                 #dma-cells = <1>;
 310         };
 311
 312         ahb@6000c000 {
 313                 compatible = "nvidia,tegra20-ahb";
 314                 reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */
 315         };
 316
 317         gpio: gpio@6000d000 {
 318                 compatible = "nvidia,tegra20-gpio";
 319                 reg = <0x6000d000 0x1000>;
 320                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 321                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 322                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 323                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 324                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 325                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 326                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 327                 #gpio-cells = <2>;
 328                 gpio-controller;
 329                 #interrupt-cells = <2>;
 330                 interrupt-controller;
 331                 gpio-ranges = <&pinmux 0 0 224>;
 332         };
 333
 334         vde@6001a000 {
 335                 compatible = "nvidia,tegra20-vde";
 336                 reg = <0x6001a000 0x1000>, /* Syntax Engine */
 337                       <0x6001b000 0x1000>, /* Video Bitstream Engine */
 338                       <0x6001c000  0x100>, /* Macroblock Engine */
 339                       <0x6001c200  0x100>, /* Post-processing Engine */
 340                       <0x6001c400  0x100>, /* Motion Compensation Engine */
 341                       <0x6001c600  0x100>, /* Transform Engine */
 342                       <0x6001c800  0x100>, /* Pixel prediction block */
 343                       <0x6001ca00  0x100>, /* Video DMA */
 344                       <0x6001d800  0x300>; /* Video frame controls */
 345                 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
 346                             "tfe", "ppb", "vdma", "frameid";
 347                 iram = <&vde_pool>; /* IRAM region */
 348                 interrupts = <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
 349                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
 350                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
 351                 interrupt-names = "sync-token", "bsev", "sxe";
 352                 clocks = <&tegra_car TEGRA20_CLK_VDE>;
 353                 reset-names = "vde", "mc";
 354                 resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>;
 355                 power-domains = <&pd_vde>;
 356                 operating-points-v2 = <&vde_dvfs_opp_table>;
 357         };
 358
 359         apbmisc@70000800 {
 360                 compatible = "nvidia,tegra20-apbmisc";
 361                 reg = <0x70000800 0x64>, /* Chip revision */
 362                       <0x70000008 0x04>; /* Strapping options */
 363         };
 364
 365         pinmux: pinmux@70000014 {
 366                 compatible = "nvidia,tegra20-pinmux";
 367                 reg = <0x70000014 0x10>, /* Tri-state registers */
 368                       <0x70000080 0x20>, /* Mux registers */
 369                       <0x700000a0 0x14>, /* Pull-up/down registers */
 370                       <0x70000868 0xa8>; /* Pad control registers */
 371         };
 372
 373         das@70000c00 {
 374                 compatible = "nvidia,tegra20-das";
 375                 reg = <0x70000c00 0x80>;
 376         };
 377
 378         tegra_ac97: ac97@70002000 {
 379                 compatible = "nvidia,tegra20-ac97";
 380                 reg = <0x70002000 0x200>;
 381                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 382                 clocks = <&tegra_car TEGRA20_CLK_AC97>;
 383                 resets = <&tegra_car 3>;
 384                 reset-names = "ac97";
 385                 dmas = <&apbdma 12>, <&apbdma 12>;
 386                 dma-names = "rx", "tx";
 387                 status = "disabled";
 388         };
 389
 390         tegra_spdif: spdif@70002400 {
 391                 compatible = "nvidia,tegra20-spdif";
 392                 reg = <0x70002400 0x200>;
 393                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 394                 clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>,
 395                          <&tegra_car TEGRA20_CLK_SPDIF_IN>;
 396                 clock-names = "out", "in";
 397                 resets = <&tegra_car 10>;
 398                 dmas = <&apbdma 3>, <&apbdma 3>;
 399                 dma-names = "rx", "tx";
 400                 #sound-dai-cells = <0>;
 401                 status = "disabled";
 402
 403                 assigned-clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>;
 404                 assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_A_OUT0>;
 405         };
 406
 407         tegra_i2s1: i2s@70002800 {
 408                 compatible = "nvidia,tegra20-i2s";
 409                 reg = <0x70002800 0x200>;
 410                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 411                 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
 412                 resets = <&tegra_car 11>;
 413                 reset-names = "i2s";
 414                 dmas = <&apbdma 2>, <&apbdma 2>;
 415                 dma-names = "rx", "tx";
 416                 status = "disabled";
 417         };
 418
 419         tegra_i2s2: i2s@70002a00 {
 420                 compatible = "nvidia,tegra20-i2s";
 421                 reg = <0x70002a00 0x200>;
 422                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 423                 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
 424                 resets = <&tegra_car 18>;
 425                 reset-names = "i2s";
 426                 dmas = <&apbdma 1>, <&apbdma 1>;
 427                 dma-names = "rx", "tx";
 428                 status = "disabled";
 429         };
 430
 431         /*
 432          * There are two serial driver i.e. 8250 based simple serial
 433          * driver and APB DMA based serial driver for higher baudrate
 434          * and performace. To enable the 8250 based driver, the compatible
 435          * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
 436          * driver, the compatible is "nvidia,tegra20-hsuart".
 437          */
 438         uarta: serial@70006000 {
 439                 compatible = "nvidia,tegra20-uart";
 440                 reg = <0x70006000 0x40>;
 441                 reg-shift = <2>;
 442                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 443                 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
 444                 resets = <&tegra_car 6>;
 445                 reset-names = "serial";
 446                 dmas = <&apbdma 8>, <&apbdma 8>;
 447                 dma-names = "rx", "tx";
 448                 status = "disabled";
 449         };
 450
 451         uartb: serial@70006040 {
 452                 compatible = "nvidia,tegra20-uart";
 453                 reg = <0x70006040 0x40>;
 454                 reg-shift = <2>;
 455                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 456                 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
 457                 resets = <&tegra_car 7>;
 458                 reset-names = "serial";
 459                 dmas = <&apbdma 9>, <&apbdma 9>;
 460                 dma-names = "rx", "tx";
 461                 status = "disabled";
 462         };
 463
 464         uartc: serial@70006200 {
 465                 compatible = "nvidia,tegra20-uart";
 466                 reg = <0x70006200 0x100>;
 467                 reg-shift = <2>;
 468                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 469                 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
 470                 resets = <&tegra_car 55>;
 471                 reset-names = "serial";
 472                 dmas = <&apbdma 10>, <&apbdma 10>;
 473                 dma-names = "rx", "tx";
 474                 status = "disabled";
 475         };
 476
 477         uartd: serial@70006300 {
 478                 compatible = "nvidia,tegra20-uart";
 479                 reg = <0x70006300 0x100>;
 480                 reg-shift = <2>;
 481                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 482                 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
 483                 resets = <&tegra_car 65>;
 484                 reset-names = "serial";
 485                 dmas = <&apbdma 19>, <&apbdma 19>;
 486                 dma-names = "rx", "tx";
 487                 status = "disabled";
 488         };
 489
 490         uarte: serial@70006400 {
 491                 compatible = "nvidia,tegra20-uart";
 492                 reg = <0x70006400 0x100>;
 493                 reg-shift = <2>;
 494                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 495                 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
 496                 resets = <&tegra_car 66>;
 497                 reset-names = "serial";
 498                 dmas = <&apbdma 20>, <&apbdma 20>;
 499                 dma-names = "rx", "tx";
 500                 status = "disabled";
 501         };
 502
 503         nand-controller@70008000 {
 504                 compatible = "nvidia,tegra20-nand";
 505                 reg = <0x70008000 0x100>;
 506                 #address-cells = <1>;
 507                 #size-cells = <0>;
 508                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 509                 clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
 510                 clock-names = "nand";
 511                 resets = <&tegra_car 13>;
 512                 reset-names = "nand";
 513                 assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
 514                 assigned-clock-rates = <150000000>;
 515                 power-domains = <&pd_core>;
 516                 operating-points-v2 = <&ndflash_dvfs_opp_table>;
 517                 status = "disabled";
 518         };
 519
 520         gmi@70009000 {
 521                 compatible = "nvidia,tegra20-gmi";
 522                 reg = <0x70009000 0x1000>;
 523                 #address-cells = <2>;
 524                 #size-cells = <1>;
 525                 ranges = <0 0 0xd0000000 0xfffffff>;
 526                 clocks = <&tegra_car TEGRA20_CLK_NOR>;
 527                 clock-names = "gmi";
 528                 resets = <&tegra_car 42>;
 529                 reset-names = "gmi";
 530                 power-domains = <&pd_core>;
 531                 operating-points-v2 = <&nor_dvfs_opp_table>;
 532                 status = "disabled";
 533         };
 534
 535         pwm: pwm@7000a000 {
 536                 compatible = "nvidia,tegra20-pwm";
 537                 reg = <0x7000a000 0x100>;
 538                 #pwm-cells = <2>;
 539                 clocks = <&tegra_car TEGRA20_CLK_PWM>;
 540                 resets = <&tegra_car 17>;
 541                 reset-names = "pwm";
 542                 status = "disabled";
 543         };
 544
 545         rtc@7000e000 {
 546                 compatible = "nvidia,tegra20-rtc";
 547                 reg = <0x7000e000 0x100>;
 548                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 549                 clocks = <&tegra_car TEGRA20_CLK_RTC>;
 550         };
 551
 552         i2c@7000c000 {
 553                 compatible = "nvidia,tegra20-i2c";
 554                 reg = <0x7000c000 0x100>;
 555                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 556                 #address-cells = <1>;
 557                 #size-cells = <0>;
 558                 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
 559                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 560                 clock-names = "div-clk", "fast-clk";
 561                 resets = <&tegra_car 12>;
 562                 reset-names = "i2c";
 563                 dmas = <&apbdma 21>, <&apbdma 21>;
 564                 dma-names = "rx", "tx";
 565                 status = "disabled";
 566         };
 567
 568         spi@7000c380 {
 569                 compatible = "nvidia,tegra20-sflash";
 570                 reg = <0x7000c380 0x80>;
 571                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 572                 #address-cells = <1>;
 573                 #size-cells = <0>;
 574                 clocks = <&tegra_car TEGRA20_CLK_SPI>;
 575                 resets = <&tegra_car 43>;
 576                 reset-names = "spi";
 577                 dmas = <&apbdma 11>, <&apbdma 11>;
 578                 dma-names = "rx", "tx";
 579                 status = "disabled";
 580         };
 581
 582         i2c2: i2c@7000c400 {
 583                 compatible = "nvidia,tegra20-i2c";
 584                 reg = <0x7000c400 0x100>;
 585                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 586                 #address-cells = <1>;
 587                 #size-cells = <0>;
 588                 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
 589                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 590                 clock-names = "div-clk", "fast-clk";
 591                 resets = <&tegra_car 54>;
 592                 reset-names = "i2c";
 593                 dmas = <&apbdma 22>, <&apbdma 22>;
 594                 dma-names = "rx", "tx";
 595                 status = "disabled";
 596         };
 597
 598         i2c@7000c500 {
 599                 compatible = "nvidia,tegra20-i2c";
 600                 reg = <0x7000c500 0x100>;
 601                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 602                 #address-cells = <1>;
 603                 #size-cells = <0>;
 604                 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
 605                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 606                 clock-names = "div-clk", "fast-clk";
 607                 resets = <&tegra_car 67>;
 608                 reset-names = "i2c";
 609                 dmas = <&apbdma 23>, <&apbdma 23>;
 610                 dma-names = "rx", "tx";
 611                 status = "disabled";
 612         };
 613
 614         i2c@7000d000 {
 615                 compatible = "nvidia,tegra20-i2c-dvc";
 616                 reg = <0x7000d000 0x200>;
 617                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 618                 #address-cells = <1>;
 619                 #size-cells = <0>;
 620                 clocks = <&tegra_car TEGRA20_CLK_DVC>,
 621                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 622                 clock-names = "div-clk", "fast-clk";
 623                 resets = <&tegra_car 47>;
 624                 reset-names = "i2c";
 625                 dmas = <&apbdma 24>, <&apbdma 24>;
 626                 dma-names = "rx", "tx";
 627                 status = "disabled";
 628         };
 629
 630         spi@7000d400 {
 631                 compatible = "nvidia,tegra20-slink";
 632                 reg = <0x7000d400 0x200>;
 633                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 634                 #address-cells = <1>;
 635                 #size-cells = <0>;
 636                 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
 637                 resets = <&tegra_car 41>;
 638                 reset-names = "spi";
 639                 dmas = <&apbdma 15>, <&apbdma 15>;
 640                 dma-names = "rx", "tx";
 641                 status = "disabled";
 642         };
 643
 644         spi@7000d600 {
 645                 compatible = "nvidia,tegra20-slink";
 646                 reg = <0x7000d600 0x200>;
 647                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 648                 #address-cells = <1>;
 649                 #size-cells = <0>;
 650                 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
 651                 resets = <&tegra_car 44>;
 652                 reset-names = "spi";
 653                 dmas = <&apbdma 16>, <&apbdma 16>;
 654                 dma-names = "rx", "tx";
 655                 status = "disabled";
 656         };
 657
 658         spi@7000d800 {
 659                 compatible = "nvidia,tegra20-slink";
 660                 reg = <0x7000d800 0x200>;
 661                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 662                 #address-cells = <1>;
 663                 #size-cells = <0>;
 664                 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
 665                 resets = <&tegra_car 46>;
 666                 reset-names = "spi";
 667                 dmas = <&apbdma 17>, <&apbdma 17>;
 668                 dma-names = "rx", "tx";
 669                 status = "disabled";
 670         };
 671
 672         spi@7000da00 {
 673                 compatible = "nvidia,tegra20-slink";
 674                 reg = <0x7000da00 0x200>;
 675                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 676                 #address-cells = <1>;
 677                 #size-cells = <0>;
 678                 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
 679                 resets = <&tegra_car 68>;
 680                 reset-names = "spi";
 681                 dmas = <&apbdma 18>, <&apbdma 18>;
 682                 dma-names = "rx", "tx";
 683                 status = "disabled";
 684         };
 685
 686         kbc@7000e200 {
 687                 compatible = "nvidia,tegra20-kbc";
 688                 reg = <0x7000e200 0x100>;
 689                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 690                 clocks = <&tegra_car TEGRA20_CLK_KBC>;
 691                 resets = <&tegra_car 36>;
 692                 reset-names = "kbc";
 693                 status = "disabled";
 694         };
 695
 696         tegra_pmc: pmc@7000e400 {
 697                 compatible = "nvidia,tegra20-pmc";
 698                 reg = <0x7000e400 0x400>;
 699                 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
 700                 clock-names = "pclk", "clk32k_in";
 701                 #clock-cells = <1>;
 702
 703                 pd_core: core-domain {
 704                         #power-domain-cells = <0>;
 705                         operating-points-v2 = <&core_opp_table>;
 706                 };
 707
 708                 powergates {
 709                         pd_3d: td {
 710                                 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
 711                                 resets = <&mc TEGRA20_MC_RESET_3D>,
 712                                          <&tegra_car TEGRA20_CLK_GR3D>;
 713                                 power-domains = <&pd_core>;
 714                                 #power-domain-cells = <0>;
 715                         };
 716
 717                         pd_venc: venc {
 718                                 clocks = <&tegra_car TEGRA20_CLK_ISP>,
 719                                          <&tegra_car TEGRA20_CLK_VI>,
 720                                          <&tegra_car TEGRA20_CLK_CSI>;
 721                                 resets = <&mc TEGRA20_MC_RESET_ISP>,
 722                                          <&mc TEGRA20_MC_RESET_VI>,
 723                                          <&tegra_car TEGRA20_CLK_ISP>,
 724                                          <&tegra_car 20 /* VI */>,
 725                                          <&tegra_car TEGRA20_CLK_CSI>;
 726                                 power-domains = <&pd_core>;
 727                                 #power-domain-cells = <0>;
 728                         };
 729
 730                         pd_vde: vdec {
 731                                 clocks = <&tegra_car TEGRA20_CLK_VDE>;
 732                                 resets = <&mc TEGRA20_MC_RESET_VDE>,
 733                                          <&tegra_car TEGRA20_CLK_VDE>;
 734                                 power-domains = <&pd_core>;
 735                                 #power-domain-cells = <0>;
 736                         };
 737
 738                         pd_mpe: mpe {
 739                                 clocks = <&tegra_car TEGRA20_CLK_MPE>;
 740                                 resets = <&mc TEGRA20_MC_RESET_MPEA>,
 741                                          <&mc TEGRA20_MC_RESET_MPEB>,
 742                                          <&mc TEGRA20_MC_RESET_MPEC>,
 743                                          <&tegra_car TEGRA20_CLK_MPE>;
 744                                 power-domains = <&pd_core>;
 745                                 #power-domain-cells = <0>;
 746                         };
 747                 };
 748         };
 749
 750         mc: memory-controller@7000f000 {
 751                 compatible = "nvidia,tegra20-mc-gart";
 752                 reg = <0x7000f000 0x00000400>, /* controller registers */
 753                       <0x58000000 0x02000000>; /* GART aperture */
 754                 clocks = <&tegra_car TEGRA20_CLK_MC>;
 755                 clock-names = "mc";
 756                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 757                 #reset-cells = <1>;
 758                 #iommu-cells = <0>;
 759                 #interconnect-cells = <1>;
 760         };
 761
 762         emc: memory-controller@7000f400 {
 763                 compatible = "nvidia,tegra20-emc";
 764                 reg = <0x7000f400 0x400>;
 765                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 766                 clocks = <&tegra_car TEGRA20_CLK_EMC>;
 767                 power-domains = <&pd_core>;
 768                 #address-cells = <1>;
 769                 #size-cells = <0>;
 770                 #interconnect-cells = <0>;
 771
 772                 nvidia,memory-controller = <&mc>;
 773                 operating-points-v2 = <&emc_icc_dvfs_opp_table>;
 774         };
 775
 776         fuse@7000f800 {
 777                 compatible = "nvidia,tegra20-efuse";
 778                 reg = <0x7000f800 0x400>;
 779                 clocks = <&tegra_car TEGRA20_CLK_FUSE>;
 780                 clock-names = "fuse";
 781                 resets = <&tegra_car 39>;
 782                 reset-names = "fuse";
 783         };
 784
 785         pcie@80003000 {
 786                 compatible = "nvidia,tegra20-pcie";
 787                 device_type = "pci";
 788                 reg = <0x80003000 0x00000800>, /* PADS registers */
 789                       <0x80003800 0x00000200>, /* AFI registers */
 790                       <0x90000000 0x10000000>; /* configuration space */
 791                 reg-names = "pads", "afi", "cs";
 792                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
 793                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
 794                 interrupt-names = "intr", "msi";
 795
 796                 #interrupt-cells = <1>;
 797                 interrupt-map-mask = <0 0 0 0>;
 798                 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 799
 800                 bus-range = <0x00 0xff>;
 801                 #address-cells = <3>;
 802                 #size-cells = <2>;
 803
 804                 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x00001000>, /* port 0 registers */
 805                          <0x02000000 0 0x80001000 0x80001000 0 0x00001000>, /* port 1 registers */
 806                          <0x01000000 0 0          0x82000000 0 0x00010000>, /* downstream I/O */
 807                          <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, /* non-prefetchable memory */
 808                          <0x42000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
 809
 810                 clocks = <&tegra_car TEGRA20_CLK_PEX>,
 811                          <&tegra_car TEGRA20_CLK_AFI>,
 812                          <&tegra_car TEGRA20_CLK_PLL_E>;
 813                 clock-names = "pex", "afi", "pll_e";
 814                 resets = <&tegra_car 70>,
 815                          <&tegra_car 72>,
 816                          <&tegra_car 74>;
 817                 reset-names = "pex", "afi", "pcie_x";
 818                 power-domains = <&pd_core>;
 819                 operating-points-v2 = <&pcie_dvfs_opp_table>;
 820
 821                 status = "disabled";
 822
 823                 pci@1,0 {
 824                         device_type = "pci";
 825                         assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
 826                         reg = <0x000800 0 0 0 0>;
 827                         bus-range = <0x00 0xff>;
 828                         status = "disabled";
 829
 830                         #address-cells = <3>;
 831                         #size-cells = <2>;
 832                         ranges;
 833
 834                         nvidia,num-lanes = <2>;
 835                 };
 836
 837                 pci@2,0 {
 838                         device_type = "pci";
 839                         assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
 840                         reg = <0x001000 0 0 0 0>;
 841                         bus-range = <0x00 0xff>;
 842                         status = "disabled";
 843
 844                         #address-cells = <3>;
 845                         #size-cells = <2>;
 846                         ranges;
 847
 848                         nvidia,num-lanes = <2>;
 849                 };
 850         };
 851
 852         usb@c5000000 {
 853                 compatible = "nvidia,tegra20-ehci";
 854                 reg = <0xc5000000 0x4000>;
 855                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 856                 phy_type = "utmi";
 857                 clocks = <&tegra_car TEGRA20_CLK_USBD>;
 858                 resets = <&tegra_car 22>;
 859                 reset-names = "usb";
 860                 nvidia,needs-double-reset;
 861                 nvidia,phy = <&phy1>;
 862                 power-domains = <&pd_core>;
 863                 operating-points-v2 = <&usbd_dvfs_opp_table>;
 864                 status = "disabled";
 865         };
 866
 867         phy1: usb-phy@c5000000 {
 868                 compatible = "nvidia,tegra20-usb-phy";
 869                 reg = <0xc5000000 0x4000>,
 870                       <0xc5000000 0x4000>;
 871                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 872                 phy_type = "utmi";
 873                 clocks = <&tegra_car TEGRA20_CLK_USBD>,
 874                          <&tegra_car TEGRA20_CLK_PLL_U>,
 875                          <&tegra_car TEGRA20_CLK_CLK_M>,
 876                          <&tegra_car TEGRA20_CLK_USBD>;
 877                 clock-names = "reg", "pll_u", "timer", "utmi-pads";
 878                 resets = <&tegra_car 22>, <&tegra_car 22>;
 879                 reset-names = "usb", "utmi-pads";
 880                 #phy-cells = <0>;
 881                 nvidia,has-legacy-mode;
 882                 nvidia,hssync-start-delay = <9>;
 883                 nvidia,idle-wait-delay = <17>;
 884                 nvidia,elastic-limit = <16>;
 885                 nvidia,term-range-adj = <6>;
 886                 nvidia,xcvr-setup = <9>;
 887                 nvidia,xcvr-lsfslew = <1>;
 888                 nvidia,xcvr-lsrslew = <1>;
 889                 nvidia,has-utmi-pad-registers;
 890                 nvidia,pmc = <&tegra_pmc 0>;
 891                 status = "disabled";
 892         };
 893
 894         usb@c5004000 {
 895                 compatible = "nvidia,tegra20-ehci";
 896                 reg = <0xc5004000 0x4000>;
 897                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 898                 phy_type = "ulpi";
 899                 clocks = <&tegra_car TEGRA20_CLK_USB2>;
 900                 resets = <&tegra_car 58>;
 901                 reset-names = "usb";
 902                 nvidia,phy = <&phy2>;
 903                 power-domains = <&pd_core>;
 904                 operating-points-v2 = <&usb2_dvfs_opp_table>;
 905                 status = "disabled";
 906         };
 907
 908         phy2: usb-phy@c5004000 {
 909                 compatible = "nvidia,tegra20-usb-phy";
 910                 reg = <0xc5004000 0x4000>;
 911                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 912                 phy_type = "ulpi";
 913                 clocks = <&tegra_car TEGRA20_CLK_USB2>,
 914                          <&tegra_car TEGRA20_CLK_PLL_U>,
 915                          <&tegra_car TEGRA20_CLK_CDEV2>;
 916                 clock-names = "reg", "pll_u", "ulpi-link";
 917                 resets = <&tegra_car 58>, <&tegra_car 22>;
 918                 reset-names = "usb", "utmi-pads";
 919                 #phy-cells = <0>;
 920                 nvidia,pmc = <&tegra_pmc 1>;
 921                 status = "disabled";
 922         };
 923
 924         usb@c5008000 {
 925                 compatible = "nvidia,tegra20-ehci";
 926                 reg = <0xc5008000 0x4000>;
 927                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 928                 phy_type = "utmi";
 929                 clocks = <&tegra_car TEGRA20_CLK_USB3>;
 930                 resets = <&tegra_car 59>;
 931                 reset-names = "usb";
 932                 nvidia,phy = <&phy3>;
 933                 power-domains = <&pd_core>;
 934                 operating-points-v2 = <&usb3_dvfs_opp_table>;
 935                 status = "disabled";
 936         };
 937
 938         phy3: usb-phy@c5008000 {
 939                 compatible = "nvidia,tegra20-usb-phy";
 940                 reg = <0xc5008000 0x4000>,
 941                       <0xc5000000 0x4000>;
 942                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 943                 phy_type = "utmi";
 944                 clocks = <&tegra_car TEGRA20_CLK_USB3>,
 945                          <&tegra_car TEGRA20_CLK_PLL_U>,
 946                          <&tegra_car TEGRA20_CLK_CLK_M>,
 947                          <&tegra_car TEGRA20_CLK_USBD>;
 948                 clock-names = "reg", "pll_u", "timer", "utmi-pads";
 949                 resets = <&tegra_car 59>, <&tegra_car 22>;
 950                 reset-names = "usb", "utmi-pads";
 951                 #phy-cells = <0>;
 952                 nvidia,hssync-start-delay = <9>;
 953                 nvidia,idle-wait-delay = <17>;
 954                 nvidia,elastic-limit = <16>;
 955                 nvidia,term-range-adj = <6>;
 956                 nvidia,xcvr-setup = <9>;
 957                 nvidia,xcvr-lsfslew = <2>;
 958                 nvidia,xcvr-lsrslew = <2>;
 959                 nvidia,pmc = <&tegra_pmc 2>;
 960                 status = "disabled";
 961         };
 962
 963         mmc@c8000000 {
 964                 compatible = "nvidia,tegra20-sdhci";
 965                 reg = <0xc8000000 0x200>;
 966                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 967                 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
 968                 clock-names = "sdhci";
 969                 resets = <&tegra_car 14>;
 970                 reset-names = "sdhci";
 971                 power-domains = <&pd_core>;
 972                 operating-points-v2 = <&sdmmc1_dvfs_opp_table>;
 973                 status = "disabled";
 974         };
 975
 976         mmc@c8000200 {
 977                 compatible = "nvidia,tegra20-sdhci";
 978                 reg = <0xc8000200 0x200>;
 979                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 980                 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
 981                 clock-names = "sdhci";
 982                 resets = <&tegra_car 9>;
 983                 reset-names = "sdhci";
 984                 power-domains = <&pd_core>;
 985                 operating-points-v2 = <&sdmmc2_dvfs_opp_table>;
 986                 status = "disabled";
 987         };
 988
 989         mmc@c8000400 {
 990                 compatible = "nvidia,tegra20-sdhci";
 991                 reg = <0xc8000400 0x200>;
 992                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 993                 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
 994                 clock-names = "sdhci";
 995                 resets = <&tegra_car 69>;
 996                 reset-names = "sdhci";
 997                 power-domains = <&pd_core>;
 998                 operating-points-v2 = <&sdmmc3_dvfs_opp_table>;
 999                 status = "disabled";
1000         };
1001
1002         mmc@c8000600 {
1003                 compatible = "nvidia,tegra20-sdhci";
1004                 reg = <0xc8000600 0x200>;
1005                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1006                 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
1007                 clock-names = "sdhci";
1008                 resets = <&tegra_car 15>;
1009                 reset-names = "sdhci";
1010                 power-domains = <&pd_core>;
1011                 operating-points-v2 = <&sdmmc4_dvfs_opp_table>;
1012                 status = "disabled";
1013         };
1014
1015         cpus {
1016                 #address-cells = <1>;
1017                 #size-cells = <0>;
1018
1019                 cpu@0 {
1020                         device_type = "cpu";
1021                         compatible = "arm,cortex-a9";
1022                         reg = <0>;
1023                         clocks = <&tegra_car TEGRA20_CLK_CCLK>;
1024                 };
1025
1026                 cpu@1 {
1027                         device_type = "cpu";
1028                         compatible = "arm,cortex-a9";
1029                         reg = <1>;
1030                         clocks = <&tegra_car TEGRA20_CLK_CCLK>;
1031                 };
1032         };
1033
1034         pmu {
1035                 compatible = "arm,cortex-a9-pmu";
1036                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1037                              <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1038                 interrupt-affinity = <&{/cpus/cpu@0}>,
1039                                      <&{/cpus/cpu@1}>;
1040         };
1041
1042         sound-hdmi {
1043                 compatible = "simple-audio-card";
1044                 simple-audio-card,name = "NVIDIA Tegra20 HDMI";
1045
1046                 #address-cells = <1>;
1047                 #size-cells = <0>;
1048
1049                 simple-audio-card,dai-link@0 {
1050                         reg = <0>;
1051
1052                         cpu {
1053                                 sound-dai = <&tegra_spdif>;
1054                         };
1055
1056                         codec {
1057                                 sound-dai = <&tegra_hdmi>;
1058                         };
1059                 };
1060         };
1061 };