arch/arm/boot/dts/tegra20-colibri.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include "tegra20.dtsi"
   3
   4 / {
   5         model = "Toradex Colibri T20 256/512 MB";
   6         compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
   7
   8         aliases {
   9                 rtc0 = "/i2c@7000d000/tps6586x@34";
  10                 rtc1 = "/rtc@7000e000";
  11         };
  12
  13         memory@0 {
  14                 /*
  15                  * Set memory to 256 MB to be safe as this could be used on
  16                  * 256 or 512 MB module. It is expected from bootloader
  17                  * to fix this up for 512 MB version.
  18                  */
  19                 reg = <0x00000000 0x10000000>;
  20         };
  21
  22         host1x@50000000 {
  23                 hdmi@54280000 {
  24                         vdd-supply = <&hdmi_vdd_reg>;
  25                         pll-supply = <&hdmi_pll_reg>;
  26
  27                         nvidia,ddc-i2c-bus = <&i2c_ddc>;
  28                         nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  29                                 GPIO_ACTIVE_HIGH>;
  30                 };
  31         };
  32
  33         pinmux@70000014 {
  34                 pinctrl-names = "default";
  35                 pinctrl-0 = <&state_default>;
  36
  37                 state_default: pinmux {
  38                         audio_refclk {
  39                                 nvidia,pins = "cdev1";
  40                                 nvidia,function = "plla_out";
  41                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  42                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  43                         };
  44                         crt {
  45                                 nvidia,pins = "crtp";
  46                                 nvidia,function = "crt";
  47                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  48                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  49                         };
  50                         dap3 {
  51                                 nvidia,pins = "dap3";
  52                                 nvidia,function = "dap3";
  53                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  54                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  55                         };
  56                         displaya {
  57                                 nvidia,pins = "ld0", "ld1", "ld2", "ld3",
  58                                         "ld4", "ld5", "ld6", "ld7", "ld8",
  59                                         "ld9", "ld10", "ld11", "ld12", "ld13",
  60                                         "ld14", "ld15", "ld16", "ld17",
  61                                         "lhs", "lpw0", "lpw2", "lsc0",
  62                                         "lsc1", "lsck", "lsda", "lspi", "lvs";
  63                                 nvidia,function = "displaya";
  64                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  65                         };
  66                         gpio_dte {
  67                                 nvidia,pins = "dte";
  68                                 nvidia,function = "rsvd1";
  69                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  70                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  71                         };
  72                         gpio_gmi {
  73                                 nvidia,pins = "ata", "atc", "atd", "ate",
  74                                         "dap1", "dap2", "dap4", "gpu", "irrx",
  75                                         "irtx", "spia", "spib", "spic";
  76                                 nvidia,function = "gmi";
  77                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  78                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  79                         };
  80                         gpio_pta {
  81                                 nvidia,pins = "pta";
  82                                 nvidia,function = "rsvd4";
  83                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  84                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  85                         };
  86                         gpio_uac {
  87                                 nvidia,pins = "uac";
  88                                 nvidia,function = "rsvd2";
  89                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  90                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  91                         };
  92                         hdint {
  93                                 nvidia,pins = "hdint";
  94                                 nvidia,function = "hdmi";
  95                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  96                         };
  97                         i2c1 {
  98                                 nvidia,pins = "rm";
  99                                 nvidia,function = "i2c1";
 100                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 101                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 102                         };
 103                         i2c3 {
 104                                 nvidia,pins = "dtf";
 105                                 nvidia,function = "i2c3";
 106                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 107                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 108                         };
 109                         i2cddc {
 110                                 nvidia,pins = "ddc";
 111                                 nvidia,function = "i2c2";
 112                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 113                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 114                         };
 115                         i2cp {
 116                                 nvidia,pins = "i2cp";
 117                                 nvidia,function = "i2cp";
 118                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 119                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 120                         };
 121                         irda {
 122                                 nvidia,pins = "uad";
 123                                 nvidia,function = "irda";
 124                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 125                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 126                         };
 127                         nand {
 128                                 nvidia,pins = "kbca", "kbcc", "kbcd",
 129                                         "kbce", "kbcf";
 130                                 nvidia,function = "nand";
 131                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 132                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 133                         };
 134                         owc {
 135                                 nvidia,pins = "owc";
 136                                 nvidia,function = "owr";
 137                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 138                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 139                         };
 140                         pmc {
 141                                 nvidia,pins = "pmc";
 142                                 nvidia,function = "pwr_on";
 143                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 144                         };
 145                         pwm {
 146                                 nvidia,pins = "sdb", "sdc", "sdd";
 147                                 nvidia,function = "pwm";
 148                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 149                         };
 150                         sdio4 {
 151                                 nvidia,pins = "atb", "gma", "gme";
 152                                 nvidia,function = "sdio4";
 153                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 154                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 155                         };
 156                         spi1 {
 157                                 nvidia,pins = "spid", "spie", "spif";
 158                                 nvidia,function = "spi1";
 159                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 160                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 161                         };
 162                         spi4 {
 163                                 nvidia,pins = "slxa", "slxc", "slxd", "slxk";
 164                                 nvidia,function = "spi4";
 165                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 166                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 167                         };
 168                         uarta {
 169                                 nvidia,pins = "sdio1";
 170                                 nvidia,function = "uarta";
 171                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 172                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 173                         };
 174                         uartd {
 175                                 nvidia,pins = "gmc";
 176                                 nvidia,function = "uartd";
 177                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 178                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 179                         };
 180                         ulpi {
 181                                 nvidia,pins = "uaa", "uab", "uda";
 182                                 nvidia,function = "ulpi";
 183                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 184                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 185                         };
 186                         ulpi_refclk {
 187                                 nvidia,pins = "cdev2";
 188                                 nvidia,function = "pllp_out4";
 189                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 190                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 191                         };
 192                         usb_gpio {
 193                                 nvidia,pins = "spig", "spih";
 194                                 nvidia,function = "spi2_alt";
 195                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 196                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 197                         };
 198                         vi {
 199                                 nvidia,pins = "dta", "dtb", "dtc", "dtd";
 200                                 nvidia,function = "vi";
 201                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 202                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 203                         };
 204                         vi_sc {
 205                                 nvidia,pins = "csus";
 206                                 nvidia,function = "vi_sensor_clk";
 207                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 208                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 209                         };
 210                 };
 211         };
 212
 213         ac97: ac97@70002000 {
 214                 status = "okay";
 215                 nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
 216                         GPIO_ACTIVE_HIGH>;
 217                 nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
 218                         GPIO_ACTIVE_HIGH>;
 219         };
 220
 221         nand-controller@70008000 {
 222                 status = "okay";
 223
 224                 nand@0 {
 225                         reg = <0>;
 226                         #address-cells = <1>;
 227                         #size-cells = <1>;
 228                         nand-bus-width = <8>;
 229                         nand-on-flash-bbt;
 230                         nand-ecc-algo = "bch";
 231                         nand-is-boot-medium;
 232                         nand-ecc-maximize;
 233                         wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
 234                 };
 235         };
 236
 237         /*
 238          * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
 239          * board)
 240          */
 241         i2c@7000c000 {
 242                 clock-frequency = <400000>;
 243         };
 244
 245         /* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */
 246         i2c_ddc: i2c@7000c400 {
 247                 clock-frequency = <10000>;
 248         };
 249
 250         /* GEN2_I2C: unused */
 251
 252         /* CAM/GEN3_I2C: used as EXT_IO1/2 GPIOs on SODIMM pin 133/127 */
 253
 254         /* PWR_I2C: power I2C to PMIC and temperature sensor (On-module) */
 255         i2c@7000d000 {
 256                 status = "okay";
 257                 clock-frequency = <100000>;
 258
 259                 pmic: tps6586x@34 {
 260                         compatible = "ti,tps6586x";
 261                         reg = <0x34>;
 262                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 263
 264                         ti,system-power-controller;
 265
 266                         #gpio-cells = <2>;
 267                         gpio-controller;
 268
 269                         sys-supply = <&vdd_3v3_reg>;
 270                         vin-sm0-supply = <&sys_reg>;
 271                         vin-sm1-supply = <&sys_reg>;
 272                         vin-sm2-supply = <&sys_reg>;
 273                         vinldo01-supply = <&sm2_reg>;
 274                         vinldo23-supply = <&vdd_3v3_reg>;
 275                         vinldo4-supply = <&vdd_3v3_reg>;
 276                         vinldo678-supply = <&vdd_3v3_reg>;
 277                         vinldo9-supply = <&vdd_3v3_reg>;
 278
 279                         regulators {
 280                                 #address-cells = <1>;
 281                                 #size-cells = <0>;
 282
 283                                 sys_reg: regulator@0 {
 284                                         reg = <0>;
 285                                         regulator-compatible = "sys";
 286                                         regulator-name = "vdd_sys";
 287                                         regulator-always-on;
 288                                 };
 289
 290                                 regulator@1 {
 291                                         reg = <1>;
 292                                         regulator-compatible = "sm0";
 293                                         regulator-name = "vdd_sm0,vdd_core";
 294                                         regulator-min-microvolt = <1200000>;
 295                                         regulator-max-microvolt = <1200000>;
 296                                         regulator-always-on;
 297                                 };
 298
 299                                 regulator@2 {
 300                                         reg = <2>;
 301                                         regulator-compatible = "sm1";
 302                                         regulator-name = "vdd_sm1,vdd_cpu";
 303                                         regulator-min-microvolt = <1000000>;
 304                                         regulator-max-microvolt = <1000000>;
 305                                         regulator-always-on;
 306                                 };
 307
 308                                 sm2_reg: regulator@3 {
 309                                         reg = <3>;
 310                                         regulator-compatible = "sm2";
 311                                         regulator-name = "vdd_sm2,vin_ldo*";
 312                                         regulator-min-microvolt = <1800000>;
 313                                         regulator-max-microvolt = <1800000>;
 314                                         regulator-always-on;
 315                                 };
 316
 317                                 /* LDO0 is not connected to anything */
 318
 319                                 regulator@5 {
 320                                         reg = <5>;
 321                                         regulator-compatible = "ldo1";
 322                                         regulator-name = "vdd_ldo1,avdd_pll*";
 323                                         regulator-min-microvolt = <1100000>;
 324                                         regulator-max-microvolt = <1100000>;
 325                                         regulator-always-on;
 326                                 };
 327
 328                                 regulator@6 {
 329                                         reg = <6>;
 330                                         regulator-compatible = "ldo2";
 331                                         regulator-name = "vdd_ldo2,vdd_rtc";
 332                                         regulator-min-microvolt = <1200000>;
 333                                         regulator-max-microvolt = <1200000>;
 334                                 };
 335
 336                                 /* LDO3 is not connected to anything */
 337
 338                                 regulator@8 {
 339                                         reg = <8>;
 340                                         regulator-compatible = "ldo4";
 341                                         regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
 342                                         regulator-min-microvolt = <1800000>;
 343                                         regulator-max-microvolt = <1800000>;
 344                                         regulator-always-on;
 345                                 };
 346
 347                                 ldo5_reg: regulator@9 {
 348                                         reg = <9>;
 349                                         regulator-compatible = "ldo5";
 350                                         regulator-name = "vdd_ldo5,vdd_fuse";
 351                                         regulator-min-microvolt = <3300000>;
 352                                         regulator-max-microvolt = <3300000>;
 353                                         regulator-always-on;
 354                                 };
 355
 356                                 regulator@10 {
 357                                         reg = <10>;
 358                                         regulator-compatible = "ldo6";
 359                                         regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
 360                                         regulator-min-microvolt = <2850000>;
 361                                         regulator-max-microvolt = <2850000>;
 362                                 };
 363
 364                                 hdmi_vdd_reg: regulator@11 {
 365                                         reg = <11>;
 366                                         regulator-compatible = "ldo7";
 367                                         regulator-name = "vdd_ldo7,avdd_hdmi";
 368                                         regulator-min-microvolt = <3300000>;
 369                                         regulator-max-microvolt = <3300000>;
 370                                 };
 371
 372                                 hdmi_pll_reg: regulator@12 {
 373                                         reg = <12>;
 374                                         regulator-compatible = "ldo8";
 375                                         regulator-name = "vdd_ldo8,avdd_hdmi_pll";
 376                                         regulator-min-microvolt = <1800000>;
 377                                         regulator-max-microvolt = <1800000>;
 378                                 };
 379
 380                                 regulator@13 {
 381                                         reg = <13>;
 382                                         regulator-compatible = "ldo9";
 383                                         regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
 384                                         regulator-min-microvolt = <2850000>;
 385                                         regulator-max-microvolt = <2850000>;
 386                                         regulator-always-on;
 387                                 };
 388
 389                                 regulator@14 {
 390                                         reg = <14>;
 391                                         regulator-compatible = "ldo_rtc";
 392                                         regulator-name = "vdd_rtc_out,vdd_cell";
 393                                         regulator-min-microvolt = <3300000>;
 394                                         regulator-max-microvolt = <3300000>;
 395                                         regulator-always-on;
 396                                 };
 397                         };
 398                 };
 399
 400                 temperature-sensor@4c {
 401                         compatible = "national,lm95245";
 402                         reg = <0x4c>;
 403                 };
 404         };
 405
 406         pmc@7000e400 {
 407                 nvidia,suspend-mode = <1>;
 408                 nvidia,cpu-pwr-good-time = <5000>;
 409                 nvidia,cpu-pwr-off-time = <5000>;
 410                 nvidia,core-pwr-good-time = <3845 3845>;
 411                 nvidia,core-pwr-off-time = <3875>;
 412                 nvidia,sys-clock-req-active-high;
 413         };
 414
 415         memory-controller@7000f400 {
 416                 emc-table@83250 {
 417                         reg = <83250>;
 418                         compatible = "nvidia,tegra20-emc-table";
 419                         clock-frequency = <83250>;
 420                         nvidia,emc-registers =   <0x00000005 0x00000011
 421                                 0x00000004 0x00000002 0x00000004 0x00000004
 422                                 0x00000001 0x0000000a 0x00000002 0x00000002
 423                                 0x00000001 0x00000001 0x00000003 0x00000004
 424                                 0x00000003 0x00000009 0x0000000c 0x0000025f
 425                                 0x00000000 0x00000003 0x00000003 0x00000002
 426                                 0x00000002 0x00000001 0x00000008 0x000000c8
 427                                 0x00000003 0x00000005 0x00000003 0x0000000c
 428                                 0x00000002 0x00000000 0x00000000 0x00000002
 429                                 0x00000000 0x00000000 0x00000083 0x00520006
 430                                 0x00000010 0x00000008 0x00000000 0x00000000
 431                                 0x00000000 0x00000000 0x00000000 0x00000000>;
 432                 };
 433                 emc-table@133200 {
 434                         reg = <133200>;
 435                         compatible = "nvidia,tegra20-emc-table";
 436                         clock-frequency = <133200>;
 437                         nvidia,emc-registers =   <0x00000008 0x00000019
 438                                 0x00000006 0x00000002 0x00000004 0x00000004
 439                                 0x00000001 0x0000000a 0x00000002 0x00000002
 440                                 0x00000002 0x00000001 0x00000003 0x00000004
 441                                 0x00000003 0x00000009 0x0000000c 0x0000039f
 442                                 0x00000000 0x00000003 0x00000003 0x00000002
 443                                 0x00000002 0x00000001 0x00000008 0x000000c8
 444                                 0x00000003 0x00000007 0x00000003 0x0000000c
 445                                 0x00000002 0x00000000 0x00000000 0x00000002
 446                                 0x00000000 0x00000000 0x00000083 0x00510006
 447                                 0x00000010 0x00000008 0x00000000 0x00000000
 448                                 0x00000000 0x00000000 0x00000000 0x00000000>;
 449                 };
 450                 emc-table@166500 {
 451                         reg = <166500>;
 452                         compatible = "nvidia,tegra20-emc-table";
 453                         clock-frequency = <166500>;
 454                         nvidia,emc-registers =   <0x0000000a 0x00000021
 455                                 0x00000008 0x00000003 0x00000004 0x00000004
 456                                 0x00000002 0x0000000a 0x00000003 0x00000003
 457                                 0x00000002 0x00000001 0x00000003 0x00000004
 458                                 0x00000003 0x00000009 0x0000000c 0x000004df
 459                                 0x00000000 0x00000003 0x00000003 0x00000003
 460                                 0x00000003 0x00000001 0x00000009 0x000000c8
 461                                 0x00000003 0x00000009 0x00000004 0x0000000c
 462                                 0x00000002 0x00000000 0x00000000 0x00000002
 463                                 0x00000000 0x00000000 0x00000083 0x004f0006
 464                                 0x00000010 0x00000008 0x00000000 0x00000000
 465                                 0x00000000 0x00000000 0x00000000 0x00000000>;
 466                 };
 467                 emc-table@333000 {
 468                         reg = <333000>;
 469                         compatible = "nvidia,tegra20-emc-table";
 470                         clock-frequency = <333000>;
 471                         nvidia,emc-registers =   <0x00000014 0x00000041
 472                                 0x0000000f 0x00000005 0x00000004 0x00000005
 473                                 0x00000003 0x0000000a 0x00000005 0x00000005
 474                                 0x00000004 0x00000001 0x00000003 0x00000004
 475                                 0x00000003 0x00000009 0x0000000c 0x000009ff
 476                                 0x00000000 0x00000003 0x00000003 0x00000005
 477                                 0x00000005 0x00000001 0x0000000e 0x000000c8
 478                                 0x00000003 0x00000011 0x00000006 0x0000000c
 479                                 0x00000002 0x00000000 0x00000000 0x00000002
 480                                 0x00000000 0x00000000 0x00000083 0x00380006
 481                                 0x00000010 0x00000008 0x00000000 0x00000000
 482                                 0x00000000 0x00000000 0x00000000 0x00000000>;
 483                 };
 484         };
 485
 486         usb@c5004000 {
 487                 status = "okay";
 488                 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
 489                         GPIO_ACTIVE_LOW>;
 490         };
 491
 492         usb-phy@c5004000 {
 493                 status = "okay";
 494                 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
 495                         GPIO_ACTIVE_LOW>;
 496         };
 497
 498         sdhci@c8000600 {
 499                 cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
 500         };
 501
 502         clocks {
 503                 compatible = "simple-bus";
 504                 #address-cells = <1>;
 505                 #size-cells = <0>;
 506
 507                 clk32k_in: clock@0 {
 508                         compatible = "fixed-clock";
 509                         reg = <0>;
 510                         #clock-cells = <0>;
 511                         clock-frequency = <32768>;
 512                 };
 513         };
 514
 515         regulators {
 516                 compatible = "simple-bus";
 517                 #address-cells = <1>;
 518                 #size-cells = <0>;
 519
 520                 vdd_3v3_reg: regulator@100 {
 521                         compatible = "regulator-fixed";
 522                         reg = <100>;
 523                         regulator-name = "vdd_3v3";
 524                         regulator-min-microvolt = <3300000>;
 525                         regulator-max-microvolt = <3300000>;
 526                         regulator-always-on;
 527                 };
 528
 529                 regulator@101 {
 530                         compatible = "regulator-fixed";
 531                         reg = <101>;
 532                         regulator-name = "internal_usb";
 533                         regulator-min-microvolt = <5000000>;
 534                         regulator-max-microvolt = <5000000>;
 535                         enable-active-high;
 536                         regulator-boot-on;
 537                         regulator-always-on;
 538                         gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
 539                 };
 540         };
 541
 542         sound {
 543                 compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
 544                                  "nvidia,tegra-audio-wm9712";
 545                 nvidia,model = "Colibri T20 AC97 Audio";
 546
 547                 nvidia,audio-routing =
 548                         "Headphone", "HPOUTL",
 549                         "Headphone", "HPOUTR",
 550                         "LineIn", "LINEINL",
 551                         "LineIn", "LINEINR",
 552                         "Mic", "MIC1";
 553
 554                 nvidia,ac97-controller = <&ac97>;
 555
 556                 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
 557                          <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
 558                          <&tegra_car TEGRA20_CLK_CDEV1>;
 559                 clock-names = "pll_a", "pll_a_out0", "mclk";
 560         };
 561 };