arch/arm/boot/dts/tegra20-colibri.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include "tegra20.dtsi"
   3
   4 /*
   5  * Toradex Colibri T20 Module Device Tree
   6  * Compatible for Revisions Colibri T20 256MB V1.1B, V1.2A;
   7  * Colibri T20 256MB IT V1.2A; Colibri T20 512MB V1.1C, V1.2A;
   8  * Colibri T20 512MB IT V1.2A
   9  */
  10 / {
  11         memory@0 {
  12                 /*
  13                  * Set memory to 256 MB to be safe as this could be used on
  14                  * 256 or 512 MB module. It is expected from bootloader
  15                  * to fix this up for 512 MB version.
  16                  */
  17                 reg = <0x00000000 0x10000000>;
  18         };
  19
  20         host1x@50000000 {
  21                 hdmi@54280000 {
  22                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  23                         nvidia,hpd-gpio =
  24                                 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  25                         pll-supply = <&reg_1v8_avdd_hdmi_pll>;
  26                         vdd-supply = <&reg_3v3_avdd_hdmi>;
  27                 };
  28         };
  29
  30         pinmux@70000014 {
  31                 pinctrl-names = "default";
  32                 pinctrl-0 = <&state_default>;
  33
  34                 state_default: pinmux {
  35                         /* Analogue Audio AC97 to WM9712 (On-module) */
  36                         audio-refclk {
  37                                 nvidia,pins = "cdev1";
  38                                 nvidia,function = "plla_out";
  39                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  40                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  41                         };
  42                         dap3 {
  43                                 nvidia,pins = "dap3";
  44                                 nvidia,function = "dap3";
  45                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  46                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  47                         };
  48
  49                         /*
  50                          * AC97_RESET, ULPI_RESET, AC97_INT aka WM9712 GENIRQ
  51                          * (All on-module), SODIMM Pin 45 Wakeup
  52                          */
  53                         gpio-uac {
  54                                 nvidia,pins = "uac";
  55                                 nvidia,function = "rsvd2";
  56                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  57                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  58                         };
  59
  60                         /*
  61                          * Buffer Enables for nPWE and RDnWR (On-module,
  62                          * see GPIO hogging further down below)
  63                          */
  64                         gpio-pta {
  65                                 nvidia,pins = "pta";
  66                                 nvidia,function = "rsvd4";
  67                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  68                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  69                         };
  70
  71                         /*
  72                          * CLK_32K_OUT, CORE_PWR_REQ, CPU_PWR_REQ, PWR_INT_N,
  73                          * SYS_CLK_REQ (All on-module)
  74                          */
  75                         pmc {
  76                                 nvidia,pins = "pmc";
  77                                 nvidia,function = "pwr_on";
  78                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  79                         };
  80
  81                         /*
  82                          * Colibri Address/Data Bus (GMI)
  83                          * Note: spid and spie optionally used for SPI1
  84                          */
  85                         gmi {
  86                                 nvidia,pins = "atc", "atd", "ate", "dap1",
  87                                               "dap2", "dap4", "gmd", "gpu",
  88                                               "irrx", "irtx", "spia", "spib",
  89                                               "spic", "spid", "spie", "uca",
  90                                               "ucb";
  91                                 nvidia,function = "gmi";
  92                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  93                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  94                         };
  95                         /* Further pins may be used as GPIOs */
  96                         gmi-gpio1 {
  97                                 nvidia,pins = "lpw0", "lsc1", "lsck", "lsda";
  98                                 nvidia,function = "hdmi";
  99                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 100                         };
 101                         gmi-gpio2 {
 102                                 nvidia,pins = "lcsn", "ldc", "lm0", "lsdi";
 103                                 nvidia,function = "rsvd4";
 104                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 105                         };
 106
 107                         /* Colibri BL_ON */
 108                         bl-on {
 109                                 nvidia,pins = "dta";
 110                                 nvidia,function = "rsvd1";
 111                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 112                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 113                         };
 114
 115                         /* Colibri Backlight PWM<A>, PWM<B> */
 116                         sdc {
 117                                 nvidia,pins = "sdc";
 118                                 nvidia,function = "pwm";
 119                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 120                         };
 121
 122                         /* Colibri DDC */
 123                         ddc {
 124                                 nvidia,pins = "ddc";
 125                                 nvidia,function = "i2c2";
 126                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 127                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 128                         };
 129
 130                         /*
 131                          * Colibri EXT_IO*
 132                          * Note: dtf optionally used for I2C3
 133                          */
 134                         ext-io {
 135                                 nvidia,pins = "dtf", "spdi";
 136                                 nvidia,function = "rsvd2";
 137                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 138                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 139                         };
 140
 141                         /*
 142                          * Colibri Ethernet (On-module)
 143                          * ULPI EHCI instance 1 USB2_DP/N -> AX88772B
 144                          */
 145                         ulpi {
 146                                 nvidia,pins = "uaa", "uab", "uda";
 147                                 nvidia,function = "ulpi";
 148                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 149                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 150                         };
 151                         ulpi-refclk {
 152                                 nvidia,pins = "cdev2";
 153                                 nvidia,function = "pllp_out4";
 154                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 155                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 156                         };
 157
 158                         /* Colibri HOTPLUG_DETECT (HDMI) */
 159                         hotplug-detect {
 160                                 nvidia,pins = "hdint";
 161                                 nvidia,function = "hdmi";
 162                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 163                         };
 164
 165                         /* Colibri I2C */
 166                         i2c {
 167                                 nvidia,pins = "rm";
 168                                 nvidia,function = "i2c1";
 169                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 170                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 171                         };
 172
 173                         /*
 174                          * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
 175                          * today's display need DE, disable LCD_M1
 176                          */
 177                         lm1 {
 178                                 nvidia,pins = "lm1";
 179                                 nvidia,function = "rsvd3";
 180                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 181                         };
 182
 183                         /* Colibri LCD (L_* resp. LDD<*>) */
 184                         lcd {
 185                                 nvidia,pins = "ld0", "ld1", "ld2", "ld3",
 186                                               "ld4", "ld5", "ld6", "ld7",
 187                                               "ld8", "ld9", "ld10", "ld11",
 188                                               "ld12", "ld13", "ld14", "ld15",
 189                                               "ld16", "ld17", "lhs", "lsc0",
 190                                               "lspi", "lvs";
 191                                 nvidia,function = "displaya";
 192                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 193                         };
 194                         /* Colibri LCD (Optional 24 BPP Support) */
 195                         lcd-24 {
 196                                 nvidia,pins = "ldi", "lhp0", "lhp1", "lhp2",
 197                                               "lpp", "lvp1";
 198                                 nvidia,function = "displaya";
 199                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 200                         };
 201
 202                         /* Colibri MMC */
 203                         mmc {
 204                                 nvidia,pins = "atb", "gma";
 205                                 nvidia,function = "sdio4";
 206                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 207                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 208                         };
 209
 210                         /* Colibri MMCCD */
 211                         mmccd {
 212                                 nvidia,pins = "gmb";
 213                                 nvidia,function = "gmi_int";
 214                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 215                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 216                         };
 217
 218                         /* Colibri MMC (Optional 8-bit) */
 219                         mmc-8bit {
 220                                 nvidia,pins = "gme";
 221                                 nvidia,function = "sdio4";
 222                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 223                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 224                         };
 225
 226                         /*
 227                          * Colibri Parallel Camera (Optional)
 228                          * pins multiplexed with others and therefore disabled
 229                          * Note: dta used for BL_ON by default
 230                          */
 231                         cif-mclk {
 232                                 nvidia,pins = "csus";
 233                                 nvidia,function = "vi_sensor_clk";
 234                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 235                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 236                         };
 237                         cif {
 238                                 nvidia,pins = "dtb", "dtc", "dtd";
 239                                 nvidia,function = "vi";
 240                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 241                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 242                         };
 243
 244                         /* Colibri PWM<C>, PWM<D> */
 245                         sdb_sdd {
 246                                 nvidia,pins = "sdb", "sdd";
 247                                 nvidia,function = "pwm";
 248                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 249                         };
 250
 251                         /* Colibri SSP */
 252                         ssp {
 253                                 nvidia,pins = "slxa", "slxc", "slxd", "slxk";
 254                                 nvidia,function = "spi4";
 255                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 256                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 257                         };
 258
 259                         /* Colibri UART-A */
 260                         uart-a {
 261                                 nvidia,pins = "sdio1";
 262                                 nvidia,function = "uarta";
 263                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 264                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 265                         };
 266                         uart-a-dsr {
 267                                 nvidia,pins = "lpw1";
 268                                 nvidia,function = "rsvd3";
 269                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 270                         };
 271                         uart-a-dcd {
 272                                 nvidia,pins = "lpw2";
 273                                 nvidia,function = "hdmi";
 274                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 275                         };
 276
 277                         /* Colibri UART-B */
 278                         uart-b {
 279                                 nvidia,pins = "gmc";
 280                                 nvidia,function = "uartd";
 281                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 282                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 283                         };
 284
 285                         /* Colibri UART-C */
 286                         uart-c {
 287                                 nvidia,pins = "uad";
 288                                 nvidia,function = "irda";
 289                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 290                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 291                         };
 292
 293                         /* Colibri USB_CDET */
 294                         usb-cdet {
 295                                 nvidia,pins = "spdo";
 296                                 nvidia,function = "rsvd2";
 297                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 298                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 299                         };
 300
 301                         /* Colibri USBH_OC */
 302                         usbh-oc {
 303                                 nvidia,pins = "spih";
 304                                 nvidia,function = "spi2_alt";
 305                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 306                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 307                         };
 308
 309                         /* Colibri USBH_PEN */
 310                         usbh-pen {
 311                                 nvidia,pins = "spig";
 312                                 nvidia,function = "spi2_alt";
 313                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 314                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 315                         };
 316
 317                         /* Colibri VGA not supported */
 318                         vga {
 319                                 nvidia,pins = "crtp";
 320                                 nvidia,function = "crt";
 321                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 322                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 323                         };
 324
 325                         /* I2C3 (Optional) */
 326                         i2c3 {
 327                                 nvidia,pins = "dtf";
 328                                 nvidia,function = "i2c3";
 329                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 330                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 331                         };
 332
 333                         /* JTAG_RTCK */
 334                         jtag-rtck {
 335                                 nvidia,pins = "gpu7";
 336                                 nvidia,function = "rtck";
 337                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 338                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 339                         };
 340
 341                         /*
 342                          * LAN_RESET, LAN_EXT_WAKEUP and LAN_PME
 343                          * (All On-module)
 344                          */
 345                         gpio-gpv {
 346                                 nvidia,pins = "gpv";
 347                                 nvidia,function = "rsvd2";
 348                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 349                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 350                         };
 351
 352                         /*
 353                          * LAN_V_BUS, VDD_FAULT, BATT_FAULT, WM9712 PENDOWN
 354                          * (All On-module); Colibri CAN_INT
 355                          */
 356                         gpio-dte {
 357                                 nvidia,pins = "dte";
 358                                 nvidia,function = "rsvd1";
 359                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 360                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 361                         };
 362
 363                         /* NAND (On-module) */
 364                         nand {
 365                                 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
 366                                               "kbce", "kbcf";
 367                                 nvidia,function = "nand";
 368                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 369                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 370                         };
 371
 372                         /* Onewire (Optional) */
 373                         owr {
 374                                 nvidia,pins = "owc";
 375                                 nvidia,function = "owr";
 376                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 377                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 378                         };
 379
 380                         /* Power I2C (On-module) */
 381                         i2cp {
 382                                 nvidia,pins = "i2cp";
 383                                 nvidia,function = "i2cp";
 384                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 385                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 386                         };
 387
 388                         /* RESET_OUT */
 389                         reset-out {
 390                                 nvidia,pins = "ata";
 391                                 nvidia,function = "gmi";
 392                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 393                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 394                         };
 395
 396                         /*
 397                          * SPI1 (Optional)
 398                          * Note: spid and spie used for Colibri Address/Data
 399                          *       Bus (GMI)
 400                          */
 401                         spi1 {
 402                                 nvidia,pins = "spid", "spie", "spif";
 403                                 nvidia,function = "spi1";
 404                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 405                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 406                         };
 407
 408                         /*
 409                          * THERMD_ALERT# (On-module), unlatched I2C address pin
 410                          * of LM95245 temperature sensor therefore requires
 411                          * disabling for now
 412                          */
 413                         lvp0 {
 414                                 nvidia,pins = "lvp0";
 415                                 nvidia,function = "rsvd3";
 416                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 417                         };
 418                 };
 419         };
 420
 421         tegra_ac97: ac97@70002000 {
 422                 status = "okay";
 423                 nvidia,codec-reset-gpio =
 424                         <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
 425                 nvidia,codec-sync-gpio =
 426                         <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
 427         };
 428
 429         serial@70006040 {
 430                 compatible = "nvidia,tegra20-hsuart";
 431                 /delete-property/ reg-shift;
 432         };
 433
 434         serial@70006300 {
 435                 compatible = "nvidia,tegra20-hsuart";
 436                 /delete-property/ reg-shift;
 437         };
 438
 439         nand-controller@70008000 {
 440                 status = "okay";
 441
 442                 nand@0 {
 443                         reg = <0>;
 444                         #address-cells = <1>;
 445                         #size-cells = <1>;
 446                         nand-bus-width = <8>;
 447                         nand-on-flash-bbt;
 448                         nand-ecc-algo = "bch";
 449                         nand-is-boot-medium;
 450                         nand-ecc-maximize;
 451                         wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
 452                 };
 453         };
 454
 455         /*
 456          * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
 457          * board)
 458          */
 459         i2c@7000c000 {
 460                 clock-frequency = <400000>;
 461         };
 462
 463         /* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */
 464         hdmi_ddc: i2c@7000c400 {
 465                 clock-frequency = <10000>;
 466         };
 467
 468         /* GEN2_I2C: unused */
 469
 470         /* CAM/GEN3_I2C: used as EXT_IO1/2 GPIOs on SODIMM pin 133/127 */
 471
 472         /* PWR_I2C: power I2C to PMIC and temperature sensor (On-module) */
 473         i2c@7000d000 {
 474                 status = "okay";
 475                 clock-frequency = <100000>;
 476
 477                 pmic@34 {
 478                         compatible = "ti,tps6586x";
 479                         reg = <0x34>;
 480                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 481                         ti,system-power-controller;
 482                         #gpio-cells = <2>;
 483                         gpio-controller;
 484                         sys-supply = <&reg_module_3v3>;
 485                         vin-sm0-supply = <&reg_3v3_vsys>;
 486                         vin-sm1-supply = <&reg_3v3_vsys>;
 487                         vin-sm2-supply = <&reg_3v3_vsys>;
 488                         vinldo01-supply = <&reg_1v8_vdd_ddr2>;
 489                         vinldo23-supply = <&reg_module_3v3>;
 490                         vinldo4-supply = <&reg_module_3v3>;
 491                         vinldo678-supply = <&reg_module_3v3>;
 492                         vinldo9-supply = <&reg_module_3v3>;
 493
 494                         regulators {
 495                                 reg_3v3_vsys: sys {
 496                                         regulator-name = "VSYS_3.3V";
 497                                         regulator-always-on;
 498                                 };
 499
 500                                 vdd_core: sm0 {
 501                                         regulator-name = "VDD_CORE_1.2V";
 502                                         regulator-min-microvolt = <1200000>;
 503                                         regulator-max-microvolt = <1200000>;
 504                                         regulator-always-on;
 505                                 };
 506
 507                                 sm1 {
 508                                         regulator-name = "VDD_CPU_1.0V";
 509                                         regulator-min-microvolt = <1000000>;
 510                                         regulator-max-microvolt = <1000000>;
 511                                         regulator-always-on;
 512                                 };
 513
 514                                 reg_1v8_vdd_ddr2: sm2 {
 515                                         regulator-name = "VDD_DDR2_1.8V";
 516                                         regulator-min-microvolt = <1800000>;
 517                                         regulator-max-microvolt = <1800000>;
 518                                         regulator-always-on;
 519                                 };
 520
 521                                 /* LDO0 is not connected to anything */
 522
 523                                 /*
 524                                  * +3.3V_ENABLE_N switching via FET:
 525                                  * AVDD_AUDIO_S and +3.3V
 526                                  * see also +3.3V fixed supply
 527                                  */
 528                                 ldo1 {
 529                                         regulator-name = "AVDD_PLL_1.1V";
 530                                         regulator-min-microvolt = <1100000>;
 531                                         regulator-max-microvolt = <1100000>;
 532                                         regulator-always-on;
 533                                 };
 534
 535                                 ldo2 {
 536                                         regulator-name = "VDD_RTC_1.2V";
 537                                         regulator-min-microvolt = <1200000>;
 538                                         regulator-max-microvolt = <1200000>;
 539                                 };
 540
 541                                 /* LDO3 is not connected to anything */
 542
 543                                 ldo4 {
 544                                         regulator-name = "VDDIO_SYS_1.8V";
 545                                         regulator-min-microvolt = <1800000>;
 546                                         regulator-max-microvolt = <1800000>;
 547                                         regulator-always-on;
 548                                 };
 549
 550                                 /* Switched via FET from regular +3.3V */
 551                                 ldo5 {
 552                                         regulator-name = "+3.3V_USB";
 553                                         regulator-min-microvolt = <3300000>;
 554                                         regulator-max-microvolt = <3300000>;
 555                                         regulator-always-on;
 556                                 };
 557
 558                                 ldo6 {
 559                                         regulator-name = "AVDD_VDAC_2.85V";
 560                                         regulator-min-microvolt = <2850000>;
 561                                         regulator-max-microvolt = <2850000>;
 562                                 };
 563
 564                                 reg_3v3_avdd_hdmi: ldo7 {
 565                                         regulator-name = "AVDD_HDMI_3.3V";
 566                                         regulator-min-microvolt = <3300000>;
 567                                         regulator-max-microvolt = <3300000>;
 568                                 };
 569
 570                                 reg_1v8_avdd_hdmi_pll: ldo8 {
 571                                         regulator-name = "AVDD_HDMI_PLL_1.8V";
 572                                         regulator-min-microvolt = <1800000>;
 573                                         regulator-max-microvolt = <1800000>;
 574                                 };
 575
 576                                 ldo9 {
 577                                         regulator-name = "VDDIO_RX_DDR_2.85V";
 578                                         regulator-min-microvolt = <2850000>;
 579                                         regulator-max-microvolt = <2850000>;
 580                                         regulator-always-on;
 581                                 };
 582
 583                                 ldo_rtc {
 584                                         regulator-name = "VCC_BATT";
 585                                         regulator-min-microvolt = <3300000>;
 586                                         regulator-max-microvolt = <3300000>;
 587                                         regulator-always-on;
 588                                 };
 589                         };
 590                 };
 591
 592                 /* LM95245 temperature sensor */
 593                 temp-sensor@4c {
 594                         compatible = "national,lm95245";
 595                         reg = <0x4c>;
 596                 };
 597         };
 598
 599         pmc@7000e400 {
 600                 nvidia,suspend-mode = <1>;
 601                 nvidia,cpu-pwr-good-time = <5000>;
 602                 nvidia,cpu-pwr-off-time = <5000>;
 603                 nvidia,core-pwr-good-time = <3845 3845>;
 604                 nvidia,core-pwr-off-time = <3875>;
 605                 nvidia,sys-clock-req-active-high;
 606                 core-supply = <&vdd_core>;
 607
 608                 /* Set SLEEP MODE bit in SUPPLYENE register of TPS658643 PMIC */
 609                 i2c-thermtrip {
 610                         nvidia,i2c-controller-id = <3>;
 611                         nvidia,bus-addr = <0x34>;
 612                         nvidia,reg-addr = <0x14>;
 613                         nvidia,reg-data = <0x8>;
 614                 };
 615         };
 616
 617         memory-controller@7000f400 {
 618                 emc-table@83250 {
 619                         reg = <83250>;
 620                         compatible = "nvidia,tegra20-emc-table";
 621                         clock-frequency = <83250>;
 622                         nvidia,emc-registers =   <0x00000005 0x00000011
 623                                 0x00000004 0x00000002 0x00000004 0x00000004
 624                                 0x00000001 0x0000000a 0x00000002 0x00000002
 625                                 0x00000001 0x00000001 0x00000003 0x00000004
 626                                 0x00000003 0x00000009 0x0000000c 0x0000025f
 627                                 0x00000000 0x00000003 0x00000003 0x00000002
 628                                 0x00000002 0x00000001 0x00000008 0x000000c8
 629                                 0x00000003 0x00000005 0x00000003 0x0000000c
 630                                 0x00000002 0x00000000 0x00000000 0x00000002
 631                                 0x00000000 0x00000000 0x00000083 0x00520006
 632                                 0x00000010 0x00000008 0x00000000 0x00000000
 633                                 0x00000000 0x00000000 0x00000000 0x00000000>;
 634                 };
 635                 emc-table@133200 {
 636                         reg = <133200>;
 637                         compatible = "nvidia,tegra20-emc-table";
 638                         clock-frequency = <133200>;
 639                         nvidia,emc-registers =   <0x00000008 0x00000019
 640                                 0x00000006 0x00000002 0x00000004 0x00000004
 641                                 0x00000001 0x0000000a 0x00000002 0x00000002
 642                                 0x00000002 0x00000001 0x00000003 0x00000004
 643                                 0x00000003 0x00000009 0x0000000c 0x0000039f
 644                                 0x00000000 0x00000003 0x00000003 0x00000002
 645                                 0x00000002 0x00000001 0x00000008 0x000000c8
 646                                 0x00000003 0x00000007 0x00000003 0x0000000c
 647                                 0x00000002 0x00000000 0x00000000 0x00000002
 648                                 0x00000000 0x00000000 0x00000083 0x00510006
 649                                 0x00000010 0x00000008 0x00000000 0x00000000
 650                                 0x00000000 0x00000000 0x00000000 0x00000000>;
 651                 };
 652                 emc-table@166500 {
 653                         reg = <166500>;
 654                         compatible = "nvidia,tegra20-emc-table";
 655                         clock-frequency = <166500>;
 656                         nvidia,emc-registers =   <0x0000000a 0x00000021
 657                                 0x00000008 0x00000003 0x00000004 0x00000004
 658                                 0x00000002 0x0000000a 0x00000003 0x00000003
 659                                 0x00000002 0x00000001 0x00000003 0x00000004
 660                                 0x00000003 0x00000009 0x0000000c 0x000004df
 661                                 0x00000000 0x00000003 0x00000003 0x00000003
 662                                 0x00000003 0x00000001 0x00000009 0x000000c8
 663                                 0x00000003 0x00000009 0x00000004 0x0000000c
 664                                 0x00000002 0x00000000 0x00000000 0x00000002
 665                                 0x00000000 0x00000000 0x00000083 0x004f0006
 666                                 0x00000010 0x00000008 0x00000000 0x00000000
 667                                 0x00000000 0x00000000 0x00000000 0x00000000>;
 668                 };
 669                 emc-table@333000 {
 670                         reg = <333000>;
 671                         compatible = "nvidia,tegra20-emc-table";
 672                         clock-frequency = <333000>;
 673                         nvidia,emc-registers =   <0x00000014 0x00000041
 674                                 0x0000000f 0x00000005 0x00000004 0x00000005
 675                                 0x00000003 0x0000000a 0x00000005 0x00000005
 676                                 0x00000004 0x00000001 0x00000003 0x00000004
 677                                 0x00000003 0x00000009 0x0000000c 0x000009ff
 678                                 0x00000000 0x00000003 0x00000003 0x00000005
 679                                 0x00000005 0x00000001 0x0000000e 0x000000c8
 680                                 0x00000003 0x00000011 0x00000006 0x0000000c
 681                                 0x00000002 0x00000000 0x00000000 0x00000002
 682                                 0x00000000 0x00000000 0x00000083 0x00380006
 683                                 0x00000010 0x00000008 0x00000000 0x00000000
 684                                 0x00000000 0x00000000 0x00000000 0x00000000>;
 685                 };
 686         };
 687
 688         /* EHCI instance 1: ULPI PHY -> AX88772B (On-module) */
 689         usb@c5004000 {
 690                 status = "okay";
 691                 #address-cells = <1>;
 692                 #size-cells = <0>;
 693
 694                 ethernet@1 {
 695                         compatible = "usbb95,772b";
 696                         reg = <1>;
 697                         local-mac-address = [00 00 00 00 00 00];
 698                 };
 699         };
 700
 701         usb-phy@c5004000 {
 702                 status = "okay";
 703                 nvidia,phy-reset-gpio =
 704                         <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
 705                 vbus-supply = <&reg_lan_v_bus>;
 706         };
 707
 708         clk32k_in: xtal3 {
 709                 compatible = "fixed-clock";
 710                 #clock-cells = <0>;
 711                 clock-frequency = <32768>;
 712         };
 713
 714         reg_lan_v_bus: regulator-lan-v-bus {
 715                 compatible = "regulator-fixed";
 716                 regulator-name = "LAN_V_BUS";
 717                 regulator-min-microvolt = <5000000>;
 718                 regulator-max-microvolt = <5000000>;
 719                 enable-active-high;
 720                 gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
 721         };
 722
 723         reg_module_3v3: regulator-module-3v3 {
 724                 compatible = "regulator-fixed";
 725                 regulator-name = "+V3.3";
 726                 regulator-min-microvolt = <3300000>;
 727                 regulator-max-microvolt = <3300000>;
 728                 regulator-always-on;
 729         };
 730
 731         sound {
 732                 compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
 733                              "nvidia,tegra-audio-wm9712";
 734                 nvidia,model = "Toradex Colibri T20";
 735                 nvidia,audio-routing =
 736                         "Headphone", "HPOUTL",
 737                         "Headphone", "HPOUTR",
 738                         "LineIn", "LINEINL",
 739                         "LineIn", "LINEINR",
 740                         "Mic", "MIC1";
 741                 nvidia,ac97-controller = <&tegra_ac97>;
 742                 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
 743                          <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
 744                          <&tegra_car TEGRA20_CLK_CDEV1>;
 745                 clock-names = "pll_a", "pll_a_out0", "mclk";
 746         };
 747 };
 748
 749 &emc_icc_dvfs_opp_table {
 750         /delete-node/ opp-760000000;
 751 };
 752
 753 &gpio {
 754         lan-reset-n-hog {
 755                 gpio-hog;
 756                 gpios = <TEGRA_GPIO(V, 4) GPIO_ACTIVE_HIGH>;
 757                 output-high;
 758                 line-name = "LAN_RESET#";
 759         };
 760
 761         /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */
 762         npwe-hog {
 763                 gpio-hog;
 764                 gpios = <TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
 765                 output-high;
 766                 line-name = "Tri-state nPWE";
 767         };
 768
 769         /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */
 770         rdnwr-hog {
 771                 gpio-hog;
 772                 gpios = <TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>;
 773                 output-low;
 774                 line-name = "Not tri-state RDnWR";
 775         };
 776 };