GNU Linux-libre 4.19.264-gnu1
[releases.git] / arch / arm / boot / dts / tegra124.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9
10 / {
11         compatible = "nvidia,tegra124";
12         interrupt-parent = <&lic>;
13         #address-cells = <2>;
14         #size-cells = <2>;
15
16         memory@80000000 {
17                 device_type = "memory";
18                 reg = <0x0 0x80000000 0x0 0x0>;
19         };
20
21         pcie@1003000 {
22                 compatible = "nvidia,tegra124-pcie";
23                 device_type = "pci";
24                 reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
25                        0x0 0x01003800 0x0 0x00000800   /* AFI registers */
26                        0x0 0x02000000 0x0 0x10000000>; /* configuration space */
27                 reg-names = "pads", "afi", "cs";
28                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
29                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
30                 interrupt-names = "intr", "msi";
31
32                 #interrupt-cells = <1>;
33                 interrupt-map-mask = <0 0 0 0>;
34                 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
35
36                 bus-range = <0x00 0xff>;
37                 #address-cells = <3>;
38                 #size-cells = <2>;
39
40                 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
41                           0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
42                           0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
43                           0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
44                           0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
45
46                 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
47                          <&tegra_car TEGRA124_CLK_AFI>,
48                          <&tegra_car TEGRA124_CLK_PLL_E>,
49                          <&tegra_car TEGRA124_CLK_CML0>;
50                 clock-names = "pex", "afi", "pll_e", "cml";
51                 resets = <&tegra_car 70>,
52                          <&tegra_car 72>,
53                          <&tegra_car 74>;
54                 reset-names = "pex", "afi", "pcie_x";
55                 status = "disabled";
56
57                 pci@1,0 {
58                         device_type = "pci";
59                         assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
60                         reg = <0x000800 0 0 0 0>;
61                         bus-range = <0x00 0xff>;
62                         status = "disabled";
63
64                         #address-cells = <3>;
65                         #size-cells = <2>;
66                         ranges;
67
68                         nvidia,num-lanes = <2>;
69                 };
70
71                 pci@2,0 {
72                         device_type = "pci";
73                         assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
74                         reg = <0x001000 0 0 0 0>;
75                         bus-range = <0x00 0xff>;
76                         status = "disabled";
77
78                         #address-cells = <3>;
79                         #size-cells = <2>;
80                         ranges;
81
82                         nvidia,num-lanes = <1>;
83                 };
84         };
85
86         host1x@50000000 {
87                 compatible = "nvidia,tegra124-host1x", "simple-bus";
88                 reg = <0x0 0x50000000 0x0 0x00034000>;
89                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
90                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
91                 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
92                 resets = <&tegra_car 28>;
93                 reset-names = "host1x";
94                 iommus = <&mc TEGRA_SWGROUP_HC>;
95
96                 #address-cells = <2>;
97                 #size-cells = <2>;
98
99                 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
100
101                 dc@54200000 {
102                         compatible = "nvidia,tegra124-dc";
103                         reg = <0x0 0x54200000 0x0 0x00040000>;
104                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
105                         clocks = <&tegra_car TEGRA124_CLK_DISP1>,
106                                  <&tegra_car TEGRA124_CLK_PLL_P>;
107                         clock-names = "dc", "parent";
108                         resets = <&tegra_car 27>;
109                         reset-names = "dc";
110
111                         iommus = <&mc TEGRA_SWGROUP_DC>;
112
113                         nvidia,head = <0>;
114                 };
115
116                 dc@54240000 {
117                         compatible = "nvidia,tegra124-dc";
118                         reg = <0x0 0x54240000 0x0 0x00040000>;
119                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
120                         clocks = <&tegra_car TEGRA124_CLK_DISP2>,
121                                  <&tegra_car TEGRA124_CLK_PLL_P>;
122                         clock-names = "dc", "parent";
123                         resets = <&tegra_car 26>;
124                         reset-names = "dc";
125
126                         iommus = <&mc TEGRA_SWGROUP_DCB>;
127
128                         nvidia,head = <1>;
129                 };
130
131                 hdmi: hdmi@54280000 {
132                         compatible = "nvidia,tegra124-hdmi";
133                         reg = <0x0 0x54280000 0x0 0x00040000>;
134                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
135                         clocks = <&tegra_car TEGRA124_CLK_HDMI>,
136                                  <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
137                         clock-names = "hdmi", "parent";
138                         resets = <&tegra_car 51>;
139                         reset-names = "hdmi";
140                         status = "disabled";
141                 };
142
143                 sor@54540000 {
144                         compatible = "nvidia,tegra124-sor";
145                         reg = <0x0 0x54540000 0x0 0x00040000>;
146                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
147                         clocks = <&tegra_car TEGRA124_CLK_SOR0>,
148                                  <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
149                                  <&tegra_car TEGRA124_CLK_PLL_DP>,
150                                  <&tegra_car TEGRA124_CLK_CLK_M>;
151                         clock-names = "sor", "parent", "dp", "safe";
152                         resets = <&tegra_car 182>;
153                         reset-names = "sor";
154                         status = "disabled";
155                 };
156
157                 dpaux: dpaux@545c0000 {
158                         compatible = "nvidia,tegra124-dpaux";
159                         reg = <0x0 0x545c0000 0x0 0x00040000>;
160                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
161                         clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
162                                  <&tegra_car TEGRA124_CLK_PLL_DP>;
163                         clock-names = "dpaux", "parent";
164                         resets = <&tegra_car 181>;
165                         reset-names = "dpaux";
166                         status = "disabled";
167                 };
168         };
169
170         gic: interrupt-controller@50041000 {
171                 compatible = "arm,cortex-a15-gic";
172                 #interrupt-cells = <3>;
173                 interrupt-controller;
174                 reg = <0x0 0x50041000 0x0 0x1000>,
175                       <0x0 0x50042000 0x0 0x1000>,
176                       <0x0 0x50044000 0x0 0x2000>,
177                       <0x0 0x50046000 0x0 0x2000>;
178                 interrupts = <GIC_PPI 9
179                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
180                 interrupt-parent = <&gic>;
181         };
182
183         /*
184          * Please keep the following 0, notation in place as a former mainline
185          * U-Boot version was looking for that particular notation in order to
186          * perform required fix-ups on that GPU node.
187          */
188         gpu@0,57000000 {
189                 compatible = "nvidia,gk20a";
190                 reg = <0x0 0x57000000 0x0 0x01000000>,
191                       <0x0 0x58000000 0x0 0x01000000>;
192                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
193                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
194                 interrupt-names = "stall", "nonstall";
195                 clocks = <&tegra_car TEGRA124_CLK_GPU>,
196                          <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
197                 clock-names = "gpu", "pwr";
198                 resets = <&tegra_car 184>;
199                 reset-names = "gpu";
200
201                 iommus = <&mc TEGRA_SWGROUP_GPU>;
202
203                 status = "disabled";
204         };
205
206         lic: interrupt-controller@60004000 {
207                 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
208                 reg = <0x0 0x60004000 0x0 0x100>,
209                       <0x0 0x60004100 0x0 0x100>,
210                       <0x0 0x60004200 0x0 0x100>,
211                       <0x0 0x60004300 0x0 0x100>,
212                       <0x0 0x60004400 0x0 0x100>;
213                 interrupt-controller;
214                 #interrupt-cells = <3>;
215                 interrupt-parent = <&gic>;
216         };
217
218         timer@60005000 {
219                 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
220                 reg = <0x0 0x60005000 0x0 0x400>;
221                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
222                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
223                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
224                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
225                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
226                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
227                 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
228         };
229
230         tegra_car: clock@60006000 {
231                 compatible = "nvidia,tegra124-car";
232                 reg = <0x0 0x60006000 0x0 0x1000>;
233                 #clock-cells = <1>;
234                 #reset-cells = <1>;
235                 nvidia,external-memory-controller = <&emc>;
236         };
237
238         flow-controller@60007000 {
239                 compatible = "nvidia,tegra124-flowctrl";
240                 reg = <0x0 0x60007000 0x0 0x1000>;
241         };
242
243         actmon@6000c800 {
244                 compatible = "nvidia,tegra124-actmon";
245                 reg = <0x0 0x6000c800 0x0 0x400>;
246                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
247                 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
248                          <&tegra_car TEGRA124_CLK_EMC>;
249                 clock-names = "actmon", "emc";
250                 resets = <&tegra_car 119>;
251                 reset-names = "actmon";
252         };
253
254         gpio: gpio@6000d000 {
255                 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
256                 reg = <0x0 0x6000d000 0x0 0x1000>;
257                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
258                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
259                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
260                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
261                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
262                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
263                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
264                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
265                 #gpio-cells = <2>;
266                 gpio-controller;
267                 #interrupt-cells = <2>;
268                 interrupt-controller;
269                 /*
270                 gpio-ranges = <&pinmux 0 0 251>;
271                 */
272         };
273
274         apbdma: dma@60020000 {
275                 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
276                 reg = <0x0 0x60020000 0x0 0x1400>;
277                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
278                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
279                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
280                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
281                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
282                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
283                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
284                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
285                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
286                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
287                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
288                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
289                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
290                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
291                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
292                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
293                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
294                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
295                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
296                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
297                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
298                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
299                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
300                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
301                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
302                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
303                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
304                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
305                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
306                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
307                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
308                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
309                 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
310                 resets = <&tegra_car 34>;
311                 reset-names = "dma";
312                 #dma-cells = <1>;
313         };
314
315         apbmisc@70000800 {
316                 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
317                 reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
318                       <0x0 0x7000e864 0x0 0x04>;   /* Strapping options */
319         };
320
321         pinmux: pinmux@70000868 {
322                 compatible = "nvidia,tegra124-pinmux";
323                 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
324                       <0x0 0x70003000 0x0 0x434>, /* Mux registers */
325                       <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
326         };
327
328         /*
329          * There are two serial driver i.e. 8250 based simple serial
330          * driver and APB DMA based serial driver for higher baudrate
331          * and performace. To enable the 8250 based driver, the compatible
332          * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
333          * the APB DMA based serial driver, the compatible is
334          * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
335          */
336         uarta: serial@70006000 {
337                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
338                 reg = <0x0 0x70006000 0x0 0x40>;
339                 reg-shift = <2>;
340                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
341                 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
342                 resets = <&tegra_car 6>;
343                 reset-names = "serial";
344                 dmas = <&apbdma 8>, <&apbdma 8>;
345                 dma-names = "rx", "tx";
346                 status = "disabled";
347         };
348
349         uartb: serial@70006040 {
350                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
351                 reg = <0x0 0x70006040 0x0 0x40>;
352                 reg-shift = <2>;
353                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
354                 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
355                 resets = <&tegra_car 7>;
356                 reset-names = "serial";
357                 dmas = <&apbdma 9>, <&apbdma 9>;
358                 dma-names = "rx", "tx";
359                 status = "disabled";
360         };
361
362         uartc: serial@70006200 {
363                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
364                 reg = <0x0 0x70006200 0x0 0x40>;
365                 reg-shift = <2>;
366                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
367                 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
368                 resets = <&tegra_car 55>;
369                 reset-names = "serial";
370                 dmas = <&apbdma 10>, <&apbdma 10>;
371                 dma-names = "rx", "tx";
372                 status = "disabled";
373         };
374
375         uartd: serial@70006300 {
376                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
377                 reg = <0x0 0x70006300 0x0 0x40>;
378                 reg-shift = <2>;
379                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
380                 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
381                 resets = <&tegra_car 65>;
382                 reset-names = "serial";
383                 dmas = <&apbdma 19>, <&apbdma 19>;
384                 dma-names = "rx", "tx";
385                 status = "disabled";
386         };
387
388         pwm: pwm@7000a000 {
389                 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
390                 reg = <0x0 0x7000a000 0x0 0x100>;
391                 #pwm-cells = <2>;
392                 clocks = <&tegra_car TEGRA124_CLK_PWM>;
393                 resets = <&tegra_car 17>;
394                 reset-names = "pwm";
395                 status = "disabled";
396         };
397
398         i2c@7000c000 {
399                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
400                 reg = <0x0 0x7000c000 0x0 0x100>;
401                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
402                 #address-cells = <1>;
403                 #size-cells = <0>;
404                 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
405                 clock-names = "div-clk";
406                 resets = <&tegra_car 12>;
407                 reset-names = "i2c";
408                 dmas = <&apbdma 21>, <&apbdma 21>;
409                 dma-names = "rx", "tx";
410                 status = "disabled";
411         };
412
413         i2c@7000c400 {
414                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
415                 reg = <0x0 0x7000c400 0x0 0x100>;
416                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
417                 #address-cells = <1>;
418                 #size-cells = <0>;
419                 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
420                 clock-names = "div-clk";
421                 resets = <&tegra_car 54>;
422                 reset-names = "i2c";
423                 dmas = <&apbdma 22>, <&apbdma 22>;
424                 dma-names = "rx", "tx";
425                 status = "disabled";
426         };
427
428         i2c@7000c500 {
429                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
430                 reg = <0x0 0x7000c500 0x0 0x100>;
431                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
432                 #address-cells = <1>;
433                 #size-cells = <0>;
434                 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
435                 clock-names = "div-clk";
436                 resets = <&tegra_car 67>;
437                 reset-names = "i2c";
438                 dmas = <&apbdma 23>, <&apbdma 23>;
439                 dma-names = "rx", "tx";
440                 status = "disabled";
441         };
442
443         i2c@7000c700 {
444                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
445                 reg = <0x0 0x7000c700 0x0 0x100>;
446                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
447                 #address-cells = <1>;
448                 #size-cells = <0>;
449                 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
450                 clock-names = "div-clk";
451                 resets = <&tegra_car 103>;
452                 reset-names = "i2c";
453                 dmas = <&apbdma 26>, <&apbdma 26>;
454                 dma-names = "rx", "tx";
455                 status = "disabled";
456         };
457
458         i2c@7000d000 {
459                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
460                 reg = <0x0 0x7000d000 0x0 0x100>;
461                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
462                 #address-cells = <1>;
463                 #size-cells = <0>;
464                 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
465                 clock-names = "div-clk";
466                 resets = <&tegra_car 47>;
467                 reset-names = "i2c";
468                 dmas = <&apbdma 24>, <&apbdma 24>;
469                 dma-names = "rx", "tx";
470                 status = "disabled";
471         };
472
473         i2c@7000d100 {
474                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
475                 reg = <0x0 0x7000d100 0x0 0x100>;
476                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
477                 #address-cells = <1>;
478                 #size-cells = <0>;
479                 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
480                 clock-names = "div-clk";
481                 resets = <&tegra_car 166>;
482                 reset-names = "i2c";
483                 dmas = <&apbdma 30>, <&apbdma 30>;
484                 dma-names = "rx", "tx";
485                 status = "disabled";
486         };
487
488         spi@7000d400 {
489                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
490                 reg = <0x0 0x7000d400 0x0 0x200>;
491                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
492                 #address-cells = <1>;
493                 #size-cells = <0>;
494                 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
495                 clock-names = "spi";
496                 resets = <&tegra_car 41>;
497                 reset-names = "spi";
498                 dmas = <&apbdma 15>, <&apbdma 15>;
499                 dma-names = "rx", "tx";
500                 status = "disabled";
501         };
502
503         spi@7000d600 {
504                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
505                 reg = <0x0 0x7000d600 0x0 0x200>;
506                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
507                 #address-cells = <1>;
508                 #size-cells = <0>;
509                 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
510                 clock-names = "spi";
511                 resets = <&tegra_car 44>;
512                 reset-names = "spi";
513                 dmas = <&apbdma 16>, <&apbdma 16>;
514                 dma-names = "rx", "tx";
515                 status = "disabled";
516         };
517
518         spi@7000d800 {
519                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
520                 reg = <0x0 0x7000d800 0x0 0x200>;
521                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
522                 #address-cells = <1>;
523                 #size-cells = <0>;
524                 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
525                 clock-names = "spi";
526                 resets = <&tegra_car 46>;
527                 reset-names = "spi";
528                 dmas = <&apbdma 17>, <&apbdma 17>;
529                 dma-names = "rx", "tx";
530                 status = "disabled";
531         };
532
533         spi@7000da00 {
534                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
535                 reg = <0x0 0x7000da00 0x0 0x200>;
536                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
537                 #address-cells = <1>;
538                 #size-cells = <0>;
539                 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
540                 clock-names = "spi";
541                 resets = <&tegra_car 68>;
542                 reset-names = "spi";
543                 dmas = <&apbdma 18>, <&apbdma 18>;
544                 dma-names = "rx", "tx";
545                 status = "disabled";
546         };
547
548         spi@7000dc00 {
549                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
550                 reg = <0x0 0x7000dc00 0x0 0x200>;
551                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
552                 #address-cells = <1>;
553                 #size-cells = <0>;
554                 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
555                 clock-names = "spi";
556                 resets = <&tegra_car 104>;
557                 reset-names = "spi";
558                 dmas = <&apbdma 27>, <&apbdma 27>;
559                 dma-names = "rx", "tx";
560                 status = "disabled";
561         };
562
563         spi@7000de00 {
564                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
565                 reg = <0x0 0x7000de00 0x0 0x200>;
566                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
567                 #address-cells = <1>;
568                 #size-cells = <0>;
569                 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
570                 clock-names = "spi";
571                 resets = <&tegra_car 105>;
572                 reset-names = "spi";
573                 dmas = <&apbdma 28>, <&apbdma 28>;
574                 dma-names = "rx", "tx";
575                 status = "disabled";
576         };
577
578         rtc@7000e000 {
579                 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
580                 reg = <0x0 0x7000e000 0x0 0x100>;
581                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
582                 clocks = <&tegra_car TEGRA124_CLK_RTC>;
583         };
584
585         pmc@7000e400 {
586                 compatible = "nvidia,tegra124-pmc";
587                 reg = <0x0 0x7000e400 0x0 0x400>;
588                 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
589                 clock-names = "pclk", "clk32k_in";
590         };
591
592         fuse@7000f800 {
593                 compatible = "nvidia,tegra124-efuse";
594                 reg = <0x0 0x7000f800 0x0 0x400>;
595                 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
596                 clock-names = "fuse";
597                 resets = <&tegra_car 39>;
598                 reset-names = "fuse";
599         };
600
601         mc: memory-controller@70019000 {
602                 compatible = "nvidia,tegra124-mc";
603                 reg = <0x0 0x70019000 0x0 0x1000>;
604                 clocks = <&tegra_car TEGRA124_CLK_MC>;
605                 clock-names = "mc";
606
607                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
608
609                 #iommu-cells = <1>;
610         };
611
612         emc: emc@7001b000 {
613                 compatible = "nvidia,tegra124-emc";
614                 reg = <0x0 0x7001b000 0x0 0x1000>;
615
616                 nvidia,memory-controller = <&mc>;
617         };
618
619         sata@70020000 {
620                 compatible = "nvidia,tegra124-ahci";
621                 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
622                       <0x0 0x70020000 0x0 0x7000>; /* SATA */
623                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
624                 clocks = <&tegra_car TEGRA124_CLK_SATA>,
625                          <&tegra_car TEGRA124_CLK_SATA_OOB>,
626                          <&tegra_car TEGRA124_CLK_CML1>,
627                          <&tegra_car TEGRA124_CLK_PLL_E>;
628                 clock-names = "sata", "sata-oob", "cml1", "pll_e";
629                 resets = <&tegra_car 124>,
630                          <&tegra_car 123>,
631                          <&tegra_car 129>;
632                 reset-names = "sata", "sata-oob", "sata-cold";
633                 status = "disabled";
634         };
635
636         hda@70030000 {
637                 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
638                 reg = <0x0 0x70030000 0x0 0x10000>;
639                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
640                 clocks = <&tegra_car TEGRA124_CLK_HDA>,
641                          <&tegra_car TEGRA124_CLK_HDA2HDMI>,
642                          <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
643                 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
644                 resets = <&tegra_car 125>, /* hda */
645                          <&tegra_car 128>, /* hda2hdmi */
646                          <&tegra_car 111>; /* hda2codec_2x */
647                 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
648                 status = "disabled";
649         };
650
651         usb@70090000 {
652                 compatible = "nvidia,tegra124-xusb";
653                 reg = <0x0 0x70090000 0x0 0x8000>,
654                       <0x0 0x70098000 0x0 0x1000>,
655                       <0x0 0x70099000 0x0 0x1000>;
656                 reg-names = "hcd", "fpci", "ipfs";
657
658                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
659                              <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
660
661                 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
662                          <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
663                          <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
664                          <&tegra_car TEGRA124_CLK_XUSB_SS>,
665                          <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
666                          <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
667                          <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
668                          <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
669                          <&tegra_car TEGRA124_CLK_PLL_U_480M>,
670                          <&tegra_car TEGRA124_CLK_CLK_M>,
671                          <&tegra_car TEGRA124_CLK_PLL_E>;
672                 clock-names = "xusb_host", "xusb_host_src",
673                               "xusb_falcon_src", "xusb_ss",
674                               "xusb_ss_div2", "xusb_ss_src",
675                               "xusb_hs_src", "xusb_fs_src",
676                               "pll_u_480m", "clk_m", "pll_e";
677                 resets = <&tegra_car 89>, <&tegra_car 156>,
678                          <&tegra_car 143>;
679                 reset-names = "xusb_host", "xusb_ss", "xusb_src";
680
681                 nvidia,xusb-padctl = <&padctl>;
682
683                 status = "disabled";
684         };
685
686         padctl: padctl@7009f000 {
687                 compatible = "nvidia,tegra124-xusb-padctl";
688                 reg = <0x0 0x7009f000 0x0 0x1000>;
689                 resets = <&tegra_car 142>;
690                 reset-names = "padctl";
691
692                 pads {
693                         usb2 {
694                                 status = "disabled";
695
696                                 lanes {
697                                         usb2-0 {
698                                                 status = "disabled";
699                                                 #phy-cells = <0>;
700                                         };
701
702                                         usb2-1 {
703                                                 status = "disabled";
704                                                 #phy-cells = <0>;
705                                         };
706
707                                         usb2-2 {
708                                                 status = "disabled";
709                                                 #phy-cells = <0>;
710                                         };
711                                 };
712                         };
713
714                         ulpi {
715                                 status = "disabled";
716
717                                 lanes {
718                                         ulpi-0 {
719                                                 status = "disabled";
720                                                 #phy-cells = <0>;
721                                         };
722                                 };
723                         };
724
725                         hsic {
726                                 status = "disabled";
727
728                                 lanes {
729                                         hsic-0 {
730                                                 status = "disabled";
731                                                 #phy-cells = <0>;
732                                         };
733
734                                         hsic-1 {
735                                                 status = "disabled";
736                                                 #phy-cells = <0>;
737                                         };
738                                 };
739                         };
740
741                         pcie {
742                                 status = "disabled";
743
744                                 lanes {
745                                         pcie-0 {
746                                                 status = "disabled";
747                                                 #phy-cells = <0>;
748                                         };
749
750                                         pcie-1 {
751                                                 status = "disabled";
752                                                 #phy-cells = <0>;
753                                         };
754
755                                         pcie-2 {
756                                                 status = "disabled";
757                                                 #phy-cells = <0>;
758                                         };
759
760                                         pcie-3 {
761                                                 status = "disabled";
762                                                 #phy-cells = <0>;
763                                         };
764
765                                         pcie-4 {
766                                                 status = "disabled";
767                                                 #phy-cells = <0>;
768                                         };
769                                 };
770                         };
771
772                         sata {
773                                 status = "disabled";
774
775                                 lanes {
776                                         sata-0 {
777                                                 status = "disabled";
778                                                 #phy-cells = <0>;
779                                         };
780                                 };
781                         };
782                 };
783
784                 ports {
785                         usb2-0 {
786                                 status = "disabled";
787                         };
788
789                         usb2-1 {
790                                 status = "disabled";
791                         };
792
793                         usb2-2 {
794                                 status = "disabled";
795                         };
796
797                         ulpi-0 {
798                                 status = "disabled";
799                         };
800
801                         hsic-0 {
802                                 status = "disabled";
803                         };
804
805                         hsic-1 {
806                                 status = "disabled";
807                         };
808
809                         usb3-0 {
810                                 status = "disabled";
811                         };
812
813                         usb3-1 {
814                                 status = "disabled";
815                         };
816                 };
817         };
818
819         sdhci@700b0000 {
820                 compatible = "nvidia,tegra124-sdhci";
821                 reg = <0x0 0x700b0000 0x0 0x200>;
822                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
823                 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
824                 resets = <&tegra_car 14>;
825                 reset-names = "sdhci";
826                 status = "disabled";
827         };
828
829         sdhci@700b0200 {
830                 compatible = "nvidia,tegra124-sdhci";
831                 reg = <0x0 0x700b0200 0x0 0x200>;
832                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
833                 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
834                 resets = <&tegra_car 9>;
835                 reset-names = "sdhci";
836                 status = "disabled";
837         };
838
839         sdhci@700b0400 {
840                 compatible = "nvidia,tegra124-sdhci";
841                 reg = <0x0 0x700b0400 0x0 0x200>;
842                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
843                 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
844                 resets = <&tegra_car 69>;
845                 reset-names = "sdhci";
846                 status = "disabled";
847         };
848
849         sdhci@700b0600 {
850                 compatible = "nvidia,tegra124-sdhci";
851                 reg = <0x0 0x700b0600 0x0 0x200>;
852                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
853                 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
854                 resets = <&tegra_car 15>;
855                 reset-names = "sdhci";
856                 status = "disabled";
857         };
858
859         cec@70015000 {
860                 compatible = "nvidia,tegra124-cec";
861                 reg = <0x0 0x70015000 0x0 0x00001000>;
862                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
863                 clocks = <&tegra_car TEGRA124_CLK_CEC>;
864                 clock-names = "cec";
865                 status = "disabled";
866                 hdmi-phandle = <&hdmi>;
867         };
868
869         soctherm: thermal-sensor@700e2000 {
870                 compatible = "nvidia,tegra124-soctherm";
871                 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
872                         0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
873                 reg-names = "soctherm-reg", "car-reg";
874                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
875                 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
876                         <&tegra_car TEGRA124_CLK_SOC_THERM>;
877                 clock-names = "tsensor", "soctherm";
878                 resets = <&tegra_car 78>;
879                 reset-names = "soctherm";
880                 #thermal-sensor-cells = <1>;
881
882                 throttle-cfgs {
883                         throttle_heavy: heavy {
884                                 nvidia,priority = <100>;
885                                 nvidia,cpu-throt-percent = <85>;
886
887                                 #cooling-cells = <2>;
888                         };
889                 };
890         };
891
892         dfll: clock@70110000 {
893                 compatible = "nvidia,tegra124-dfll";
894                 reg = <0 0x70110000 0 0x100>, /* DFLL control */
895                       <0 0x70110000 0 0x100>, /* I2C output control */
896                       <0 0x70110100 0 0x100>, /* Integrated I2C controller */
897                       <0 0x70110200 0 0x100>; /* Look-up table RAM */
898                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
899                 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
900                          <&tegra_car TEGRA124_CLK_DFLL_REF>,
901                          <&tegra_car TEGRA124_CLK_I2C5>;
902                 clock-names = "soc", "ref", "i2c";
903                 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
904                 reset-names = "dvco";
905                 #clock-cells = <0>;
906                 clock-output-names = "dfllCPU_out";
907                 nvidia,sample-rate = <12500>;
908                 nvidia,droop-ctrl = <0x00000f00>;
909                 nvidia,force-mode = <1>;
910                 nvidia,cf = <10>;
911                 nvidia,ci = <0>;
912                 nvidia,cg = <2>;
913                 status = "disabled";
914         };
915
916         ahub@70300000 {
917                 compatible = "nvidia,tegra124-ahub";
918                 reg = <0x0 0x70300000 0x0 0x200>,
919                       <0x0 0x70300800 0x0 0x800>,
920                       <0x0 0x70300200 0x0 0x600>;
921                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
922                 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
923                          <&tegra_car TEGRA124_CLK_APBIF>;
924                 clock-names = "d_audio", "apbif";
925                 resets = <&tegra_car 106>, /* d_audio */
926                          <&tegra_car 107>, /* apbif */
927                          <&tegra_car 30>,  /* i2s0 */
928                          <&tegra_car 11>,  /* i2s1 */
929                          <&tegra_car 18>,  /* i2s2 */
930                          <&tegra_car 101>, /* i2s3 */
931                          <&tegra_car 102>, /* i2s4 */
932                          <&tegra_car 108>, /* dam0 */
933                          <&tegra_car 109>, /* dam1 */
934                          <&tegra_car 110>, /* dam2 */
935                          <&tegra_car 10>,  /* spdif */
936                          <&tegra_car 153>, /* amx */
937                          <&tegra_car 185>, /* amx1 */
938                          <&tegra_car 154>, /* adx */
939                          <&tegra_car 180>, /* adx1 */
940                          <&tegra_car 186>, /* afc0 */
941                          <&tegra_car 187>, /* afc1 */
942                          <&tegra_car 188>, /* afc2 */
943                          <&tegra_car 189>, /* afc3 */
944                          <&tegra_car 190>, /* afc4 */
945                          <&tegra_car 191>; /* afc5 */
946                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
947                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
948                               "spdif", "amx", "amx1", "adx", "adx1",
949                               "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
950                 dmas = <&apbdma 1>, <&apbdma 1>,
951                        <&apbdma 2>, <&apbdma 2>,
952                        <&apbdma 3>, <&apbdma 3>,
953                        <&apbdma 4>, <&apbdma 4>,
954                        <&apbdma 6>, <&apbdma 6>,
955                        <&apbdma 7>, <&apbdma 7>,
956                        <&apbdma 12>, <&apbdma 12>,
957                        <&apbdma 13>, <&apbdma 13>,
958                        <&apbdma 14>, <&apbdma 14>,
959                        <&apbdma 29>, <&apbdma 29>;
960                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
961                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
962                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
963                             "rx9", "tx9";
964                 ranges;
965                 #address-cells = <2>;
966                 #size-cells = <2>;
967
968                 tegra_i2s0: i2s@70301000 {
969                         compatible = "nvidia,tegra124-i2s";
970                         reg = <0x0 0x70301000 0x0 0x100>;
971                         nvidia,ahub-cif-ids = <4 4>;
972                         clocks = <&tegra_car TEGRA124_CLK_I2S0>;
973                         resets = <&tegra_car 30>;
974                         reset-names = "i2s";
975                         status = "disabled";
976                 };
977
978                 tegra_i2s1: i2s@70301100 {
979                         compatible = "nvidia,tegra124-i2s";
980                         reg = <0x0 0x70301100 0x0 0x100>;
981                         nvidia,ahub-cif-ids = <5 5>;
982                         clocks = <&tegra_car TEGRA124_CLK_I2S1>;
983                         resets = <&tegra_car 11>;
984                         reset-names = "i2s";
985                         status = "disabled";
986                 };
987
988                 tegra_i2s2: i2s@70301200 {
989                         compatible = "nvidia,tegra124-i2s";
990                         reg = <0x0 0x70301200 0x0 0x100>;
991                         nvidia,ahub-cif-ids = <6 6>;
992                         clocks = <&tegra_car TEGRA124_CLK_I2S2>;
993                         resets = <&tegra_car 18>;
994                         reset-names = "i2s";
995                         status = "disabled";
996                 };
997
998                 tegra_i2s3: i2s@70301300 {
999                         compatible = "nvidia,tegra124-i2s";
1000                         reg = <0x0 0x70301300 0x0 0x100>;
1001                         nvidia,ahub-cif-ids = <7 7>;
1002                         clocks = <&tegra_car TEGRA124_CLK_I2S3>;
1003                         resets = <&tegra_car 101>;
1004                         reset-names = "i2s";
1005                         status = "disabled";
1006                 };
1007
1008                 tegra_i2s4: i2s@70301400 {
1009                         compatible = "nvidia,tegra124-i2s";
1010                         reg = <0x0 0x70301400 0x0 0x100>;
1011                         nvidia,ahub-cif-ids = <8 8>;
1012                         clocks = <&tegra_car TEGRA124_CLK_I2S4>;
1013                         resets = <&tegra_car 102>;
1014                         reset-names = "i2s";
1015                         status = "disabled";
1016                 };
1017         };
1018
1019         usb@7d000000 {
1020                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1021                 reg = <0x0 0x7d000000 0x0 0x4000>;
1022                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1023                 phy_type = "utmi";
1024                 clocks = <&tegra_car TEGRA124_CLK_USBD>;
1025                 resets = <&tegra_car 22>;
1026                 reset-names = "usb";
1027                 nvidia,phy = <&phy1>;
1028                 status = "disabled";
1029         };
1030
1031         phy1: usb-phy@7d000000 {
1032                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1033                 reg = <0x0 0x7d000000 0x0 0x4000>,
1034                       <0x0 0x7d000000 0x0 0x4000>;
1035                 phy_type = "utmi";
1036                 clocks = <&tegra_car TEGRA124_CLK_USBD>,
1037                          <&tegra_car TEGRA124_CLK_PLL_U>,
1038                          <&tegra_car TEGRA124_CLK_USBD>;
1039                 clock-names = "reg", "pll_u", "utmi-pads";
1040                 resets = <&tegra_car 22>, <&tegra_car 22>;
1041                 reset-names = "usb", "utmi-pads";
1042                 nvidia,hssync-start-delay = <0>;
1043                 nvidia,idle-wait-delay = <17>;
1044                 nvidia,elastic-limit = <16>;
1045                 nvidia,term-range-adj = <6>;
1046                 nvidia,xcvr-setup = <9>;
1047                 nvidia,xcvr-lsfslew = <0>;
1048                 nvidia,xcvr-lsrslew = <3>;
1049                 nvidia,hssquelch-level = <2>;
1050                 nvidia,hsdiscon-level = <5>;
1051                 nvidia,xcvr-hsslew = <12>;
1052                 nvidia,has-utmi-pad-registers;
1053                 status = "disabled";
1054         };
1055
1056         usb@7d004000 {
1057                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1058                 reg = <0x0 0x7d004000 0x0 0x4000>;
1059                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1060                 phy_type = "utmi";
1061                 clocks = <&tegra_car TEGRA124_CLK_USB2>;
1062                 resets = <&tegra_car 58>;
1063                 reset-names = "usb";
1064                 nvidia,phy = <&phy2>;
1065                 status = "disabled";
1066         };
1067
1068         phy2: usb-phy@7d004000 {
1069                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1070                 reg = <0x0 0x7d004000 0x0 0x4000>,
1071                       <0x0 0x7d000000 0x0 0x4000>;
1072                 phy_type = "utmi";
1073                 clocks = <&tegra_car TEGRA124_CLK_USB2>,
1074                          <&tegra_car TEGRA124_CLK_PLL_U>,
1075                          <&tegra_car TEGRA124_CLK_USBD>;
1076                 clock-names = "reg", "pll_u", "utmi-pads";
1077                 resets = <&tegra_car 58>, <&tegra_car 22>;
1078                 reset-names = "usb", "utmi-pads";
1079                 nvidia,hssync-start-delay = <0>;
1080                 nvidia,idle-wait-delay = <17>;
1081                 nvidia,elastic-limit = <16>;
1082                 nvidia,term-range-adj = <6>;
1083                 nvidia,xcvr-setup = <9>;
1084                 nvidia,xcvr-lsfslew = <0>;
1085                 nvidia,xcvr-lsrslew = <3>;
1086                 nvidia,hssquelch-level = <2>;
1087                 nvidia,hsdiscon-level = <5>;
1088                 nvidia,xcvr-hsslew = <12>;
1089                 status = "disabled";
1090         };
1091
1092         usb@7d008000 {
1093                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1094                 reg = <0x0 0x7d008000 0x0 0x4000>;
1095                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1096                 phy_type = "utmi";
1097                 clocks = <&tegra_car TEGRA124_CLK_USB3>;
1098                 resets = <&tegra_car 59>;
1099                 reset-names = "usb";
1100                 nvidia,phy = <&phy3>;
1101                 status = "disabled";
1102         };
1103
1104         phy3: usb-phy@7d008000 {
1105                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1106                 reg = <0x0 0x7d008000 0x0 0x4000>,
1107                       <0x0 0x7d000000 0x0 0x4000>;
1108                 phy_type = "utmi";
1109                 clocks = <&tegra_car TEGRA124_CLK_USB3>,
1110                          <&tegra_car TEGRA124_CLK_PLL_U>,
1111                          <&tegra_car TEGRA124_CLK_USBD>;
1112                 clock-names = "reg", "pll_u", "utmi-pads";
1113                 resets = <&tegra_car 59>, <&tegra_car 22>;
1114                 reset-names = "usb", "utmi-pads";
1115                 nvidia,hssync-start-delay = <0>;
1116                 nvidia,idle-wait-delay = <17>;
1117                 nvidia,elastic-limit = <16>;
1118                 nvidia,term-range-adj = <6>;
1119                 nvidia,xcvr-setup = <9>;
1120                 nvidia,xcvr-lsfslew = <0>;
1121                 nvidia,xcvr-lsrslew = <3>;
1122                 nvidia,hssquelch-level = <2>;
1123                 nvidia,hsdiscon-level = <5>;
1124                 nvidia,xcvr-hsslew = <12>;
1125                 status = "disabled";
1126         };
1127
1128         cpus {
1129                 #address-cells = <1>;
1130                 #size-cells = <0>;
1131
1132                 cpu@0 {
1133                         device_type = "cpu";
1134                         compatible = "arm,cortex-a15";
1135                         reg = <0>;
1136
1137                         clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
1138                                  <&tegra_car TEGRA124_CLK_CCLK_LP>,
1139                                  <&tegra_car TEGRA124_CLK_PLL_X>,
1140                                  <&tegra_car TEGRA124_CLK_PLL_P>,
1141                                  <&dfll>;
1142                         clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
1143                         /* FIXME: what's the actual transition time? */
1144                         clock-latency = <300000>;
1145                 };
1146
1147                 cpu@1 {
1148                         device_type = "cpu";
1149                         compatible = "arm,cortex-a15";
1150                         reg = <1>;
1151                 };
1152
1153                 cpu@2 {
1154                         device_type = "cpu";
1155                         compatible = "arm,cortex-a15";
1156                         reg = <2>;
1157                 };
1158
1159                 cpu@3 {
1160                         device_type = "cpu";
1161                         compatible = "arm,cortex-a15";
1162                         reg = <3>;
1163                 };
1164         };
1165
1166         pmu {
1167                 compatible = "arm,cortex-a15-pmu";
1168                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1169                              <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1170                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1171                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1172                 interrupt-affinity = <&{/cpus/cpu@0}>,
1173                                      <&{/cpus/cpu@1}>,
1174                                      <&{/cpus/cpu@2}>,
1175                                      <&{/cpus/cpu@3}>;
1176         };
1177
1178         thermal-zones {
1179                 cpu {
1180                         polling-delay-passive = <1000>;
1181                         polling-delay = <1000>;
1182
1183                         thermal-sensors =
1184                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1185
1186                         trips {
1187                                 cpu-shutdown-trip {
1188                                         temperature = <103000>;
1189                                         hysteresis = <0>;
1190                                         type = "critical";
1191                                 };
1192                                 cpu_throttle_trip: throttle-trip {
1193                                         temperature = <100000>;
1194                                         hysteresis = <1000>;
1195                                         type = "hot";
1196                                 };
1197                         };
1198
1199                         cooling-maps {
1200                                 map0 {
1201                                         trip = <&cpu_throttle_trip>;
1202                                         cooling-device = <&throttle_heavy 1 1>;
1203                                 };
1204                         };
1205                 };
1206
1207                 mem {
1208                         polling-delay-passive = <1000>;
1209                         polling-delay = <1000>;
1210
1211                         thermal-sensors =
1212                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1213
1214                         trips {
1215                                 mem-shutdown-trip {
1216                                         temperature = <103000>;
1217                                         hysteresis = <0>;
1218                                         type = "critical";
1219                                 };
1220                         };
1221
1222                         cooling-maps {
1223                                 /*
1224                                  * There are currently no cooling maps,
1225                                  * because there are no cooling devices.
1226                                  */
1227                         };
1228                 };
1229
1230                 gpu {
1231                         polling-delay-passive = <1000>;
1232                         polling-delay = <1000>;
1233
1234                         thermal-sensors =
1235                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1236
1237                         trips {
1238                                 gpu-shutdown-trip {
1239                                         temperature = <101000>;
1240                                         hysteresis = <0>;
1241                                         type = "critical";
1242                                 };
1243                                 gpu_throttle_trip: throttle-trip {
1244                                         temperature = <99000>;
1245                                         hysteresis = <1000>;
1246                                         type = "hot";
1247                                 };
1248                         };
1249
1250                         cooling-maps {
1251                                 map0 {
1252                                         trip = <&gpu_throttle_trip>;
1253                                         cooling-device = <&throttle_heavy 1 1>;
1254                                 };
1255                         };
1256                 };
1257
1258                 pllx {
1259                         polling-delay-passive = <1000>;
1260                         polling-delay = <1000>;
1261
1262                         thermal-sensors =
1263                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1264
1265                         trips {
1266                                 pllx-shutdown-trip {
1267                                         temperature = <103000>;
1268                                         hysteresis = <0>;
1269                                         type = "critical";
1270                                 };
1271                         };
1272
1273                         cooling-maps {
1274                                 /*
1275                                  * There are currently no cooling maps,
1276                                  * because there are no cooling devices.
1277                                  */
1278                         };
1279                 };
1280         };
1281
1282         timer {
1283                 compatible = "arm,armv7-timer";
1284                 interrupts = <GIC_PPI 13
1285                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1286                              <GIC_PPI 14
1287                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1288                              <GIC_PPI 11
1289                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1290                              <GIC_PPI 10
1291                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1292                 interrupt-parent = <&gic>;
1293         };
1294 };