2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/sun6i-rtc.h>
44 #include <dt-bindings/clock/sun8i-de2.h>
45 #include <dt-bindings/clock/sun8i-h3-ccu.h>
46 #include <dt-bindings/clock/sun8i-r-ccu.h>
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/reset/sun8i-de2.h>
49 #include <dt-bindings/reset/sun8i-h3-ccu.h>
50 #include <dt-bindings/reset/sun8i-r-ccu.h>
53 interrupt-parent = <&gic>;
63 compatible = "allwinner,simple-framebuffer",
65 allwinner,pipeline = "mixer0-lcd0-hdmi";
66 clocks = <&display_clocks CLK_MIXER0>,
67 <&ccu CLK_TCON0>, <&ccu CLK_HDMI>;
72 compatible = "allwinner,simple-framebuffer",
74 allwinner,pipeline = "mixer1-lcd1-tve";
75 clocks = <&display_clocks CLK_MIXER1>,
88 compatible = "fixed-clock";
89 clock-frequency = <24000000>;
90 clock-accuracy = <50000>;
91 clock-output-names = "osc24M";
96 compatible = "fixed-clock";
97 clock-frequency = <32768>;
98 clock-accuracy = <50000>;
99 clock-output-names = "ext_osc32k";
104 compatible = "allwinner,sun8i-h3-display-engine";
105 allwinner,pipelines = <&mixer0>;
110 compatible = "simple-bus";
111 #address-cells = <1>;
116 display_clocks: clock@1000000 {
117 /* compatible is in per SoC .dtsi file */
118 reg = <0x01000000 0x10000>;
119 clocks = <&ccu CLK_BUS_DE>,
123 resets = <&ccu RST_BUS_DE>;
128 mixer0: mixer@1100000 {
129 compatible = "allwinner,sun8i-h3-de2-mixer-0";
130 reg = <0x01100000 0x100000>;
131 clocks = <&display_clocks CLK_BUS_MIXER0>,
132 <&display_clocks CLK_MIXER0>;
135 resets = <&display_clocks RST_MIXER0>;
138 #address-cells = <1>;
144 mixer0_out_tcon0: endpoint {
145 remote-endpoint = <&tcon0_in_mixer0>;
151 dma: dma-controller@1c02000 {
152 compatible = "allwinner,sun8i-h3-dma";
153 reg = <0x01c02000 0x1000>;
154 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
155 clocks = <&ccu CLK_BUS_DMA>;
156 resets = <&ccu RST_BUS_DMA>;
160 tcon0: lcd-controller@1c0c000 {
161 compatible = "allwinner,sun8i-h3-tcon-tv",
162 "allwinner,sun8i-a83t-tcon-tv";
163 reg = <0x01c0c000 0x1000>;
164 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
166 clock-names = "ahb", "tcon-ch1";
167 resets = <&ccu RST_BUS_TCON0>;
171 #address-cells = <1>;
177 tcon0_in_mixer0: endpoint {
178 remote-endpoint = <&mixer0_out_tcon0>;
183 #address-cells = <1>;
187 tcon0_out_hdmi: endpoint@1 {
189 remote-endpoint = <&hdmi_in_tcon0>;
196 /* compatible and clocks are in per SoC .dtsi file */
197 reg = <0x01c0f000 0x1000>;
198 pinctrl-names = "default";
199 pinctrl-0 = <&mmc0_pins>;
200 resets = <&ccu RST_BUS_MMC0>;
202 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
204 #address-cells = <1>;
209 /* compatible and clocks are in per SoC .dtsi file */
210 reg = <0x01c10000 0x1000>;
211 pinctrl-names = "default";
212 pinctrl-0 = <&mmc1_pins>;
213 resets = <&ccu RST_BUS_MMC1>;
215 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
217 #address-cells = <1>;
222 /* compatible and clocks are in per SoC .dtsi file */
223 reg = <0x01c11000 0x1000>;
224 resets = <&ccu RST_BUS_MMC2>;
226 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
228 #address-cells = <1>;
232 sid: eeprom@1c14000 {
233 /* compatible is in per SoC .dtsi file */
234 reg = <0x1c14000 0x400>;
235 #address-cells = <1>;
238 ths_calibration: thermal-sensor-calibration@34 {
243 msgbox: mailbox@1c17000 {
244 compatible = "allwinner,sun8i-h3-msgbox",
245 "allwinner,sun6i-a31-msgbox";
246 reg = <0x01c17000 0x1000>;
247 clocks = <&ccu CLK_BUS_MSGBOX>;
248 resets = <&ccu RST_BUS_MSGBOX>;
249 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
253 usb_otg: usb@1c19000 {
254 compatible = "allwinner,sun8i-h3-musb";
255 reg = <0x01c19000 0x400>;
256 clocks = <&ccu CLK_BUS_OTG>;
257 resets = <&ccu RST_BUS_OTG>;
258 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
259 interrupt-names = "mc";
262 extcon = <&usbphy 0>;
267 usbphy: phy@1c19400 {
268 compatible = "allwinner,sun8i-h3-usb-phy";
269 reg = <0x01c19400 0x2c>,
274 reg-names = "phy_ctrl",
279 clocks = <&ccu CLK_USB_PHY0>,
283 clock-names = "usb0_phy",
287 resets = <&ccu RST_USB_PHY0>,
291 reset-names = "usb0_reset",
300 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
301 reg = <0x01c1a000 0x100>;
302 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
304 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
309 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
310 reg = <0x01c1a400 0x100>;
311 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
313 <&ccu CLK_USB_OHCI0>;
314 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
319 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
320 reg = <0x01c1b000 0x100>;
321 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
323 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
330 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
331 reg = <0x01c1b400 0x100>;
332 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
334 <&ccu CLK_USB_OHCI1>;
335 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
342 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
343 reg = <0x01c1c000 0x100>;
344 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
346 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
353 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
354 reg = <0x01c1c400 0x100>;
355 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
357 <&ccu CLK_USB_OHCI2>;
358 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
365 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
366 reg = <0x01c1d000 0x100>;
367 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
369 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
376 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
377 reg = <0x01c1d400 0x100>;
378 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
380 <&ccu CLK_USB_OHCI3>;
381 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
388 /* compatible is in per SoC .dtsi file */
389 reg = <0x01c20000 0x400>;
390 clocks = <&osc24M>, <&rtc CLK_OSC32K>;
391 clock-names = "hosc", "losc";
396 pio: pinctrl@1c20800 {
397 /* compatible is in per SoC .dtsi file */
398 reg = <0x01c20800 0x400>;
399 interrupt-parent = <&r_intc>;
400 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
404 clock-names = "apb", "hosc", "losc";
407 interrupt-controller;
408 #interrupt-cells = <3>;
411 pins = "PE0", "PE2", "PE3", "PE4", "PE5",
412 "PE6", "PE7", "PE8", "PE9", "PE10",
417 emac_rgmii_pins: emac-rgmii-pins {
418 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
419 "PD5", "PD7", "PD8", "PD9", "PD10",
420 "PD12", "PD13", "PD15", "PD16", "PD17";
422 drive-strength = <40>;
425 i2c0_pins: i2c0-pins {
426 pins = "PA11", "PA12";
430 i2c1_pins: i2c1-pins {
431 pins = "PA18", "PA19";
435 i2c2_pins: i2c2-pins {
436 pins = "PE12", "PE13";
440 mmc0_pins: mmc0-pins {
441 pins = "PF0", "PF1", "PF2", "PF3",
444 drive-strength = <30>;
448 mmc1_pins: mmc1-pins {
449 pins = "PG0", "PG1", "PG2", "PG3",
452 drive-strength = <30>;
456 mmc2_8bit_pins: mmc2-8bit-pins {
457 pins = "PC5", "PC6", "PC8",
458 "PC9", "PC10", "PC11",
459 "PC12", "PC13", "PC14",
462 drive-strength = <30>;
466 spdif_tx_pin: spdif-tx-pin {
471 spi0_pins: spi0-pins {
472 pins = "PC0", "PC1", "PC2", "PC3";
476 spi1_pins: spi1-pins {
477 pins = "PA15", "PA16", "PA14", "PA13";
481 uart0_pa_pins: uart0-pa-pins {
486 uart1_pins: uart1-pins {
491 uart1_rts_cts_pins: uart1-rts-cts-pins {
496 uart2_pins: uart2-pins {
501 uart2_rts_cts_pins: uart2-rts-cts-pins {
506 uart3_pins: uart3-pins {
507 pins = "PA13", "PA14";
511 uart3_rts_cts_pins: uart3-rts-cts-pins {
512 pins = "PA15", "PA16";
518 compatible = "allwinner,sun8i-a23-timer";
519 reg = <0x01c20c00 0xa0>;
520 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
525 emac: ethernet@1c30000 {
526 compatible = "allwinner,sun8i-h3-emac";
528 reg = <0x01c30000 0x10000>;
529 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
530 interrupt-names = "macirq";
531 resets = <&ccu RST_BUS_EMAC>;
532 reset-names = "stmmaceth";
533 clocks = <&ccu CLK_BUS_EMAC>;
534 clock-names = "stmmaceth";
538 #address-cells = <1>;
540 compatible = "snps,dwmac-mdio";
544 compatible = "allwinner,sun8i-h3-mdio-mux";
545 #address-cells = <1>;
548 mdio-parent-bus = <&mdio>;
549 /* Only one MDIO is usable at the time */
550 internal_mdio: mdio@1 {
551 compatible = "allwinner,sun8i-h3-mdio-internal";
553 #address-cells = <1>;
556 int_mii_phy: ethernet-phy@1 {
557 compatible = "ethernet-phy-ieee802.3-c22";
559 clocks = <&ccu CLK_BUS_EPHY>;
560 resets = <&ccu RST_BUS_EPHY>;
564 external_mdio: mdio@2 {
566 #address-cells = <1>;
572 mbus: dram-controller@1c62000 {
573 /* compatible is in per SoC .dtsi file */
574 reg = <0x01c62000 0x1000>,
576 reg-names = "mbus", "dram";
577 clocks = <&ccu CLK_MBUS>,
580 clock-names = "mbus", "dram", "bus";
581 #address-cells = <1>;
583 dma-ranges = <0x00000000 0x40000000 0xc0000000>;
584 #interconnect-cells = <1>;
588 compatible = "allwinner,sun8i-h3-spi";
589 reg = <0x01c68000 0x1000>;
590 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
591 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
592 clock-names = "ahb", "mod";
593 dmas = <&dma 23>, <&dma 23>;
594 dma-names = "rx", "tx";
595 pinctrl-names = "default";
596 pinctrl-0 = <&spi0_pins>;
597 resets = <&ccu RST_BUS_SPI0>;
599 #address-cells = <1>;
604 compatible = "allwinner,sun8i-h3-spi";
605 reg = <0x01c69000 0x1000>;
606 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
608 clock-names = "ahb", "mod";
609 dmas = <&dma 24>, <&dma 24>;
610 dma-names = "rx", "tx";
611 pinctrl-names = "default";
612 pinctrl-0 = <&spi1_pins>;
613 resets = <&ccu RST_BUS_SPI1>;
615 #address-cells = <1>;
619 wdt0: watchdog@1c20ca0 {
620 compatible = "allwinner,sun6i-a31-wdt";
621 reg = <0x01c20ca0 0x20>;
622 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
626 spdif: spdif@1c21000 {
627 #sound-dai-cells = <0>;
628 compatible = "allwinner,sun8i-h3-spdif";
629 reg = <0x01c21000 0x400>;
630 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
632 resets = <&ccu RST_BUS_SPDIF>;
633 clock-names = "apb", "spdif";
640 compatible = "allwinner,sun8i-h3-pwm";
641 reg = <0x01c21400 0x8>;
648 #sound-dai-cells = <0>;
649 compatible = "allwinner,sun8i-h3-i2s";
650 reg = <0x01c22000 0x400>;
651 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
652 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
653 clock-names = "apb", "mod";
654 dmas = <&dma 3>, <&dma 3>;
655 resets = <&ccu RST_BUS_I2S0>;
656 dma-names = "rx", "tx";
661 #sound-dai-cells = <0>;
662 compatible = "allwinner,sun8i-h3-i2s";
663 reg = <0x01c22400 0x400>;
664 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
665 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
666 clock-names = "apb", "mod";
667 dmas = <&dma 4>, <&dma 4>;
668 resets = <&ccu RST_BUS_I2S1>;
669 dma-names = "rx", "tx";
674 #sound-dai-cells = <0>;
675 compatible = "allwinner,sun8i-h3-i2s";
676 reg = <0x01c22800 0x400>;
677 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
678 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
679 clock-names = "apb", "mod";
681 resets = <&ccu RST_BUS_I2S2>;
686 codec: codec@1c22c00 {
687 #sound-dai-cells = <0>;
688 compatible = "allwinner,sun8i-h3-codec";
689 reg = <0x01c22c00 0x400>;
690 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
692 clock-names = "apb", "codec";
693 resets = <&ccu RST_BUS_CODEC>;
694 dmas = <&dma 15>, <&dma 15>;
695 dma-names = "rx", "tx";
696 allwinner,codec-analog-controls = <&codec_analog>;
700 uart0: serial@1c28000 {
701 compatible = "snps,dw-apb-uart";
702 reg = <0x01c28000 0x400>;
703 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&ccu CLK_BUS_UART0>;
707 resets = <&ccu RST_BUS_UART0>;
708 dmas = <&dma 6>, <&dma 6>;
709 dma-names = "rx", "tx";
713 uart1: serial@1c28400 {
714 compatible = "snps,dw-apb-uart";
715 reg = <0x01c28400 0x400>;
716 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
719 clocks = <&ccu CLK_BUS_UART1>;
720 resets = <&ccu RST_BUS_UART1>;
721 dmas = <&dma 7>, <&dma 7>;
722 dma-names = "rx", "tx";
726 uart2: serial@1c28800 {
727 compatible = "snps,dw-apb-uart";
728 reg = <0x01c28800 0x400>;
729 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
732 clocks = <&ccu CLK_BUS_UART2>;
733 resets = <&ccu RST_BUS_UART2>;
734 dmas = <&dma 8>, <&dma 8>;
735 dma-names = "rx", "tx";
739 uart3: serial@1c28c00 {
740 compatible = "snps,dw-apb-uart";
741 reg = <0x01c28c00 0x400>;
742 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
745 clocks = <&ccu CLK_BUS_UART3>;
746 resets = <&ccu RST_BUS_UART3>;
747 dmas = <&dma 9>, <&dma 9>;
748 dma-names = "rx", "tx";
753 compatible = "allwinner,sun6i-a31-i2c";
754 reg = <0x01c2ac00 0x400>;
755 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
756 clocks = <&ccu CLK_BUS_I2C0>;
757 resets = <&ccu RST_BUS_I2C0>;
758 pinctrl-names = "default";
759 pinctrl-0 = <&i2c0_pins>;
761 #address-cells = <1>;
766 compatible = "allwinner,sun6i-a31-i2c";
767 reg = <0x01c2b000 0x400>;
768 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
769 clocks = <&ccu CLK_BUS_I2C1>;
770 resets = <&ccu RST_BUS_I2C1>;
771 pinctrl-names = "default";
772 pinctrl-0 = <&i2c1_pins>;
774 #address-cells = <1>;
779 compatible = "allwinner,sun6i-a31-i2c";
780 reg = <0x01c2b400 0x400>;
781 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&ccu CLK_BUS_I2C2>;
783 resets = <&ccu RST_BUS_I2C2>;
784 pinctrl-names = "default";
785 pinctrl-0 = <&i2c2_pins>;
787 #address-cells = <1>;
791 gic: interrupt-controller@1c81000 {
792 compatible = "arm,gic-400";
793 reg = <0x01c81000 0x1000>,
797 interrupt-controller;
798 #interrupt-cells = <3>;
799 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
802 csi: camera@1cb0000 {
803 compatible = "allwinner,sun8i-h3-csi";
804 reg = <0x01cb0000 0x1000>;
805 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&ccu CLK_BUS_CSI>,
809 clock-names = "bus", "mod", "ram";
810 resets = <&ccu RST_BUS_CSI>;
811 pinctrl-names = "default";
812 pinctrl-0 = <&csi_pins>;
817 compatible = "allwinner,sun8i-h3-dw-hdmi",
818 "allwinner,sun8i-a83t-dw-hdmi";
819 reg = <0x01ee0000 0x10000>;
821 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
822 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
823 <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>;
824 clock-names = "iahb", "isfr", "tmds", "cec";
825 resets = <&ccu RST_BUS_HDMI1>;
826 reset-names = "ctrl";
832 #address-cells = <1>;
838 hdmi_in_tcon0: endpoint {
839 remote-endpoint = <&tcon0_out_hdmi>;
849 hdmi_phy: hdmi-phy@1ef0000 {
850 compatible = "allwinner,sun8i-h3-hdmi-phy";
851 reg = <0x01ef0000 0x10000>;
852 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
853 <&ccu CLK_PLL_VIDEO>;
854 clock-names = "bus", "mod", "pll-0";
855 resets = <&ccu RST_BUS_HDMI0>;
861 /* compatible is in per SoC .dtsi file */
862 reg = <0x01f00000 0x400>;
863 interrupt-parent = <&r_intc>;
864 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
865 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
866 clock-output-names = "osc32k", "osc32k-out", "iosc";
871 r_intc: interrupt-controller@1f00c00 {
872 compatible = "allwinner,sun8i-h3-r-intc",
873 "allwinner,sun6i-a31-r-intc";
874 interrupt-controller;
875 #interrupt-cells = <3>;
876 reg = <0x01f00c00 0x400>;
877 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
880 r_ccu: clock@1f01400 {
881 compatible = "allwinner,sun8i-h3-r-ccu";
882 reg = <0x01f01400 0x100>;
883 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
884 <&ccu CLK_PLL_PERIPH0>;
885 clock-names = "hosc", "losc", "iosc", "pll-periph";
890 codec_analog: codec-analog@1f015c0 {
891 compatible = "allwinner,sun8i-h3-codec-analog";
892 reg = <0x01f015c0 0x4>;
896 compatible = "allwinner,sun6i-a31-ir";
897 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
898 clock-names = "apb", "ir";
899 resets = <&r_ccu RST_APB0_IR>;
900 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
901 reg = <0x01f02000 0x400>;
906 compatible = "allwinner,sun6i-a31-i2c";
907 reg = <0x01f02400 0x400>;
908 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
909 pinctrl-names = "default";
910 pinctrl-0 = <&r_i2c_pins>;
911 clocks = <&r_ccu CLK_APB0_I2C>;
912 resets = <&r_ccu RST_APB0_I2C>;
914 #address-cells = <1>;
918 r_uart: serial@1f02800 {
919 compatible = "snps,dw-apb-uart";
920 reg = <0x01f02800 0x400>;
921 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
924 clocks = <&r_ccu CLK_APB0_UART>;
925 resets = <&r_ccu RST_APB0_UART>;
926 pinctrl-names = "default";
927 pinctrl-0 = <&r_uart_pins>;
931 r_pio: pinctrl@1f02c00 {
932 compatible = "allwinner,sun8i-h3-r-pinctrl";
933 reg = <0x01f02c00 0x400>;
934 interrupt-parent = <&r_intc>;
935 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
936 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
938 clock-names = "apb", "hosc", "losc";
941 interrupt-controller;
942 #interrupt-cells = <3>;
944 r_ir_rx_pin: r-ir-rx-pin {
946 function = "s_cir_rx";
949 r_i2c_pins: r-i2c-pins {
954 r_pwm_pin: r-pwm-pin {
959 r_uart_pins: r-uart-pins {
966 compatible = "allwinner,sun8i-h3-pwm";
967 reg = <0x01f03800 0x8>;
968 pinctrl-names = "default";
969 pinctrl-0 = <&r_pwm_pin>;