1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for Sunplus SP7021
5 * Copyright (C) 2021 Sunplus Technology Co.
8 #include "sunplus-sp7021.dtsi"
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "sunplus,sp7021-achip", "sunplus,sp7021";
13 model = "Sunplus SP7021 (CA7)";
16 interrupt-parent = <&gic>;
23 compatible = "arm,cortex-a7";
26 clock-frequency = <931000000>;
29 compatible = "arm,cortex-a7";
32 clock-frequency = <931000000>;
35 compatible = "arm,cortex-a7";
38 clock-frequency = <931000000>;
41 compatible = "arm,cortex-a7";
44 clock-frequency = <931000000>;
48 gic: interrupt-controller@9f101000 {
49 compatible = "arm,cortex-a7-gic";
51 #interrupt-cells = <3>;
52 reg = <0x9f101000 0x1000>,
59 compatible = "arm,armv7-timer";
60 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
61 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
62 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
63 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
64 clock-frequency = <XTAL>;
65 arm,cpu-registers-not-fw-configured;
69 compatible = "arm,cortex-a7-pmu";
70 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
72 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
73 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
74 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
78 intc: interrupt-controller@780 {
79 interrupt-parent = <&gic>;
80 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, /* EXT_INT0 */
81 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; /* EXT_INT1 */