2 * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
3 * Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org>
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/clock/sun6i-rtc.h>
46 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
47 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
48 #include <dt-bindings/clock/sun8i-de2.h>
53 interrupt-parent = <&gic>;
61 compatible = "allwinner,simple-framebuffer",
63 allwinner,pipeline = "mixer0-lcd0";
64 clocks = <&display_clocks CLK_MIXER0>,
75 compatible = "arm,cortex-a7";
78 clocks = <&ccu CLK_CPU>;
83 compatible = "allwinner,sun8i-v3s-display-engine";
84 allwinner,pipelines = <&mixer0>;
89 compatible = "arm,armv7-timer";
90 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
93 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
103 compatible = "fixed-clock";
104 clock-frequency = <24000000>;
105 clock-accuracy = <50000>;
106 clock-output-names = "osc24M";
111 compatible = "fixed-clock";
112 clock-frequency = <32768>;
113 clock-accuracy = <50000>;
114 clock-output-names = "ext-osc32k";
119 compatible = "simple-bus";
120 #address-cells = <1>;
124 display_clocks: clock@1000000 {
125 compatible = "allwinner,sun8i-v3s-de2-clk";
126 reg = <0x01000000 0x10000>;
127 clocks = <&ccu CLK_BUS_DE>,
131 resets = <&ccu RST_BUS_DE>;
136 mixer0: mixer@1100000 {
137 compatible = "allwinner,sun8i-v3s-de2-mixer";
138 reg = <0x01100000 0x100000>;
139 clocks = <&display_clocks 0>,
143 resets = <&display_clocks 0>;
146 #address-cells = <1>;
152 mixer0_out_tcon0: endpoint {
153 remote-endpoint = <&tcon0_in_mixer0>;
159 syscon: system-control@1c00000 {
160 compatible = "allwinner,sun8i-v3s-system-control",
161 "allwinner,sun8i-h3-system-control";
162 reg = <0x01c00000 0xd0>;
163 #address-cells = <1>;
168 nmi_intc: interrupt-controller@1c000d0 {
169 compatible = "allwinner,sun8i-v3s-nmi",
170 "allwinner,sun9i-a80-nmi";
171 interrupt-controller;
172 #interrupt-cells = <2>;
173 reg = <0x01c000d0 0x0c>;
174 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
177 dma: dma-controller@1c02000 {
178 compatible = "allwinner,sun8i-v3s-dma";
179 reg = <0x01c02000 0x1000>;
180 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&ccu CLK_BUS_DMA>;
182 resets = <&ccu RST_BUS_DMA>;
186 tcon0: lcd-controller@1c0c000 {
187 compatible = "allwinner,sun8i-v3s-tcon";
188 reg = <0x01c0c000 0x1000>;
189 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&ccu CLK_BUS_TCON0>,
194 clock-output-names = "tcon-pixel-clock";
196 resets = <&ccu RST_BUS_TCON0>;
201 #address-cells = <1>;
207 tcon0_in_mixer0: endpoint {
208 remote-endpoint = <&mixer0_out_tcon0>;
213 #address-cells = <1>;
222 compatible = "allwinner,sun7i-a20-mmc";
223 reg = <0x01c0f000 0x1000>;
224 clocks = <&ccu CLK_BUS_MMC0>,
226 <&ccu CLK_MMC0_OUTPUT>,
227 <&ccu CLK_MMC0_SAMPLE>;
232 resets = <&ccu RST_BUS_MMC0>;
234 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
235 pinctrl-names = "default";
236 pinctrl-0 = <&mmc0_pins>;
238 #address-cells = <1>;
243 compatible = "allwinner,sun7i-a20-mmc";
244 reg = <0x01c10000 0x1000>;
245 clocks = <&ccu CLK_BUS_MMC1>,
247 <&ccu CLK_MMC1_OUTPUT>,
248 <&ccu CLK_MMC1_SAMPLE>;
253 resets = <&ccu RST_BUS_MMC1>;
255 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&mmc1_pins>;
259 #address-cells = <1>;
264 compatible = "allwinner,sun7i-a20-mmc";
265 reg = <0x01c11000 0x1000>;
266 clocks = <&ccu CLK_BUS_MMC2>,
268 <&ccu CLK_MMC2_OUTPUT>,
269 <&ccu CLK_MMC2_SAMPLE>;
274 resets = <&ccu RST_BUS_MMC2>;
276 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
278 #address-cells = <1>;
283 compatible = "allwinner,sun8i-v3s-crypto",
284 "allwinner,sun8i-a33-crypto";
285 reg = <0x01c15000 0x1000>;
286 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
288 clock-names = "ahb", "mod";
289 dmas = <&dma 16>, <&dma 16>;
290 dma-names = "rx", "tx";
291 resets = <&ccu RST_BUS_CE>;
295 usb_otg: usb@1c19000 {
296 compatible = "allwinner,sun8i-h3-musb";
297 reg = <0x01c19000 0x0400>;
298 clocks = <&ccu CLK_BUS_OTG>;
299 resets = <&ccu RST_BUS_OTG>;
300 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
301 interrupt-names = "mc";
304 extcon = <&usbphy 0>;
308 usbphy: phy@1c19400 {
309 compatible = "allwinner,sun8i-v3s-usb-phy";
310 reg = <0x01c19400 0x2c>,
312 reg-names = "phy_ctrl",
314 clocks = <&ccu CLK_USB_PHY0>;
315 clock-names = "usb0_phy";
316 resets = <&ccu RST_USB_PHY0>;
317 reset-names = "usb0_reset";
323 compatible = "allwinner,sun8i-v3s-ccu";
324 reg = <0x01c20000 0x400>;
325 clocks = <&osc24M>, <&rtc CLK_OSC32K>;
326 clock-names = "hosc", "losc";
333 compatible = "allwinner,sun8i-v3-rtc";
334 reg = <0x01c20400 0x54>;
335 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
338 clock-output-names = "osc32k", "osc32k-out";
341 pio: pinctrl@1c20800 {
342 compatible = "allwinner,sun8i-v3s-pinctrl";
343 reg = <0x01c20800 0x400>;
344 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
348 clock-names = "apb", "hosc", "losc";
351 interrupt-controller;
352 #interrupt-cells = <3>;
355 csi0_mclk_pin: csi0-mclk-pin {
357 function = "csi_mipi";
361 csi1_8bit_pins: csi1-8bit-pins {
362 pins = "PE0", "PE2", "PE3", "PE8", "PE9",
363 "PE10", "PE11", "PE12", "PE13", "PE14",
369 csi1_mclk_pin: csi1-mclk-pin {
374 i2c0_pins: i2c0-pins {
380 i2c1_pb_pins: i2c1-pb-pins {
386 i2c1_pe_pins: i2c1-pe-pins {
387 pins = "PE21", "PE22";
391 uart0_pb_pins: uart0-pb-pins {
396 uart2_pins: uart2-pins {
401 mmc0_pins: mmc0-pins {
402 pins = "PF0", "PF1", "PF2", "PF3",
405 drive-strength = <30>;
409 mmc1_pins: mmc1-pins {
410 pins = "PG0", "PG1", "PG2", "PG3",
413 drive-strength = <30>;
417 spi0_pins: spi0-pins {
418 pins = "PC0", "PC1", "PC2", "PC3";
424 compatible = "allwinner,sun8i-v3s-timer";
425 reg = <0x01c20c00 0xa0>;
426 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
427 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
432 wdt0: watchdog@1c20ca0 {
433 compatible = "allwinner,sun6i-a31-wdt";
434 reg = <0x01c20ca0 0x20>;
435 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
440 compatible = "allwinner,sun8i-v3s-pwm",
441 "allwinner,sun7i-a20-pwm";
442 reg = <0x01c21400 0xc>;
448 lradc: lradc@1c22800 {
449 compatible = "allwinner,sun4i-a10-lradc-keys";
450 reg = <0x01c22800 0x400>;
451 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
455 codec: codec@1c22c00 {
456 #sound-dai-cells = <0>;
457 compatible = "allwinner,sun8i-v3s-codec";
458 reg = <0x01c22c00 0x400>;
459 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
461 clock-names = "apb", "codec";
462 resets = <&ccu RST_BUS_CODEC>;
463 dmas = <&dma 15>, <&dma 15>;
464 dma-names = "rx", "tx";
465 allwinner,codec-analog-controls = <&codec_analog>;
469 codec_analog: codec-analog@1c23000 {
470 compatible = "allwinner,sun8i-v3s-codec-analog";
471 reg = <0x01c23000 0x4>;
474 uart0: serial@1c28000 {
475 compatible = "snps,dw-apb-uart";
476 reg = <0x01c28000 0x400>;
477 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
480 clocks = <&ccu CLK_BUS_UART0>;
481 dmas = <&dma 6>, <&dma 6>;
482 dma-names = "rx", "tx";
483 resets = <&ccu RST_BUS_UART0>;
487 uart1: serial@1c28400 {
488 compatible = "snps,dw-apb-uart";
489 reg = <0x01c28400 0x400>;
490 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&ccu CLK_BUS_UART1>;
494 dmas = <&dma 7>, <&dma 7>;
495 dma-names = "rx", "tx";
496 resets = <&ccu RST_BUS_UART1>;
500 uart2: serial@1c28800 {
501 compatible = "snps,dw-apb-uart";
502 reg = <0x01c28800 0x400>;
503 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&ccu CLK_BUS_UART2>;
507 dmas = <&dma 8>, <&dma 8>;
508 dma-names = "rx", "tx";
509 resets = <&ccu RST_BUS_UART2>;
510 pinctrl-0 = <&uart2_pins>;
511 pinctrl-names = "default";
516 compatible = "allwinner,sun6i-a31-i2c";
517 reg = <0x01c2ac00 0x400>;
518 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&ccu CLK_BUS_I2C0>;
520 resets = <&ccu RST_BUS_I2C0>;
521 pinctrl-names = "default";
522 pinctrl-0 = <&i2c0_pins>;
524 #address-cells = <1>;
529 compatible = "allwinner,sun6i-a31-i2c";
530 reg = <0x01c2b000 0x400>;
531 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&ccu CLK_BUS_I2C1>;
533 resets = <&ccu RST_BUS_I2C1>;
535 #address-cells = <1>;
539 emac: ethernet@1c30000 {
540 compatible = "allwinner,sun8i-v3s-emac";
542 reg = <0x01c30000 0x10000>;
543 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
544 interrupt-names = "macirq";
545 resets = <&ccu RST_BUS_EMAC>;
546 reset-names = "stmmaceth";
547 clocks = <&ccu CLK_BUS_EMAC>;
548 clock-names = "stmmaceth";
549 phy-handle = <&int_mii_phy>;
554 #address-cells = <1>;
556 compatible = "snps,dwmac-mdio";
560 compatible = "allwinner,sun8i-h3-mdio-mux";
561 #address-cells = <1>;
564 mdio-parent-bus = <&mdio>;
565 /* Only one MDIO is usable at the time */
566 internal_mdio: mdio@1 {
567 compatible = "allwinner,sun8i-h3-mdio-internal";
569 #address-cells = <1>;
572 int_mii_phy: ethernet-phy@1 {
573 compatible = "ethernet-phy-ieee802.3-c22";
575 clocks = <&ccu CLK_BUS_EPHY>;
576 resets = <&ccu RST_BUS_EPHY>;
583 compatible = "allwinner,sun8i-h3-spi";
584 reg = <0x01c68000 0x1000>;
585 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
587 clock-names = "ahb", "mod";
588 dmas = <&dma 23>, <&dma 23>;
589 dma-names = "rx", "tx";
590 pinctrl-names = "default";
591 pinctrl-0 = <&spi0_pins>;
592 resets = <&ccu RST_BUS_SPI0>;
594 #address-cells = <1>;
598 gic: interrupt-controller@1c81000 {
599 compatible = "arm,gic-400";
600 reg = <0x01c81000 0x1000>,
604 interrupt-controller;
605 #interrupt-cells = <3>;
606 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
609 csi1: camera@1cb4000 {
610 compatible = "allwinner,sun8i-v3s-csi";
611 reg = <0x01cb4000 0x3000>;
612 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&ccu CLK_BUS_CSI>,
614 <&ccu CLK_CSI1_SCLK>,
616 clock-names = "bus", "mod", "ram";
617 resets = <&ccu RST_BUS_CSI>;