arch/arm/boot/dts/sun8i-v3s.dtsi

   1 /*
   2  * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
   3  * Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/interrupt-controller/arm-gic.h>
  45 #include <dt-bindings/clock/sun6i-rtc.h>
  46 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
  47 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
  48 #include <dt-bindings/clock/sun8i-de2.h>
  49
  50 / {
  51         #address-cells = <1>;
  52         #size-cells = <1>;
  53         interrupt-parent = <&gic>;
  54
  55         chosen {
  56                 #address-cells = <1>;
  57                 #size-cells = <1>;
  58                 ranges;
  59
  60                 framebuffer-lcd {
  61                         compatible = "allwinner,simple-framebuffer",
  62                                      "simple-framebuffer";
  63                         allwinner,pipeline = "mixer0-lcd0";
  64                         clocks = <&display_clocks CLK_MIXER0>,
  65                                  <&ccu CLK_TCON0>;
  66                         status = "disabled";
  67                 };
  68         };
  69
  70         cpus {
  71                 #address-cells = <1>;
  72                 #size-cells = <0>;
  73
  74                 cpu@0 {
  75                         compatible = "arm,cortex-a7";
  76                         device_type = "cpu";
  77                         reg = <0>;
  78                         clocks = <&ccu CLK_CPU>;
  79                 };
  80         };
  81
  82         de: display-engine {
  83                 compatible = "allwinner,sun8i-v3s-display-engine";
  84                 allwinner,pipelines = <&mixer0>;
  85                 status = "disabled";
  86         };
  87
  88         timer {
  89                 compatible = "arm,armv7-timer";
  90                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  91                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  92                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  93                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  94         };
  95
  96         clocks {
  97                 #address-cells = <1>;
  98                 #size-cells = <1>;
  99                 ranges;
 100
 101                 osc24M: osc24M_clk {
 102                         #clock-cells = <0>;
 103                         compatible = "fixed-clock";
 104                         clock-frequency = <24000000>;
 105                         clock-accuracy = <50000>;
 106                         clock-output-names = "osc24M";
 107                 };
 108
 109                 osc32k: osc32k_clk {
 110                         #clock-cells = <0>;
 111                         compatible = "fixed-clock";
 112                         clock-frequency = <32768>;
 113                         clock-accuracy = <50000>;
 114                         clock-output-names = "ext-osc32k";
 115                 };
 116         };
 117
 118         soc {
 119                 compatible = "simple-bus";
 120                 #address-cells = <1>;
 121                 #size-cells = <1>;
 122                 ranges;
 123
 124                 display_clocks: clock@1000000 {
 125                         compatible = "allwinner,sun8i-v3s-de2-clk";
 126                         reg = <0x01000000 0x10000>;
 127                         clocks = <&ccu CLK_BUS_DE>,
 128                                  <&ccu CLK_DE>;
 129                         clock-names = "bus",
 130                                       "mod";
 131                         resets = <&ccu RST_BUS_DE>;
 132                         #clock-cells = <1>;
 133                         #reset-cells = <1>;
 134                 };
 135
 136                 mixer0: mixer@1100000 {
 137                         compatible = "allwinner,sun8i-v3s-de2-mixer";
 138                         reg = <0x01100000 0x100000>;
 139                         clocks = <&display_clocks 0>,
 140                                  <&display_clocks 6>;
 141                         clock-names = "bus",
 142                                       "mod";
 143                         resets = <&display_clocks 0>;
 144
 145                         ports {
 146                                 #address-cells = <1>;
 147                                 #size-cells = <0>;
 148
 149                                 mixer0_out: port@1 {
 150                                         reg = <1>;
 151
 152                                         mixer0_out_tcon0: endpoint {
 153                                                 remote-endpoint = <&tcon0_in_mixer0>;
 154                                         };
 155                                 };
 156                         };
 157                 };
 158
 159                 syscon: system-control@1c00000 {
 160                         compatible = "allwinner,sun8i-v3s-system-control",
 161                                      "allwinner,sun8i-h3-system-control";
 162                         reg = <0x01c00000 0xd0>;
 163                         #address-cells = <1>;
 164                         #size-cells = <1>;
 165                         ranges;
 166                 };
 167
 168                 nmi_intc: interrupt-controller@1c000d0 {
 169                         compatible = "allwinner,sun8i-v3s-nmi",
 170                                      "allwinner,sun9i-a80-nmi";
 171                         interrupt-controller;
 172                         #interrupt-cells = <2>;
 173                         reg = <0x01c000d0 0x0c>;
 174                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 175                 };
 176
 177                 dma: dma-controller@1c02000 {
 178                         compatible = "allwinner,sun8i-v3s-dma";
 179                         reg = <0x01c02000 0x1000>;
 180                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 181                         clocks = <&ccu CLK_BUS_DMA>;
 182                         resets = <&ccu RST_BUS_DMA>;
 183                         #dma-cells = <1>;
 184                 };
 185
 186                 tcon0: lcd-controller@1c0c000 {
 187                         compatible = "allwinner,sun8i-v3s-tcon";
 188                         reg = <0x01c0c000 0x1000>;
 189                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 190                         clocks = <&ccu CLK_BUS_TCON0>,
 191                                  <&ccu CLK_TCON0>;
 192                         clock-names = "ahb",
 193                                       "tcon-ch0";
 194                         clock-output-names = "tcon-pixel-clock";
 195                         #clock-cells = <0>;
 196                         resets = <&ccu RST_BUS_TCON0>;
 197                         reset-names = "lcd";
 198                         status = "disabled";
 199
 200                         ports {
 201                                 #address-cells = <1>;
 202                                 #size-cells = <0>;
 203
 204                                 tcon0_in: port@0 {
 205                                         reg = <0>;
 206
 207                                         tcon0_in_mixer0: endpoint {
 208                                                 remote-endpoint = <&mixer0_out_tcon0>;
 209                                         };
 210                                 };
 211
 212                                 tcon0_out: port@1 {
 213                                         #address-cells = <1>;
 214                                         #size-cells = <0>;
 215                                         reg = <1>;
 216                                 };
 217                         };
 218                 };
 219
 220
 221                 mmc0: mmc@1c0f000 {
 222                         compatible = "allwinner,sun7i-a20-mmc";
 223                         reg = <0x01c0f000 0x1000>;
 224                         clocks = <&ccu CLK_BUS_MMC0>,
 225                                  <&ccu CLK_MMC0>,
 226                                  <&ccu CLK_MMC0_OUTPUT>,
 227                                  <&ccu CLK_MMC0_SAMPLE>;
 228                         clock-names = "ahb",
 229                                       "mmc",
 230                                       "output",
 231                                       "sample";
 232                         resets = <&ccu RST_BUS_MMC0>;
 233                         reset-names = "ahb";
 234                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 235                         pinctrl-names = "default";
 236                         pinctrl-0 = <&mmc0_pins>;
 237                         status = "disabled";
 238                         #address-cells = <1>;
 239                         #size-cells = <0>;
 240                 };
 241
 242                 mmc1: mmc@1c10000 {
 243                         compatible = "allwinner,sun7i-a20-mmc";
 244                         reg = <0x01c10000 0x1000>;
 245                         clocks = <&ccu CLK_BUS_MMC1>,
 246                                  <&ccu CLK_MMC1>,
 247                                  <&ccu CLK_MMC1_OUTPUT>,
 248                                  <&ccu CLK_MMC1_SAMPLE>;
 249                         clock-names = "ahb",
 250                                       "mmc",
 251                                       "output",
 252                                       "sample";
 253                         resets = <&ccu RST_BUS_MMC1>;
 254                         reset-names = "ahb";
 255                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 256                         pinctrl-names = "default";
 257                         pinctrl-0 = <&mmc1_pins>;
 258                         status = "disabled";
 259                         #address-cells = <1>;
 260                         #size-cells = <0>;
 261                 };
 262
 263                 mmc2: mmc@1c11000 {
 264                         compatible = "allwinner,sun7i-a20-mmc";
 265                         reg = <0x01c11000 0x1000>;
 266                         clocks = <&ccu CLK_BUS_MMC2>,
 267                                  <&ccu CLK_MMC2>,
 268                                  <&ccu CLK_MMC2_OUTPUT>,
 269                                  <&ccu CLK_MMC2_SAMPLE>;
 270                         clock-names = "ahb",
 271                                       "mmc",
 272                                       "output",
 273                                       "sample";
 274                         resets = <&ccu RST_BUS_MMC2>;
 275                         reset-names = "ahb";
 276                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 277                         status = "disabled";
 278                         #address-cells = <1>;
 279                         #size-cells = <0>;
 280                 };
 281
 282                 crypto@1c15000 {
 283                         compatible = "allwinner,sun8i-v3s-crypto",
 284                                      "allwinner,sun8i-a33-crypto";
 285                         reg = <0x01c15000 0x1000>;
 286                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 287                         clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
 288                         clock-names = "ahb", "mod";
 289                         dmas = <&dma 16>, <&dma 16>;
 290                         dma-names = "rx", "tx";
 291                         resets = <&ccu RST_BUS_CE>;
 292                         reset-names = "ahb";
 293                 };
 294
 295                 usb_otg: usb@1c19000 {
 296                         compatible = "allwinner,sun8i-h3-musb";
 297                         reg = <0x01c19000 0x0400>;
 298                         clocks = <&ccu CLK_BUS_OTG>;
 299                         resets = <&ccu RST_BUS_OTG>;
 300                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 301                         interrupt-names = "mc";
 302                         phys = <&usbphy 0>;
 303                         phy-names = "usb";
 304                         extcon = <&usbphy 0>;
 305                         status = "disabled";
 306                 };
 307
 308                 usbphy: phy@1c19400 {
 309                         compatible = "allwinner,sun8i-v3s-usb-phy";
 310                         reg = <0x01c19400 0x2c>,
 311                               <0x01c1a800 0x4>;
 312                         reg-names = "phy_ctrl",
 313                                     "pmu0";
 314                         clocks = <&ccu CLK_USB_PHY0>;
 315                         clock-names = "usb0_phy";
 316                         resets = <&ccu RST_USB_PHY0>;
 317                         reset-names = "usb0_reset";
 318                         status = "disabled";
 319                         #phy-cells = <1>;
 320                 };
 321
 322                 ccu: clock@1c20000 {
 323                         compatible = "allwinner,sun8i-v3s-ccu";
 324                         reg = <0x01c20000 0x400>;
 325                         clocks = <&osc24M>, <&rtc CLK_OSC32K>;
 326                         clock-names = "hosc", "losc";
 327                         #clock-cells = <1>;
 328                         #reset-cells = <1>;
 329                 };
 330
 331                 rtc: rtc@1c20400 {
 332                         #clock-cells = <1>;
 333                         compatible = "allwinner,sun8i-v3-rtc";
 334                         reg = <0x01c20400 0x54>;
 335                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 336                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 337                         clocks = <&osc32k>;
 338                         clock-output-names = "osc32k", "osc32k-out";
 339                 };
 340
 341                 pio: pinctrl@1c20800 {
 342                         compatible = "allwinner,sun8i-v3s-pinctrl";
 343                         reg = <0x01c20800 0x400>;
 344                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 345                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 346                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
 347                                  <&rtc CLK_OSC32K>;
 348                         clock-names = "apb", "hosc", "losc";
 349                         gpio-controller;
 350                         #gpio-cells = <3>;
 351                         interrupt-controller;
 352                         #interrupt-cells = <3>;
 353
 354                         /omit-if-no-ref/
 355                         csi0_mclk_pin: csi0-mclk-pin {
 356                                 pins = "PE20";
 357                                 function = "csi_mipi";
 358                         };
 359
 360                         /omit-if-no-ref/
 361                         csi1_8bit_pins: csi1-8bit-pins {
 362                                 pins = "PE0", "PE2", "PE3", "PE8", "PE9",
 363                                        "PE10", "PE11", "PE12", "PE13", "PE14",
 364                                        "PE15";
 365                                 function = "csi";
 366                         };
 367
 368                         /omit-if-no-ref/
 369                         csi1_mclk_pin: csi1-mclk-pin {
 370                                 pins = "PE1";
 371                                 function = "csi";
 372                         };
 373
 374                         i2c0_pins: i2c0-pins {
 375                                 pins = "PB6", "PB7";
 376                                 function = "i2c0";
 377                         };
 378
 379                         /omit-if-no-ref/
 380                         i2c1_pb_pins: i2c1-pb-pins {
 381                                 pins = "PB8", "PB9";
 382                                 function = "i2c1";
 383                         };
 384
 385                         /omit-if-no-ref/
 386                         i2c1_pe_pins: i2c1-pe-pins {
 387                                 pins = "PE21", "PE22";
 388                                 function = "i2c1";
 389                         };
 390
 391                         uart0_pb_pins: uart0-pb-pins {
 392                                 pins = "PB8", "PB9";
 393                                 function = "uart0";
 394                         };
 395
 396                         uart2_pins: uart2-pins {
 397                                 pins = "PB0", "PB1";
 398                                 function = "uart2";
 399                         };
 400
 401                         mmc0_pins: mmc0-pins {
 402                                 pins = "PF0", "PF1", "PF2", "PF3",
 403                                        "PF4", "PF5";
 404                                 function = "mmc0";
 405                                 drive-strength = <30>;
 406                                 bias-pull-up;
 407                         };
 408
 409                         mmc1_pins: mmc1-pins {
 410                                 pins = "PG0", "PG1", "PG2", "PG3",
 411                                        "PG4", "PG5";
 412                                 function = "mmc1";
 413                                 drive-strength = <30>;
 414                                 bias-pull-up;
 415                         };
 416
 417                         spi0_pins: spi0-pins {
 418                                 pins = "PC0", "PC1", "PC2", "PC3";
 419                                 function = "spi0";
 420                         };
 421                 };
 422
 423                 timer@1c20c00 {
 424                         compatible = "allwinner,sun8i-v3s-timer";
 425                         reg = <0x01c20c00 0xa0>;
 426                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 427                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 428                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 429                         clocks = <&osc24M>;
 430                 };
 431
 432                 wdt0: watchdog@1c20ca0 {
 433                         compatible = "allwinner,sun6i-a31-wdt";
 434                         reg = <0x01c20ca0 0x20>;
 435                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 436                         clocks = <&osc24M>;
 437                 };
 438
 439                 pwm: pwm@1c21400 {
 440                         compatible = "allwinner,sun8i-v3s-pwm",
 441                                      "allwinner,sun7i-a20-pwm";
 442                         reg = <0x01c21400 0xc>;
 443                         clocks = <&osc24M>;
 444                         #pwm-cells = <3>;
 445                         status = "disabled";
 446                 };
 447
 448                 lradc: lradc@1c22800 {
 449                         compatible = "allwinner,sun4i-a10-lradc-keys";
 450                         reg = <0x01c22800 0x400>;
 451                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 452                         status = "disabled";
 453                 };
 454
 455                 codec: codec@1c22c00 {
 456                         #sound-dai-cells = <0>;
 457                         compatible = "allwinner,sun8i-v3s-codec";
 458                         reg = <0x01c22c00 0x400>;
 459                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 460                         clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
 461                         clock-names = "apb", "codec";
 462                         resets = <&ccu RST_BUS_CODEC>;
 463                         dmas = <&dma 15>, <&dma 15>;
 464                         dma-names = "rx", "tx";
 465                         allwinner,codec-analog-controls = <&codec_analog>;
 466                         status = "disabled";
 467                 };
 468
 469                 codec_analog: codec-analog@1c23000 {
 470                         compatible = "allwinner,sun8i-v3s-codec-analog";
 471                         reg = <0x01c23000 0x4>;
 472                 };
 473
 474                 uart0: serial@1c28000 {
 475                         compatible = "snps,dw-apb-uart";
 476                         reg = <0x01c28000 0x400>;
 477                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 478                         reg-shift = <2>;
 479                         reg-io-width = <4>;
 480                         clocks = <&ccu CLK_BUS_UART0>;
 481                         dmas = <&dma 6>, <&dma 6>;
 482                         dma-names = "rx", "tx";
 483                         resets = <&ccu RST_BUS_UART0>;
 484                         status = "disabled";
 485                 };
 486
 487                 uart1: serial@1c28400 {
 488                         compatible = "snps,dw-apb-uart";
 489                         reg = <0x01c28400 0x400>;
 490                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 491                         reg-shift = <2>;
 492                         reg-io-width = <4>;
 493                         clocks = <&ccu CLK_BUS_UART1>;
 494                         dmas = <&dma 7>, <&dma 7>;
 495                         dma-names = "rx", "tx";
 496                         resets = <&ccu RST_BUS_UART1>;
 497                         status = "disabled";
 498                 };
 499
 500                 uart2: serial@1c28800 {
 501                         compatible = "snps,dw-apb-uart";
 502                         reg = <0x01c28800 0x400>;
 503                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 504                         reg-shift = <2>;
 505                         reg-io-width = <4>;
 506                         clocks = <&ccu CLK_BUS_UART2>;
 507                         dmas = <&dma 8>, <&dma 8>;
 508                         dma-names = "rx", "tx";
 509                         resets = <&ccu RST_BUS_UART2>;
 510                         pinctrl-0 = <&uart2_pins>;
 511                         pinctrl-names = "default";
 512                         status = "disabled";
 513                 };
 514
 515                 i2c0: i2c@1c2ac00 {
 516                         compatible = "allwinner,sun6i-a31-i2c";
 517                         reg = <0x01c2ac00 0x400>;
 518                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 519                         clocks = <&ccu CLK_BUS_I2C0>;
 520                         resets = <&ccu RST_BUS_I2C0>;
 521                         pinctrl-names = "default";
 522                         pinctrl-0 = <&i2c0_pins>;
 523                         status = "disabled";
 524                         #address-cells = <1>;
 525                         #size-cells = <0>;
 526                 };
 527
 528                 i2c1: i2c@1c2b000 {
 529                         compatible = "allwinner,sun6i-a31-i2c";
 530                         reg = <0x01c2b000 0x400>;
 531                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 532                         clocks = <&ccu CLK_BUS_I2C1>;
 533                         resets = <&ccu RST_BUS_I2C1>;
 534                         status = "disabled";
 535                         #address-cells = <1>;
 536                         #size-cells = <0>;
 537                 };
 538
 539                 emac: ethernet@1c30000 {
 540                         compatible = "allwinner,sun8i-v3s-emac";
 541                         syscon = <&syscon>;
 542                         reg = <0x01c30000 0x10000>;
 543                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 544                         interrupt-names = "macirq";
 545                         resets = <&ccu RST_BUS_EMAC>;
 546                         reset-names = "stmmaceth";
 547                         clocks = <&ccu CLK_BUS_EMAC>;
 548                         clock-names = "stmmaceth";
 549                         phy-handle = <&int_mii_phy>;
 550                         phy-mode = "mii";
 551                         status = "disabled";
 552
 553                         mdio: mdio {
 554                                 #address-cells = <1>;
 555                                 #size-cells = <0>;
 556                                 compatible = "snps,dwmac-mdio";
 557                         };
 558
 559                         mdio_mux: mdio-mux {
 560                                 compatible = "allwinner,sun8i-h3-mdio-mux";
 561                                 #address-cells = <1>;
 562                                 #size-cells = <0>;
 563
 564                                 mdio-parent-bus = <&mdio>;
 565                                 /* Only one MDIO is usable at the time */
 566                                 internal_mdio: mdio@1 {
 567                                         compatible = "allwinner,sun8i-h3-mdio-internal";
 568                                         reg = <1>;
 569                                         #address-cells = <1>;
 570                                         #size-cells = <0>;
 571
 572                                         int_mii_phy: ethernet-phy@1 {
 573                                                 compatible = "ethernet-phy-ieee802.3-c22";
 574                                                 reg = <1>;
 575                                                 clocks = <&ccu CLK_BUS_EPHY>;
 576                                                 resets = <&ccu RST_BUS_EPHY>;
 577                                         };
 578                                 };
 579                         };
 580                 };
 581
 582                 spi0: spi@1c68000 {
 583                         compatible = "allwinner,sun8i-h3-spi";
 584                         reg = <0x01c68000 0x1000>;
 585                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 586                         clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
 587                         clock-names = "ahb", "mod";
 588                         dmas = <&dma 23>, <&dma 23>;
 589                         dma-names = "rx", "tx";
 590                         pinctrl-names = "default";
 591                         pinctrl-0 = <&spi0_pins>;
 592                         resets = <&ccu RST_BUS_SPI0>;
 593                         status = "disabled";
 594                         #address-cells = <1>;
 595                         #size-cells = <0>;
 596                 };
 597
 598                 gic: interrupt-controller@1c81000 {
 599                         compatible = "arm,gic-400";
 600                         reg = <0x01c81000 0x1000>,
 601                               <0x01c82000 0x2000>,
 602                               <0x01c84000 0x2000>,
 603                               <0x01c86000 0x2000>;
 604                         interrupt-controller;
 605                         #interrupt-cells = <3>;
 606                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 607                 };
 608
 609                 csi1: camera@1cb4000 {
 610                         compatible = "allwinner,sun8i-v3s-csi";
 611                         reg = <0x01cb4000 0x3000>;
 612                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 613                         clocks = <&ccu CLK_BUS_CSI>,
 614                                  <&ccu CLK_CSI1_SCLK>,
 615                                  <&ccu CLK_DRAM_CSI>;
 616                         clock-names = "bus", "mod", "ram";
 617                         resets = <&ccu RST_BUS_CSI>;
 618                         status = "disabled";
 619                 };
 620         };
 621 };