2 * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
3 * Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org>
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
46 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
47 #include <dt-bindings/clock/sun8i-de2.h>
52 interrupt-parent = <&gic>;
60 compatible = "allwinner,simple-framebuffer",
62 allwinner,pipeline = "mixer0-lcd0";
63 clocks = <&display_clocks CLK_MIXER0>,
74 compatible = "arm,cortex-a7";
77 clocks = <&ccu CLK_CPU>;
82 compatible = "allwinner,sun8i-v3s-display-engine";
83 allwinner,pipelines = <&mixer0>;
88 compatible = "arm,armv7-timer";
89 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
90 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
102 compatible = "fixed-clock";
103 clock-frequency = <24000000>;
104 clock-accuracy = <50000>;
105 clock-output-names = "osc24M";
110 compatible = "fixed-clock";
111 clock-frequency = <32768>;
112 clock-accuracy = <50000>;
113 clock-output-names = "ext-osc32k";
118 compatible = "simple-bus";
119 #address-cells = <1>;
123 display_clocks: clock@1000000 {
124 compatible = "allwinner,sun8i-v3s-de2-clk";
125 reg = <0x01000000 0x10000>;
126 clocks = <&ccu CLK_BUS_DE>,
130 resets = <&ccu RST_BUS_DE>;
135 mixer0: mixer@1100000 {
136 compatible = "allwinner,sun8i-v3s-de2-mixer";
137 reg = <0x01100000 0x100000>;
138 clocks = <&display_clocks 0>,
142 resets = <&display_clocks 0>;
145 #address-cells = <1>;
151 mixer0_out_tcon0: endpoint {
152 remote-endpoint = <&tcon0_in_mixer0>;
158 syscon: system-control@1c00000 {
159 compatible = "allwinner,sun8i-v3s-system-control",
160 "allwinner,sun8i-h3-system-control";
161 reg = <0x01c00000 0xd0>;
162 #address-cells = <1>;
167 nmi_intc: interrupt-controller@1c000d0 {
168 compatible = "allwinner,sun8i-v3s-nmi",
169 "allwinner,sun9i-a80-nmi";
170 interrupt-controller;
171 #interrupt-cells = <2>;
172 reg = <0x01c000d0 0x0c>;
173 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
176 dma: dma-controller@1c02000 {
177 compatible = "allwinner,sun8i-v3s-dma";
178 reg = <0x01c02000 0x1000>;
179 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&ccu CLK_BUS_DMA>;
181 resets = <&ccu RST_BUS_DMA>;
185 tcon0: lcd-controller@1c0c000 {
186 compatible = "allwinner,sun8i-v3s-tcon";
187 reg = <0x01c0c000 0x1000>;
188 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&ccu CLK_BUS_TCON0>,
193 clock-output-names = "tcon-pixel-clock";
195 resets = <&ccu RST_BUS_TCON0>;
200 #address-cells = <1>;
206 tcon0_in_mixer0: endpoint {
207 remote-endpoint = <&mixer0_out_tcon0>;
212 #address-cells = <1>;
221 compatible = "allwinner,sun7i-a20-mmc";
222 reg = <0x01c0f000 0x1000>;
223 clocks = <&ccu CLK_BUS_MMC0>,
225 <&ccu CLK_MMC0_OUTPUT>,
226 <&ccu CLK_MMC0_SAMPLE>;
231 resets = <&ccu RST_BUS_MMC0>;
233 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
234 pinctrl-names = "default";
235 pinctrl-0 = <&mmc0_pins>;
237 #address-cells = <1>;
242 compatible = "allwinner,sun7i-a20-mmc";
243 reg = <0x01c10000 0x1000>;
244 clocks = <&ccu CLK_BUS_MMC1>,
246 <&ccu CLK_MMC1_OUTPUT>,
247 <&ccu CLK_MMC1_SAMPLE>;
252 resets = <&ccu RST_BUS_MMC1>;
254 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
255 pinctrl-names = "default";
256 pinctrl-0 = <&mmc1_pins>;
258 #address-cells = <1>;
263 compatible = "allwinner,sun7i-a20-mmc";
264 reg = <0x01c11000 0x1000>;
265 clocks = <&ccu CLK_BUS_MMC2>,
267 <&ccu CLK_MMC2_OUTPUT>,
268 <&ccu CLK_MMC2_SAMPLE>;
273 resets = <&ccu RST_BUS_MMC2>;
275 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
277 #address-cells = <1>;
282 compatible = "allwinner,sun8i-v3s-crypto",
283 "allwinner,sun8i-a33-crypto";
284 reg = <0x01c15000 0x1000>;
285 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
287 clock-names = "ahb", "mod";
288 dmas = <&dma 16>, <&dma 16>;
289 dma-names = "rx", "tx";
290 resets = <&ccu RST_BUS_CE>;
294 usb_otg: usb@1c19000 {
295 compatible = "allwinner,sun8i-h3-musb";
296 reg = <0x01c19000 0x0400>;
297 clocks = <&ccu CLK_BUS_OTG>;
298 resets = <&ccu RST_BUS_OTG>;
299 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
300 interrupt-names = "mc";
303 extcon = <&usbphy 0>;
307 usbphy: phy@1c19400 {
308 compatible = "allwinner,sun8i-v3s-usb-phy";
309 reg = <0x01c19400 0x2c>,
311 reg-names = "phy_ctrl",
313 clocks = <&ccu CLK_USB_PHY0>;
314 clock-names = "usb0_phy";
315 resets = <&ccu RST_USB_PHY0>;
316 reset-names = "usb0_reset";
322 compatible = "allwinner,sun8i-v3s-ccu";
323 reg = <0x01c20000 0x400>;
324 clocks = <&osc24M>, <&rtc 0>;
325 clock-names = "hosc", "losc";
332 compatible = "allwinner,sun8i-v3-rtc";
333 reg = <0x01c20400 0x54>;
334 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
337 clock-output-names = "osc32k", "osc32k-out";
340 pio: pinctrl@1c20800 {
341 compatible = "allwinner,sun8i-v3s-pinctrl";
342 reg = <0x01c20800 0x400>;
343 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
346 clock-names = "apb", "hosc", "losc";
349 interrupt-controller;
350 #interrupt-cells = <3>;
353 csi0_mclk_pin: csi0-mclk-pin {
355 function = "csi_mipi";
359 csi1_8bit_pins: csi1-8bit-pins {
360 pins = "PE0", "PE2", "PE3", "PE8", "PE9",
361 "PE10", "PE11", "PE12", "PE13", "PE14",
367 csi1_mclk_pin: csi1-mclk-pin {
372 i2c0_pins: i2c0-pins {
378 i2c1_pb_pins: i2c1-pb-pins {
384 i2c1_pe_pins: i2c1-pe-pins {
385 pins = "PE21", "PE22";
389 uart0_pb_pins: uart0-pb-pins {
394 uart2_pins: uart2-pins {
399 mmc0_pins: mmc0-pins {
400 pins = "PF0", "PF1", "PF2", "PF3",
403 drive-strength = <30>;
407 mmc1_pins: mmc1-pins {
408 pins = "PG0", "PG1", "PG2", "PG3",
411 drive-strength = <30>;
415 spi0_pins: spi0-pins {
416 pins = "PC0", "PC1", "PC2", "PC3";
422 compatible = "allwinner,sun8i-v3s-timer";
423 reg = <0x01c20c00 0xa0>;
424 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
425 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
430 wdt0: watchdog@1c20ca0 {
431 compatible = "allwinner,sun6i-a31-wdt";
432 reg = <0x01c20ca0 0x20>;
433 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
438 compatible = "allwinner,sun8i-v3s-pwm",
439 "allwinner,sun7i-a20-pwm";
440 reg = <0x01c21400 0xc>;
446 lradc: lradc@1c22800 {
447 compatible = "allwinner,sun4i-a10-lradc-keys";
448 reg = <0x01c22800 0x400>;
449 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
453 codec: codec@1c22c00 {
454 #sound-dai-cells = <0>;
455 compatible = "allwinner,sun8i-v3s-codec";
456 reg = <0x01c22c00 0x400>;
457 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
459 clock-names = "apb", "codec";
460 resets = <&ccu RST_BUS_CODEC>;
461 dmas = <&dma 15>, <&dma 15>;
462 dma-names = "rx", "tx";
463 allwinner,codec-analog-controls = <&codec_analog>;
467 codec_analog: codec-analog@1c23000 {
468 compatible = "allwinner,sun8i-v3s-codec-analog";
469 reg = <0x01c23000 0x4>;
472 uart0: serial@1c28000 {
473 compatible = "snps,dw-apb-uart";
474 reg = <0x01c28000 0x400>;
475 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
478 clocks = <&ccu CLK_BUS_UART0>;
479 dmas = <&dma 6>, <&dma 6>;
480 dma-names = "rx", "tx";
481 resets = <&ccu RST_BUS_UART0>;
485 uart1: serial@1c28400 {
486 compatible = "snps,dw-apb-uart";
487 reg = <0x01c28400 0x400>;
488 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&ccu CLK_BUS_UART1>;
492 dmas = <&dma 7>, <&dma 7>;
493 dma-names = "rx", "tx";
494 resets = <&ccu RST_BUS_UART1>;
498 uart2: serial@1c28800 {
499 compatible = "snps,dw-apb-uart";
500 reg = <0x01c28800 0x400>;
501 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&ccu CLK_BUS_UART2>;
505 dmas = <&dma 8>, <&dma 8>;
506 dma-names = "rx", "tx";
507 resets = <&ccu RST_BUS_UART2>;
508 pinctrl-0 = <&uart2_pins>;
509 pinctrl-names = "default";
514 compatible = "allwinner,sun6i-a31-i2c";
515 reg = <0x01c2ac00 0x400>;
516 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&ccu CLK_BUS_I2C0>;
518 resets = <&ccu RST_BUS_I2C0>;
519 pinctrl-names = "default";
520 pinctrl-0 = <&i2c0_pins>;
522 #address-cells = <1>;
527 compatible = "allwinner,sun6i-a31-i2c";
528 reg = <0x01c2b000 0x400>;
529 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&ccu CLK_BUS_I2C1>;
531 resets = <&ccu RST_BUS_I2C1>;
533 #address-cells = <1>;
537 emac: ethernet@1c30000 {
538 compatible = "allwinner,sun8i-v3s-emac";
540 reg = <0x01c30000 0x10000>;
541 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
542 interrupt-names = "macirq";
543 resets = <&ccu RST_BUS_EMAC>;
544 reset-names = "stmmaceth";
545 clocks = <&ccu CLK_BUS_EMAC>;
546 clock-names = "stmmaceth";
547 phy-handle = <&int_mii_phy>;
552 #address-cells = <1>;
554 compatible = "snps,dwmac-mdio";
558 compatible = "allwinner,sun8i-h3-mdio-mux";
559 #address-cells = <1>;
562 mdio-parent-bus = <&mdio>;
563 /* Only one MDIO is usable at the time */
564 internal_mdio: mdio@1 {
565 compatible = "allwinner,sun8i-h3-mdio-internal";
567 #address-cells = <1>;
570 int_mii_phy: ethernet-phy@1 {
571 compatible = "ethernet-phy-ieee802.3-c22";
573 clocks = <&ccu CLK_BUS_EPHY>;
574 resets = <&ccu RST_BUS_EPHY>;
581 compatible = "allwinner,sun8i-h3-spi";
582 reg = <0x01c68000 0x1000>;
583 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
585 clock-names = "ahb", "mod";
586 dmas = <&dma 23>, <&dma 23>;
587 dma-names = "rx", "tx";
588 pinctrl-names = "default";
589 pinctrl-0 = <&spi0_pins>;
590 resets = <&ccu RST_BUS_SPI0>;
592 #address-cells = <1>;
596 csi1: camera@1cb4000 {
597 compatible = "allwinner,sun8i-v3s-csi";
598 reg = <0x01cb4000 0x3000>;
599 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&ccu CLK_BUS_CSI>,
601 <&ccu CLK_CSI1_SCLK>,
603 clock-names = "bus", "mod", "ram";
604 resets = <&ccu RST_BUS_CSI>;
608 gic: interrupt-controller@1c81000 {
609 compatible = "arm,gic-400";
610 reg = <0x01c81000 0x1000>,
614 interrupt-controller;
615 #interrupt-cells = <3>;
616 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;