2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include "sunxi-h3-h5.dtsi"
46 cpu0_opp_table: opp_table0 {
47 compatible = "operating-points-v2";
51 opp-hz = /bits/ 64 <648000000>;
52 opp-microvolt = <1040000 1040000 1300000>;
53 clock-latency-ns = <244144>; /* 8 32k periods */
57 opp-hz = /bits/ 64 <816000000>;
58 opp-microvolt = <1100000 1100000 1300000>;
59 clock-latency-ns = <244144>; /* 8 32k periods */
63 opp-hz = /bits/ 64 <1008000000>;
64 opp-microvolt = <1200000 1200000 1300000>;
65 clock-latency-ns = <244144>; /* 8 32k periods */
74 compatible = "arm,cortex-a7";
77 clocks = <&ccu CLK_CPUX>;
79 operating-points-v2 = <&cpu0_opp_table>;
84 compatible = "arm,cortex-a7";
87 clocks = <&ccu CLK_CPUX>;
89 operating-points-v2 = <&cpu0_opp_table>;
94 compatible = "arm,cortex-a7";
97 clocks = <&ccu CLK_CPUX>;
99 operating-points-v2 = <&cpu0_opp_table>;
100 #cooling-cells = <2>;
104 compatible = "arm,cortex-a7";
107 clocks = <&ccu CLK_CPUX>;
109 operating-points-v2 = <&cpu0_opp_table>;
110 #cooling-cells = <2>;
115 compatible = "arm,cortex-a7-pmu";
116 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
117 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
118 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
119 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
120 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
124 compatible = "arm,armv7-timer";
125 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
126 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
127 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
128 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
132 system-control@1c00000 {
133 compatible = "allwinner,sun8i-h3-system-control";
134 reg = <0x01c00000 0x1000>;
135 #address-cells = <1>;
139 sram_c: sram@1d00000 {
140 compatible = "mmio-sram";
141 reg = <0x01d00000 0x80000>;
142 #address-cells = <1>;
144 ranges = <0 0x01d00000 0x80000>;
146 ve_sram: sram-section@0 {
147 compatible = "allwinner,sun8i-h3-sram-c1",
148 "allwinner,sun4i-a10-sram-c1";
149 reg = <0x000000 0x80000>;
155 compatible = "allwinner,sun8i-h3-mali", "arm,mali-400";
156 reg = <0x01c40000 0x10000>;
157 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
164 interrupt-names = "gp",
171 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
172 clock-names = "bus", "core";
173 resets = <&ccu RST_BUS_GPU>;
175 assigned-clocks = <&ccu CLK_GPU>;
176 assigned-clock-rates = <384000000>;
182 compatible = "allwinner,sun8i-h3-ccu";
186 compatible = "allwinner,sun8i-h3-de2-clk";
190 compatible = "allwinner,sun7i-a20-mmc";
191 clocks = <&ccu CLK_BUS_MMC0>,
193 <&ccu CLK_MMC0_OUTPUT>,
194 <&ccu CLK_MMC0_SAMPLE>;
202 compatible = "allwinner,sun7i-a20-mmc";
203 clocks = <&ccu CLK_BUS_MMC1>,
205 <&ccu CLK_MMC1_OUTPUT>,
206 <&ccu CLK_MMC1_SAMPLE>;
214 compatible = "allwinner,sun7i-a20-mmc";
215 clocks = <&ccu CLK_BUS_MMC2>,
217 <&ccu CLK_MMC2_OUTPUT>,
218 <&ccu CLK_MMC2_SAMPLE>;
226 compatible = "allwinner,sun8i-h3-pinctrl";