2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "sun8i-a23-a33.dtsi"
50 compatible = "arm,cortex-a7";
56 compatible = "arm,cortex-a7";
63 compatible = "allwinner,sun8i-a33-display-engine";
64 allwinner,pipelines = <&fe0>;
69 reg = <0x40000000 0x80000000>;
73 tcon0: lcd-controller@01c0c000 {
74 compatible = "allwinner,sun8i-a33-tcon";
75 reg = <0x01c0c000 0x1000>;
76 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
77 clocks = <&ccu CLK_BUS_LCD>,
81 clock-output-names = "tcon-pixel-clock";
82 resets = <&ccu RST_BUS_LCD>;
95 tcon0_in_drc0: endpoint@0 {
97 remote-endpoint = <&drc0_out_tcon0>;
102 #address-cells = <1>;
109 crypto: crypto-engine@01c15000 {
110 compatible = "allwinner,sun4i-a10-crypto";
111 reg = <0x01c15000 0x1000>;
112 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
113 clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
114 clock-names = "ahb", "mod";
115 resets = <&ccu RST_BUS_SS>;
119 fe0: display-frontend@01e00000 {
120 compatible = "allwinner,sun8i-a33-display-frontend";
121 reg = <0x01e00000 0x20000>;
122 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
123 clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
124 <&ccu CLK_DRAM_DE_FE>;
125 clock-names = "ahb", "mod",
127 resets = <&ccu RST_BUS_DE_FE>;
131 #address-cells = <1>;
135 #address-cells = <1>;
139 fe0_out_be0: endpoint@0 {
141 remote-endpoint = <&be0_in_fe0>;
147 be0: display-backend@01e60000 {
148 compatible = "allwinner,sun8i-a33-display-backend";
149 reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
150 reg-names = "be", "sat";
151 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
152 clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
153 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
154 clock-names = "ahb", "mod",
156 resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
157 reset-names = "be", "sat";
158 assigned-clocks = <&ccu CLK_DE_BE>;
159 assigned-clock-rates = <300000000>;
162 #address-cells = <1>;
166 #address-cells = <1>;
170 be0_in_fe0: endpoint@0 {
172 remote-endpoint = <&fe0_out_be0>;
177 #address-cells = <1>;
181 be0_out_drc0: endpoint@0 {
183 remote-endpoint = <&drc0_in_be0>;
190 compatible = "allwinner,sun8i-a33-drc";
191 reg = <0x01e70000 0x10000>;
192 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
193 clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
195 clock-names = "ahb", "mod", "ram";
196 resets = <&ccu RST_BUS_DRC>;
198 assigned-clocks = <&ccu CLK_DRC>;
199 assigned-clock-rates = <300000000>;
202 #address-cells = <1>;
206 #address-cells = <1>;
210 drc0_in_be0: endpoint@0 {
212 remote-endpoint = <&be0_out_drc0>;
217 #address-cells = <1>;
221 drc0_out_tcon0: endpoint@0 {
223 remote-endpoint = <&tcon0_in_drc0>;
232 compatible = "allwinner,sun8i-a33-ccu";
236 compatible = "allwinner,sun8i-a33-pinctrl";
237 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
240 uart0_pins_b: uart0@1 {
241 allwinner,pins = "PB0", "PB1";
242 allwinner,function = "uart0";
243 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
244 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
250 compatible = "allwinner,sun8i-a33-musb";
254 compatible = "allwinner,sun8i-a33-usb-phy";
255 reg = <0x01c19400 0x14>, <0x01c1a800 0x4>;
256 reg-names = "phy_ctrl", "pmu1";