2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun6i-rtc.h>
48 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
49 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
52 interrupt-parent = <&gic>;
61 simplefb_lcd: framebuffer-lcd0 {
62 compatible = "allwinner,simple-framebuffer",
64 allwinner,pipeline = "de_be0-lcd0";
65 clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
66 <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
67 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
73 /* compatible gets set in SoC specific dtsi file */
74 allwinner,pipelines = <&fe0>;
79 compatible = "arm,armv7-timer";
80 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
82 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
83 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
84 clock-frequency = <24000000>;
85 arm,cpu-registers-not-fw-configured;
89 enable-method = "allwinner,sun8i-a23";
94 compatible = "arm,cortex-a7";
100 compatible = "arm,cortex-a7";
107 #address-cells = <1>;
113 compatible = "fixed-clock";
114 clock-frequency = <24000000>;
115 clock-accuracy = <50000>;
116 clock-output-names = "osc24M";
119 ext_osc32k: ext_osc32k_clk {
121 compatible = "fixed-clock";
122 clock-frequency = <32768>;
123 clock-accuracy = <50000>;
124 clock-output-names = "ext-osc32k";
129 compatible = "simple-bus";
130 #address-cells = <1>;
134 system-control@1c00000 {
135 compatible = "allwinner,sun8i-a23-system-control";
136 reg = <0x01c00000 0x30>;
137 #address-cells = <1>;
141 sram_c: sram@1d00000 {
142 compatible = "mmio-sram";
143 reg = <0x01d00000 0x80000>;
144 #address-cells = <1>;
146 ranges = <0 0x01d00000 0x80000>;
148 ve_sram: sram-section@0 {
149 compatible = "allwinner,sun8i-a23-sram-c1",
150 "allwinner,sun4i-a10-sram-c1";
151 reg = <0x000000 0x80000>;
156 dma: dma-controller@1c02000 {
157 compatible = "allwinner,sun8i-a23-dma";
158 reg = <0x01c02000 0x1000>;
159 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&ccu CLK_BUS_DMA>;
161 resets = <&ccu RST_BUS_DMA>;
165 nfc: nand-controller@1c03000 {
166 compatible = "allwinner,sun8i-a23-nand-controller";
167 reg = <0x01c03000 0x1000>;
168 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
169 clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
170 clock-names = "ahb", "mod";
171 resets = <&ccu RST_BUS_NAND>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>;
178 #address-cells = <1>;
182 tcon0: lcd-controller@1c0c000 {
183 /* compatible gets set in SoC specific dtsi file */
184 reg = <0x01c0c000 0x1000>;
185 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&ccu CLK_BUS_LCD>,
193 clock-output-names = "tcon-pixel-clock";
195 resets = <&ccu RST_BUS_LCD>,
202 #address-cells = <1>;
208 tcon0_in_drc0: endpoint {
209 remote-endpoint = <&drc0_out_tcon0>;
220 compatible = "allwinner,sun7i-a20-mmc";
221 reg = <0x01c0f000 0x1000>;
222 clocks = <&ccu CLK_BUS_MMC0>,
224 <&ccu CLK_MMC0_OUTPUT>,
225 <&ccu CLK_MMC0_SAMPLE>;
230 resets = <&ccu RST_BUS_MMC0>;
232 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
233 pinctrl-names = "default";
234 pinctrl-0 = <&mmc0_pins>;
236 #address-cells = <1>;
241 compatible = "allwinner,sun7i-a20-mmc";
242 reg = <0x01c10000 0x1000>;
243 clocks = <&ccu CLK_BUS_MMC1>,
245 <&ccu CLK_MMC1_OUTPUT>,
246 <&ccu CLK_MMC1_SAMPLE>;
251 resets = <&ccu RST_BUS_MMC1>;
253 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
255 #address-cells = <1>;
260 compatible = "allwinner,sun7i-a20-mmc";
261 reg = <0x01c11000 0x1000>;
262 clocks = <&ccu CLK_BUS_MMC2>,
264 <&ccu CLK_MMC2_OUTPUT>,
265 <&ccu CLK_MMC2_SAMPLE>;
270 resets = <&ccu RST_BUS_MMC2>;
272 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
274 #address-cells = <1>;
278 usb_otg: usb@1c19000 {
279 /* compatible gets set in SoC specific dtsi file */
280 reg = <0x01c19000 0x0400>;
281 clocks = <&ccu CLK_BUS_OTG>;
282 resets = <&ccu RST_BUS_OTG>;
283 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
284 interrupt-names = "mc";
287 extcon = <&usbphy 0>;
292 usbphy: phy@1c19400 {
294 * compatible and address regions get set in
295 * SoC specific dtsi file
297 clocks = <&ccu CLK_USB_PHY0>,
299 clock-names = "usb0_phy",
301 resets = <&ccu RST_USB_PHY0>,
303 reset-names = "usb0_reset",
310 compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
311 reg = <0x01c1a000 0x100>;
312 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&ccu CLK_BUS_EHCI>;
314 resets = <&ccu RST_BUS_EHCI>;
321 compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
322 reg = <0x01c1a400 0x100>;
323 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
325 resets = <&ccu RST_BUS_OHCI>;
332 reg = <0x01c20000 0x400>;
333 clocks = <&osc24M>, <&rtc CLK_OSC32K>;
334 clock-names = "hosc", "losc";
339 pio: pinctrl@1c20800 {
340 /* compatible gets set in SoC specific dtsi file */
341 reg = <0x01c20800 0x400>;
342 interrupt-parent = <&r_intc>;
343 /* interrupts get set in SoC specific dtsi file */
344 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
346 clock-names = "apb", "hosc", "losc";
348 interrupt-controller;
349 #interrupt-cells = <3>;
352 i2c0_pins: i2c0-pins {
357 i2c1_pins: i2c1-pins {
362 i2c2_pins: i2c2-pins {
363 pins = "PE12", "PE13";
367 lcd_rgb666_pins: lcd-rgb666-pins {
368 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
369 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
370 "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
371 "PD24", "PD25", "PD26", "PD27";
375 mmc0_pins: mmc0-pins {
376 pins = "PF0", "PF1", "PF2",
379 drive-strength = <30>;
383 mmc1_pg_pins: mmc1-pg-pins {
384 pins = "PG0", "PG1", "PG2",
387 drive-strength = <30>;
391 mmc2_8bit_pins: mmc2-8bit-pins {
392 pins = "PC5", "PC6", "PC8",
393 "PC9", "PC10", "PC11",
394 "PC12", "PC13", "PC14",
397 drive-strength = <30>;
401 nand_pins: nand-pins {
402 pins = "PC0", "PC1", "PC2", "PC5",
403 "PC8", "PC9", "PC10", "PC11",
404 "PC12", "PC13", "PC14", "PC15";
408 nand_cs0_pin: nand-cs0-pin {
414 nand_cs1_pin: nand-cs1-pin {
420 nand_rb0_pin: nand-rb0-pin {
426 nand_rb1_pin: nand-rb1-pin {
437 uart0_pf_pins: uart0-pf-pins {
442 uart1_pg_pins: uart1-pg-pins {
447 uart1_cts_rts_pg_pins: uart1-cts-rts-pg-pins {
454 compatible = "allwinner,sun8i-a23-timer";
455 reg = <0x01c20c00 0xa0>;
456 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
461 wdt0: watchdog@1c20ca0 {
462 compatible = "allwinner,sun6i-a31-wdt";
463 reg = <0x01c20ca0 0x20>;
464 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
469 compatible = "allwinner,sun7i-a20-pwm";
470 reg = <0x01c21400 0xc>;
476 lradc: lradc@1c22800 {
477 compatible = "allwinner,sun4i-a10-lradc-keys";
478 reg = <0x01c22800 0x100>;
479 interrupt-parent = <&r_intc>;
480 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
484 uart0: serial@1c28000 {
485 compatible = "snps,dw-apb-uart";
486 reg = <0x01c28000 0x400>;
487 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&ccu CLK_BUS_UART0>;
491 resets = <&ccu RST_BUS_UART0>;
492 dmas = <&dma 6>, <&dma 6>;
493 dma-names = "rx", "tx";
497 uart1: serial@1c28400 {
498 compatible = "snps,dw-apb-uart";
499 reg = <0x01c28400 0x400>;
500 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&ccu CLK_BUS_UART1>;
504 resets = <&ccu RST_BUS_UART1>;
505 dmas = <&dma 7>, <&dma 7>;
506 dma-names = "rx", "tx";
510 uart2: serial@1c28800 {
511 compatible = "snps,dw-apb-uart";
512 reg = <0x01c28800 0x400>;
513 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&ccu CLK_BUS_UART2>;
517 resets = <&ccu RST_BUS_UART2>;
518 dmas = <&dma 8>, <&dma 8>;
519 dma-names = "rx", "tx";
523 uart3: serial@1c28c00 {
524 compatible = "snps,dw-apb-uart";
525 reg = <0x01c28c00 0x400>;
526 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
529 clocks = <&ccu CLK_BUS_UART3>;
530 resets = <&ccu RST_BUS_UART3>;
531 dmas = <&dma 9>, <&dma 9>;
532 dma-names = "rx", "tx";
536 uart4: serial@1c29000 {
537 compatible = "snps,dw-apb-uart";
538 reg = <0x01c29000 0x400>;
539 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&ccu CLK_BUS_UART4>;
543 resets = <&ccu RST_BUS_UART4>;
544 dmas = <&dma 10>, <&dma 10>;
545 dma-names = "rx", "tx";
550 compatible = "allwinner,sun6i-a31-i2c";
551 reg = <0x01c2ac00 0x400>;
552 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&ccu CLK_BUS_I2C0>;
554 resets = <&ccu RST_BUS_I2C0>;
555 pinctrl-names = "default";
556 pinctrl-0 = <&i2c0_pins>;
558 #address-cells = <1>;
563 compatible = "allwinner,sun6i-a31-i2c";
564 reg = <0x01c2b000 0x400>;
565 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&ccu CLK_BUS_I2C1>;
567 resets = <&ccu RST_BUS_I2C1>;
568 pinctrl-names = "default";
569 pinctrl-0 = <&i2c1_pins>;
571 #address-cells = <1>;
576 compatible = "allwinner,sun6i-a31-i2c";
577 reg = <0x01c2b400 0x400>;
578 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&ccu CLK_BUS_I2C2>;
580 resets = <&ccu RST_BUS_I2C2>;
581 pinctrl-names = "default";
582 pinctrl-0 = <&i2c2_pins>;
584 #address-cells = <1>;
589 compatible = "allwinner,sun8i-a23-mali",
590 "allwinner,sun7i-a20-mali", "arm,mali-400";
591 reg = <0x01c40000 0x10000>;
592 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
599 interrupt-names = "gp",
606 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
607 clock-names = "bus", "core";
608 resets = <&ccu RST_BUS_GPU>;
609 #cooling-cells = <2>;
611 assigned-clocks = <&ccu CLK_GPU>;
612 assigned-clock-rates = <384000000>;
615 gic: interrupt-controller@1c81000 {
616 compatible = "arm,gic-400";
617 reg = <0x01c81000 0x1000>,
621 interrupt-controller;
622 #interrupt-cells = <3>;
623 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
626 fe0: display-frontend@1e00000 {
627 /* compatible gets set in SoC specific dtsi file */
628 reg = <0x01e00000 0x20000>;
629 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
631 <&ccu CLK_DRAM_DE_FE>;
632 clock-names = "ahb", "mod",
634 resets = <&ccu RST_BUS_DE_FE>;
637 #address-cells = <1>;
643 fe0_out_be0: endpoint {
644 remote-endpoint = <&be0_in_fe0>;
650 be0: display-backend@1e60000 {
651 /* compatible gets set in SoC specific dtsi file */
652 reg = <0x01e60000 0x10000>;
653 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
655 <&ccu CLK_DRAM_DE_BE>;
656 clock-names = "ahb", "mod",
658 resets = <&ccu RST_BUS_DE_BE>;
661 #address-cells = <1>;
667 be0_in_fe0: endpoint {
668 remote-endpoint = <&fe0_out_be0>;
675 be0_out_drc0: endpoint {
676 remote-endpoint = <&drc0_in_be0>;
683 /* compatible gets set in SoC specific dtsi file */
684 reg = <0x01e70000 0x10000>;
685 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
688 clock-names = "ahb", "mod", "ram";
689 resets = <&ccu RST_BUS_DRC>;
692 #address-cells = <1>;
698 drc0_in_be0: endpoint {
699 remote-endpoint = <&be0_out_drc0>;
706 drc0_out_tcon0: endpoint {
707 remote-endpoint = <&tcon0_in_drc0>;
714 compatible = "allwinner,sun8i-a23-rtc";
715 reg = <0x01f00000 0x400>;
716 interrupt-parent = <&r_intc>;
717 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
718 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
719 clock-output-names = "osc32k", "osc32k-out";
720 clocks = <&ext_osc32k>;
724 r_intc: interrupt-controller@1f00c00 {
725 compatible = "allwinner,sun6i-a31-r-intc";
726 interrupt-controller;
727 #interrupt-cells = <3>;
728 reg = <0x01f00c00 0x400>;
729 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
733 compatible = "allwinner,sun8i-a23-prcm";
734 reg = <0x01f01400 0x200>;
737 compatible = "fixed-factor-clock";
742 clock-output-names = "ar100";
746 compatible = "fixed-factor-clock";
751 clock-output-names = "ahb0";
755 compatible = "allwinner,sun8i-a23-apb0-clk";
758 clock-output-names = "apb0";
761 apb0_gates: apb0_gates_clk {
762 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
765 clock-output-names = "apb0_pio", "apb0_timer",
766 "apb0_rsb", "apb0_uart",
771 compatible = "allwinner,sun6i-a31-clock-reset";
775 codec_analog: codec-analog {
776 compatible = "allwinner,sun8i-a23-codec-analog";
781 compatible = "allwinner,sun8i-a23-cpuconfig";
782 reg = <0x01f01c00 0x300>;
785 r_uart: serial@1f02800 {
786 compatible = "snps,dw-apb-uart";
787 reg = <0x01f02800 0x400>;
788 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
791 clocks = <&apb0_gates 4>;
792 resets = <&apb0_rst 4>;
797 compatible = "allwinner,sun8i-a23-i2c",
798 "allwinner,sun6i-a31-i2c";
799 reg = <0x01f02400 0x400>;
800 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
801 pinctrl-names = "default";
802 pinctrl-0 = <&r_i2c_pins>;
803 clocks = <&apb0_gates 6>;
804 resets = <&apb0_rst 6>;
806 #address-cells = <1>;
810 r_pio: pinctrl@1f02c00 {
811 compatible = "allwinner,sun8i-a23-r-pinctrl";
812 reg = <0x01f02c00 0x400>;
813 interrupt-parent = <&r_intc>;
814 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
815 clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>;
816 clock-names = "apb", "hosc", "losc";
818 interrupt-controller;
819 #interrupt-cells = <3>;
822 r_i2c_pins: r-i2c-pins {
828 r_rsb_pins: r-rsb-pins {
831 drive-strength = <20>;
835 r_uart_pins_a: r-uart-pins {
842 compatible = "allwinner,sun8i-a23-rsb";
843 reg = <0x01f03400 0x400>;
844 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
845 clocks = <&apb0_gates 3>;
846 clock-frequency = <3000000>;
847 resets = <&apb0_rst 3>;
848 pinctrl-names = "default";
849 pinctrl-0 = <&r_rsb_pins>;
851 #address-cells = <1>;