2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "skeleton.dtsi"
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
49 #include <dt-bindings/dma/sun4i-a10.h>
50 #include <dt-bindings/clock/sun7i-a20-ccu.h>
51 #include <dt-bindings/reset/sun4i-a10-ccu.h>
54 interrupt-parent = <&gic>;
66 compatible = "allwinner,simple-framebuffer",
68 allwinner,pipeline = "de_be0-lcd0-hdmi";
69 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
70 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
71 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
77 compatible = "allwinner,simple-framebuffer",
79 allwinner,pipeline = "de_be0-lcd0";
80 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
81 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
82 <&ccu CLK_DRAM_DE_BE0>;
87 compatible = "allwinner,simple-framebuffer",
89 allwinner,pipeline = "de_be0-lcd0-tve0";
90 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
91 <&ccu CLK_AHB_DE_BE0>,
92 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>,
93 <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>;
103 compatible = "arm,cortex-a7";
106 clocks = <&ccu CLK_CPU>;
107 clock-latency = <244144>; /* 8 32k periods */
118 #cooling-cells = <2>;
122 compatible = "arm,cortex-a7";
125 clocks = <&ccu CLK_CPU>;
126 clock-latency = <244144>; /* 8 32k periods */
137 #cooling-cells = <2>;
144 polling-delay-passive = <250>;
145 polling-delay = <1000>;
146 thermal-sensors = <&rtp>;
150 trip = <&cpu_alert0>;
151 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
156 cpu_alert0: cpu_alert0 {
158 temperature = <75000>;
165 temperature = <100000>;
174 reg = <0x40000000 0x80000000>;
178 compatible = "arm,armv7-timer";
179 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
180 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
181 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
182 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
186 compatible = "arm,cortex-a7-pmu";
187 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
192 #address-cells = <1>;
196 osc24M: clk@1c20050 {
198 compatible = "fixed-clock";
199 clock-frequency = <24000000>;
200 clock-output-names = "osc24M";
205 compatible = "fixed-clock";
206 clock-frequency = <32768>;
207 clock-output-names = "osc32k";
211 * The following two are dummy clocks, placeholders
212 * used in the gmac_tx clock. The gmac driver will
213 * choose one parent depending on the PHY interface
214 * mode, using clk_set_rate auto-reparenting.
216 * The actual TX clock rate is not controlled by the
219 mii_phy_tx_clk: clk@1 {
221 compatible = "fixed-clock";
222 clock-frequency = <25000000>;
223 clock-output-names = "mii_phy_tx";
226 gmac_int_tx_clk: clk@2 {
228 compatible = "fixed-clock";
229 clock-frequency = <125000000>;
230 clock-output-names = "gmac_int_tx";
233 gmac_tx_clk: clk@1c20164 {
235 compatible = "allwinner,sun7i-a20-gmac-clk";
236 reg = <0x01c20164 0x4>;
237 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
238 clock-output-names = "gmac_tx";
244 compatible = "allwinner,sun7i-a20-display-engine";
245 allwinner,pipelines = <&fe0>, <&fe1>;
250 compatible = "simple-bus";
251 #address-cells = <1>;
255 system-control@1c00000 {
256 compatible = "allwinner,sun7i-a20-system-control",
257 "allwinner,sun4i-a10-system-control";
258 reg = <0x01c00000 0x30>;
259 #address-cells = <1>;
264 compatible = "mmio-sram";
265 reg = <0x00000000 0xc000>;
266 #address-cells = <1>;
268 ranges = <0 0x00000000 0xc000>;
270 emac_sram: sram-section@8000 {
271 compatible = "allwinner,sun7i-a20-sram-a3-a4",
272 "allwinner,sun4i-a10-sram-a3-a4";
273 reg = <0x8000 0x4000>;
279 compatible = "mmio-sram";
280 reg = <0x00010000 0x1000>;
281 #address-cells = <1>;
283 ranges = <0 0x00010000 0x1000>;
285 otg_sram: sram-section@0 {
286 compatible = "allwinner,sun7i-a20-sram-d",
287 "allwinner,sun4i-a10-sram-d";
288 reg = <0x0000 0x1000>;
293 sram_c: sram@1d00000 {
294 compatible = "mmio-sram";
295 reg = <0x01d00000 0xd0000>;
296 #address-cells = <1>;
298 ranges = <0 0x01d00000 0xd0000>;
300 ve_sram: sram-section@0 {
301 compatible = "allwinner,sun7i-a20-sram-c1",
302 "allwinner,sun4i-a10-sram-c1";
303 reg = <0x000000 0x80000>;
308 nmi_intc: interrupt-controller@1c00030 {
309 compatible = "allwinner,sun7i-a20-sc-nmi";
310 interrupt-controller;
311 #interrupt-cells = <2>;
312 reg = <0x01c00030 0x0c>;
313 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
316 dma: dma-controller@1c02000 {
317 compatible = "allwinner,sun4i-a10-dma";
318 reg = <0x01c02000 0x1000>;
319 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&ccu CLK_AHB_DMA>;
325 compatible = "allwinner,sun4i-a10-nand";
326 reg = <0x01c03000 0x1000>;
327 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
329 clock-names = "ahb", "mod";
330 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
333 #address-cells = <1>;
338 compatible = "allwinner,sun4i-a10-spi";
339 reg = <0x01c05000 0x1000>;
340 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
342 clock-names = "ahb", "mod";
343 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
344 <&dma SUN4I_DMA_DEDICATED 26>;
345 dma-names = "rx", "tx";
347 #address-cells = <1>;
353 compatible = "allwinner,sun4i-a10-spi";
354 reg = <0x01c06000 0x1000>;
355 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
357 clock-names = "ahb", "mod";
358 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
359 <&dma SUN4I_DMA_DEDICATED 8>;
360 dma-names = "rx", "tx";
362 #address-cells = <1>;
367 emac: ethernet@1c0b000 {
368 compatible = "allwinner,sun4i-a10-emac";
369 reg = <0x01c0b000 0x1000>;
370 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&ccu CLK_AHB_EMAC>;
372 allwinner,sram = <&emac_sram 1>;
377 compatible = "allwinner,sun4i-a10-mdio";
378 reg = <0x01c0b080 0x14>;
380 #address-cells = <1>;
384 tcon0: lcd-controller@1c0c000 {
385 compatible = "allwinner,sun7i-a20-tcon";
386 reg = <0x01c0c000 0x1000>;
387 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
388 resets = <&ccu RST_TCON0>;
390 clocks = <&ccu CLK_AHB_LCD0>,
391 <&ccu CLK_TCON0_CH0>,
392 <&ccu CLK_TCON0_CH1>;
396 clock-output-names = "tcon0-pixel-clock";
397 dmas = <&dma SUN4I_DMA_DEDICATED 14>;
400 #address-cells = <1>;
404 #address-cells = <1>;
408 tcon0_in_be0: endpoint@0 {
410 remote-endpoint = <&be0_out_tcon0>;
413 tcon0_in_be1: endpoint@1 {
415 remote-endpoint = <&be1_out_tcon0>;
420 #address-cells = <1>;
424 tcon0_out_hdmi: endpoint@1 {
426 remote-endpoint = <&hdmi_in_tcon0>;
427 allwinner,tcon-channel = <1>;
433 tcon1: lcd-controller@1c0d000 {
434 compatible = "allwinner,sun7i-a20-tcon";
435 reg = <0x01c0d000 0x1000>;
436 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
437 resets = <&ccu RST_TCON1>;
439 clocks = <&ccu CLK_AHB_LCD1>,
440 <&ccu CLK_TCON1_CH0>,
441 <&ccu CLK_TCON1_CH1>;
445 clock-output-names = "tcon1-pixel-clock";
446 dmas = <&dma SUN4I_DMA_DEDICATED 15>;
449 #address-cells = <1>;
453 #address-cells = <1>;
457 tcon1_in_be0: endpoint@0 {
459 remote-endpoint = <&be0_out_tcon1>;
462 tcon1_in_be1: endpoint@1 {
464 remote-endpoint = <&be1_out_tcon1>;
469 #address-cells = <1>;
473 tcon1_out_hdmi: endpoint@1 {
475 remote-endpoint = <&hdmi_in_tcon1>;
476 allwinner,tcon-channel = <1>;
483 compatible = "allwinner,sun7i-a20-mmc";
484 reg = <0x01c0f000 0x1000>;
485 clocks = <&ccu CLK_AHB_MMC0>,
487 <&ccu CLK_MMC0_OUTPUT>,
488 <&ccu CLK_MMC0_SAMPLE>;
493 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
495 #address-cells = <1>;
500 compatible = "allwinner,sun7i-a20-mmc";
501 reg = <0x01c10000 0x1000>;
502 clocks = <&ccu CLK_AHB_MMC1>,
504 <&ccu CLK_MMC1_OUTPUT>,
505 <&ccu CLK_MMC1_SAMPLE>;
510 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
512 #address-cells = <1>;
517 compatible = "allwinner,sun7i-a20-mmc";
518 reg = <0x01c11000 0x1000>;
519 clocks = <&ccu CLK_AHB_MMC2>,
521 <&ccu CLK_MMC2_OUTPUT>,
522 <&ccu CLK_MMC2_SAMPLE>;
527 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
529 #address-cells = <1>;
534 compatible = "allwinner,sun7i-a20-mmc";
535 reg = <0x01c12000 0x1000>;
536 clocks = <&ccu CLK_AHB_MMC3>,
538 <&ccu CLK_MMC3_OUTPUT>,
539 <&ccu CLK_MMC3_SAMPLE>;
544 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
546 #address-cells = <1>;
550 usb_otg: usb@1c13000 {
551 compatible = "allwinner,sun4i-a10-musb";
552 reg = <0x01c13000 0x0400>;
553 clocks = <&ccu CLK_AHB_OTG>;
554 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
555 interrupt-names = "mc";
558 extcon = <&usbphy 0>;
559 allwinner,sram = <&otg_sram 1>;
563 usbphy: phy@1c13400 {
565 compatible = "allwinner,sun7i-a20-usb-phy";
566 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
567 reg-names = "phy_ctrl", "pmu1", "pmu2";
568 clocks = <&ccu CLK_USB_PHY>;
569 clock-names = "usb_phy";
570 resets = <&ccu RST_USB_PHY0>,
573 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
578 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
579 reg = <0x01c14000 0x100>;
580 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
581 clocks = <&ccu CLK_AHB_EHCI0>;
588 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
589 reg = <0x01c14400 0x100>;
590 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
591 clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
597 crypto: crypto-engine@1c15000 {
598 compatible = "allwinner,sun7i-a20-crypto",
599 "allwinner,sun4i-a10-crypto";
600 reg = <0x01c15000 0x1000>;
601 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
603 clock-names = "ahb", "mod";
607 compatible = "allwinner,sun7i-a20-hdmi",
608 "allwinner,sun5i-a10s-hdmi";
609 reg = <0x01c16000 0x1000>;
610 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
611 clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
612 <&ccu CLK_PLL_VIDEO0_2X>,
613 <&ccu CLK_PLL_VIDEO1_2X>;
614 clock-names = "ahb", "mod", "pll-0", "pll-1";
615 dmas = <&dma SUN4I_DMA_NORMAL 16>,
616 <&dma SUN4I_DMA_NORMAL 16>,
617 <&dma SUN4I_DMA_DEDICATED 24>;
618 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
622 #address-cells = <1>;
626 #address-cells = <1>;
630 hdmi_in_tcon0: endpoint@0 {
632 remote-endpoint = <&tcon0_out_hdmi>;
635 hdmi_in_tcon1: endpoint@1 {
637 remote-endpoint = <&tcon1_out_hdmi>;
648 compatible = "allwinner,sun4i-a10-spi";
649 reg = <0x01c17000 0x1000>;
650 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
652 clock-names = "ahb", "mod";
653 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
654 <&dma SUN4I_DMA_DEDICATED 28>;
655 dma-names = "rx", "tx";
657 #address-cells = <1>;
663 compatible = "allwinner,sun4i-a10-ahci";
664 reg = <0x01c18000 0x1000>;
665 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
671 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
672 reg = <0x01c1c000 0x100>;
673 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
674 clocks = <&ccu CLK_AHB_EHCI1>;
681 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
682 reg = <0x01c1c400 0x100>;
683 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
684 clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
691 compatible = "allwinner,sun4i-a10-spi";
692 reg = <0x01c1f000 0x1000>;
693 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
694 clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
695 clock-names = "ahb", "mod";
696 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
697 <&dma SUN4I_DMA_DEDICATED 30>;
698 dma-names = "rx", "tx";
700 #address-cells = <1>;
706 compatible = "allwinner,sun7i-a20-ccu";
707 reg = <0x01c20000 0x400>;
708 clocks = <&osc24M>, <&osc32k>;
709 clock-names = "hosc", "losc";
714 pio: pinctrl@1c20800 {
715 compatible = "allwinner,sun7i-a20-pinctrl";
716 reg = <0x01c20800 0x400>;
717 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
718 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
719 clock-names = "apb", "hosc", "losc";
721 interrupt-controller;
722 #interrupt-cells = <3>;
725 can0_pins_a: can0@0 {
726 pins = "PH20", "PH21";
730 clk_out_a_pins_a: clk_out_a@0 {
732 function = "clk_out_a";
735 clk_out_b_pins_a: clk_out_b@0 {
737 function = "clk_out_b";
740 emac_pins_a: emac0@0 {
741 pins = "PA0", "PA1", "PA2",
742 "PA3", "PA4", "PA5", "PA6",
743 "PA7", "PA8", "PA9", "PA10",
744 "PA11", "PA12", "PA13", "PA14",
749 gmac_pins_mii_a: gmac_mii@0 {
750 pins = "PA0", "PA1", "PA2",
751 "PA3", "PA4", "PA5", "PA6",
752 "PA7", "PA8", "PA9", "PA10",
753 "PA11", "PA12", "PA13", "PA14",
758 gmac_pins_rgmii_a: gmac_rgmii@0 {
759 pins = "PA0", "PA1", "PA2",
760 "PA3", "PA4", "PA5", "PA6",
761 "PA7", "PA8", "PA10",
762 "PA11", "PA12", "PA13",
766 * data lines in RGMII mode use DDR mode
767 * and need a higher signal drive strength
769 drive-strength = <40>;
772 i2c0_pins_a: i2c0@0 {
777 i2c1_pins_a: i2c1@0 {
778 pins = "PB18", "PB19";
782 i2c2_pins_a: i2c2@0 {
783 pins = "PB20", "PB21";
787 i2c3_pins_a: i2c3@0 {
792 ir0_rx_pins_a: ir0@0 {
797 ir0_tx_pins_a: ir0@1 {
802 ir1_rx_pins_a: ir1@0 {
807 ir1_tx_pins_a: ir1@1 {
812 mmc0_pins_a: mmc0@0 {
813 pins = "PF0", "PF1", "PF2",
816 drive-strength = <30>;
820 mmc2_pins_a: mmc2@0 {
821 pins = "PC6", "PC7", "PC8",
822 "PC9", "PC10", "PC11";
824 drive-strength = <30>;
828 mmc3_pins_a: mmc3@0 {
829 pins = "PI4", "PI5", "PI6",
832 drive-strength = <30>;
836 ps20_pins_a: ps20@0 {
837 pins = "PI20", "PI21";
841 ps21_pins_a: ps21@0 {
842 pins = "PH12", "PH13";
846 pwm0_pins_a: pwm0@0 {
851 pwm1_pins_a: pwm1@0 {
856 spdif_tx_pins_a: spdif@0 {
862 spi0_pins_a: spi0@0 {
863 pins = "PI11", "PI12", "PI13";
867 spi0_cs0_pins_a: spi0_cs0@0 {
872 spi0_cs1_pins_a: spi0_cs1@0 {
877 spi1_pins_a: spi1@0 {
878 pins = "PI17", "PI18", "PI19";
882 spi1_cs0_pins_a: spi1_cs0@0 {
887 spi2_pins_a: spi2@0 {
888 pins = "PC20", "PC21", "PC22";
892 spi2_pins_b: spi2@1 {
893 pins = "PB15", "PB16", "PB17";
897 spi2_cs0_pins_a: spi2_cs0@0 {
902 spi2_cs0_pins_b: spi2_cs0@1 {
907 uart0_pins_a: uart0@0 {
908 pins = "PB22", "PB23";
912 uart2_pins_a: uart2@0 {
913 pins = "PI16", "PI17", "PI18", "PI19";
917 uart3_pins_a: uart3@0 {
918 pins = "PG6", "PG7", "PG8", "PG9";
922 uart3_pins_b: uart3@1 {
927 uart4_pins_a: uart4@0 {
928 pins = "PG10", "PG11";
932 uart4_pins_b: uart4@1 {
937 uart5_pins_a: uart5@0 {
938 pins = "PI10", "PI11";
942 uart6_pins_a: uart6@0 {
943 pins = "PI12", "PI13";
947 uart7_pins_a: uart7@0 {
948 pins = "PI20", "PI21";
954 compatible = "allwinner,sun4i-a10-timer";
955 reg = <0x01c20c00 0x90>;
956 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
957 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
958 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
959 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
960 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
961 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
965 wdt: watchdog@1c20c90 {
966 compatible = "allwinner,sun4i-a10-wdt";
967 reg = <0x01c20c90 0x10>;
971 compatible = "allwinner,sun7i-a20-rtc";
972 reg = <0x01c20d00 0x20>;
973 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
977 compatible = "allwinner,sun7i-a20-pwm";
978 reg = <0x01c20e00 0xc>;
984 spdif: spdif@1c21000 {
985 #sound-dai-cells = <0>;
986 compatible = "allwinner,sun4i-a10-spdif";
987 reg = <0x01c21000 0x400>;
988 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
989 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
990 clock-names = "apb", "spdif";
991 dmas = <&dma SUN4I_DMA_NORMAL 2>,
992 <&dma SUN4I_DMA_NORMAL 2>;
993 dma-names = "rx", "tx";
998 compatible = "allwinner,sun4i-a10-ir";
999 clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
1000 clock-names = "apb", "ir";
1001 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1002 reg = <0x01c21800 0x40>;
1003 status = "disabled";
1007 compatible = "allwinner,sun4i-a10-ir";
1008 clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
1009 clock-names = "apb", "ir";
1010 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1011 reg = <0x01c21c00 0x40>;
1012 status = "disabled";
1016 #sound-dai-cells = <0>;
1017 compatible = "allwinner,sun4i-a10-i2s";
1018 reg = <0x01c22000 0x400>;
1019 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1020 clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>;
1021 clock-names = "apb", "mod";
1022 dmas = <&dma SUN4I_DMA_NORMAL 4>,
1023 <&dma SUN4I_DMA_NORMAL 4>;
1024 dma-names = "rx", "tx";
1025 status = "disabled";
1029 #sound-dai-cells = <0>;
1030 compatible = "allwinner,sun4i-a10-i2s";
1031 reg = <0x01c22400 0x400>;
1032 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1033 clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
1034 clock-names = "apb", "mod";
1035 dmas = <&dma SUN4I_DMA_NORMAL 3>,
1036 <&dma SUN4I_DMA_NORMAL 3>;
1037 dma-names = "rx", "tx";
1038 status = "disabled";
1041 lradc: lradc@1c22800 {
1042 compatible = "allwinner,sun4i-a10-lradc-keys";
1043 reg = <0x01c22800 0x100>;
1044 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1045 status = "disabled";
1048 codec: codec@1c22c00 {
1049 #sound-dai-cells = <0>;
1050 compatible = "allwinner,sun7i-a20-codec";
1051 reg = <0x01c22c00 0x40>;
1052 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1053 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
1054 clock-names = "apb", "codec";
1055 dmas = <&dma SUN4I_DMA_NORMAL 19>,
1056 <&dma SUN4I_DMA_NORMAL 19>;
1057 dma-names = "rx", "tx";
1058 status = "disabled";
1061 sid: eeprom@1c23800 {
1062 compatible = "allwinner,sun7i-a20-sid";
1063 reg = <0x01c23800 0x200>;
1067 #sound-dai-cells = <0>;
1068 compatible = "allwinner,sun4i-a10-i2s";
1069 reg = <0x01c24400 0x400>;
1070 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1071 clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>;
1072 clock-names = "apb", "mod";
1073 dmas = <&dma SUN4I_DMA_NORMAL 6>,
1074 <&dma SUN4I_DMA_NORMAL 6>;
1075 dma-names = "rx", "tx";
1076 status = "disabled";
1080 compatible = "allwinner,sun5i-a13-ts";
1081 reg = <0x01c25000 0x100>;
1082 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1083 #thermal-sensor-cells = <0>;
1086 uart0: serial@1c28000 {
1087 compatible = "snps,dw-apb-uart";
1088 reg = <0x01c28000 0x400>;
1089 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1092 clocks = <&ccu CLK_APB1_UART0>;
1093 status = "disabled";
1096 uart1: serial@1c28400 {
1097 compatible = "snps,dw-apb-uart";
1098 reg = <0x01c28400 0x400>;
1099 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1102 clocks = <&ccu CLK_APB1_UART1>;
1103 status = "disabled";
1106 uart2: serial@1c28800 {
1107 compatible = "snps,dw-apb-uart";
1108 reg = <0x01c28800 0x400>;
1109 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1112 clocks = <&ccu CLK_APB1_UART2>;
1113 status = "disabled";
1116 uart3: serial@1c28c00 {
1117 compatible = "snps,dw-apb-uart";
1118 reg = <0x01c28c00 0x400>;
1119 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1122 clocks = <&ccu CLK_APB1_UART3>;
1123 status = "disabled";
1126 uart4: serial@1c29000 {
1127 compatible = "snps,dw-apb-uart";
1128 reg = <0x01c29000 0x400>;
1129 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1132 clocks = <&ccu CLK_APB1_UART4>;
1133 status = "disabled";
1136 uart5: serial@1c29400 {
1137 compatible = "snps,dw-apb-uart";
1138 reg = <0x01c29400 0x400>;
1139 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1142 clocks = <&ccu CLK_APB1_UART5>;
1143 status = "disabled";
1146 uart6: serial@1c29800 {
1147 compatible = "snps,dw-apb-uart";
1148 reg = <0x01c29800 0x400>;
1149 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1152 clocks = <&ccu CLK_APB1_UART6>;
1153 status = "disabled";
1156 uart7: serial@1c29c00 {
1157 compatible = "snps,dw-apb-uart";
1158 reg = <0x01c29c00 0x400>;
1159 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1162 clocks = <&ccu CLK_APB1_UART7>;
1163 status = "disabled";
1167 compatible = "allwinner,sun4i-a10-ps2";
1168 reg = <0x01c2a000 0x400>;
1169 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1170 clocks = <&ccu CLK_APB1_PS20>;
1171 status = "disabled";
1175 compatible = "allwinner,sun4i-a10-ps2";
1176 reg = <0x01c2a400 0x400>;
1177 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1178 clocks = <&ccu CLK_APB1_PS21>;
1179 status = "disabled";
1183 compatible = "allwinner,sun7i-a20-i2c",
1184 "allwinner,sun4i-a10-i2c";
1185 reg = <0x01c2ac00 0x400>;
1186 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1187 clocks = <&ccu CLK_APB1_I2C0>;
1188 status = "disabled";
1189 #address-cells = <1>;
1194 compatible = "allwinner,sun7i-a20-i2c",
1195 "allwinner,sun4i-a10-i2c";
1196 reg = <0x01c2b000 0x400>;
1197 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1198 clocks = <&ccu CLK_APB1_I2C1>;
1199 status = "disabled";
1200 #address-cells = <1>;
1205 compatible = "allwinner,sun7i-a20-i2c",
1206 "allwinner,sun4i-a10-i2c";
1207 reg = <0x01c2b400 0x400>;
1208 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1209 clocks = <&ccu CLK_APB1_I2C2>;
1210 status = "disabled";
1211 #address-cells = <1>;
1216 compatible = "allwinner,sun7i-a20-i2c",
1217 "allwinner,sun4i-a10-i2c";
1218 reg = <0x01c2b800 0x400>;
1219 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1220 clocks = <&ccu CLK_APB1_I2C3>;
1221 status = "disabled";
1222 #address-cells = <1>;
1227 compatible = "allwinner,sun7i-a20-can",
1228 "allwinner,sun4i-a10-can";
1229 reg = <0x01c2bc00 0x400>;
1230 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1231 clocks = <&ccu CLK_APB1_CAN>;
1232 status = "disabled";
1236 compatible = "allwinner,sun7i-a20-i2c",
1237 "allwinner,sun4i-a10-i2c";
1238 reg = <0x01c2c000 0x400>;
1239 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1240 clocks = <&ccu CLK_APB1_I2C4>;
1241 status = "disabled";
1242 #address-cells = <1>;
1247 compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
1248 reg = <0x01c40000 0x10000>;
1249 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1250 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1251 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1252 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
1253 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
1254 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1255 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1256 interrupt-names = "gp",
1263 clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
1264 clock-names = "bus", "core";
1265 resets = <&ccu RST_GPU>;
1267 assigned-clocks = <&ccu CLK_GPU>;
1268 assigned-clock-rates = <384000000>;
1271 gmac: ethernet@1c50000 {
1272 compatible = "allwinner,sun7i-a20-gmac";
1273 reg = <0x01c50000 0x10000>;
1274 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1275 interrupt-names = "macirq";
1276 clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>;
1277 clock-names = "stmmaceth", "allwinner_gmac_tx";
1280 snps,force_sf_dma_mode;
1281 status = "disabled";
1282 #address-cells = <1>;
1287 compatible = "allwinner,sun7i-a20-hstimer";
1288 reg = <0x01c60000 0x1000>;
1289 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1290 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1291 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1292 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1293 clocks = <&ccu CLK_AHB_HSTIMER>;
1296 gic: interrupt-controller@1c81000 {
1297 compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1298 reg = <0x01c81000 0x1000>,
1299 <0x01c82000 0x2000>,
1300 <0x01c84000 0x2000>,
1301 <0x01c86000 0x2000>;
1302 interrupt-controller;
1303 #interrupt-cells = <3>;
1304 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1307 fe0: display-frontend@1e00000 {
1308 compatible = "allwinner,sun7i-a20-display-frontend";
1309 reg = <0x01e00000 0x20000>;
1310 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1311 clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1312 <&ccu CLK_DRAM_DE_FE0>;
1313 clock-names = "ahb", "mod",
1315 resets = <&ccu RST_DE_FE0>;
1318 #address-cells = <1>;
1322 #address-cells = <1>;
1326 fe0_out_be0: endpoint@0 {
1328 remote-endpoint = <&be0_in_fe0>;
1331 fe0_out_be1: endpoint@1 {
1333 remote-endpoint = <&be1_in_fe0>;
1339 fe1: display-frontend@1e20000 {
1340 compatible = "allwinner,sun7i-a20-display-frontend";
1341 reg = <0x01e20000 0x20000>;
1342 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1343 clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1344 <&ccu CLK_DRAM_DE_FE1>;
1345 clock-names = "ahb", "mod",
1347 resets = <&ccu RST_DE_FE1>;
1350 #address-cells = <1>;
1354 #address-cells = <1>;
1358 fe1_out_be0: endpoint@0 {
1360 remote-endpoint = <&be0_in_fe1>;
1363 fe1_out_be1: endpoint@1 {
1365 remote-endpoint = <&be1_in_fe1>;
1371 be1: display-backend@1e40000 {
1372 compatible = "allwinner,sun7i-a20-display-backend";
1373 reg = <0x01e40000 0x10000>;
1374 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1375 clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1376 <&ccu CLK_DRAM_DE_BE1>;
1377 clock-names = "ahb", "mod",
1379 resets = <&ccu RST_DE_BE1>;
1382 #address-cells = <1>;
1386 #address-cells = <1>;
1390 be1_in_fe0: endpoint@0 {
1392 remote-endpoint = <&fe0_out_be1>;
1395 be1_in_fe1: endpoint@1 {
1397 remote-endpoint = <&fe1_out_be1>;
1402 #address-cells = <1>;
1406 be1_out_tcon0: endpoint@0 {
1408 remote-endpoint = <&tcon0_in_be1>;
1411 be1_out_tcon1: endpoint@1 {
1413 remote-endpoint = <&tcon1_in_be1>;
1419 be0: display-backend@1e60000 {
1420 compatible = "allwinner,sun7i-a20-display-backend";
1421 reg = <0x01e60000 0x10000>;
1422 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1423 clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1424 <&ccu CLK_DRAM_DE_BE0>;
1425 clock-names = "ahb", "mod",
1427 resets = <&ccu RST_DE_BE0>;
1430 #address-cells = <1>;
1434 #address-cells = <1>;
1438 be0_in_fe0: endpoint@0 {
1440 remote-endpoint = <&fe0_out_be0>;
1443 be0_in_fe1: endpoint@1 {
1445 remote-endpoint = <&fe1_out_be0>;
1450 #address-cells = <1>;
1454 be0_out_tcon0: endpoint@0 {
1456 remote-endpoint = <&tcon0_in_be0>;
1459 be0_out_tcon1: endpoint@1 {
1461 remote-endpoint = <&tcon1_in_be0>;