2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "skeleton.dtsi"
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
50 #include <dt-bindings/clock/sun6i-a31-ccu.h>
51 #include <dt-bindings/reset/sun6i-a31-ccu.h>
54 interrupt-parent = <&gic>;
65 simplefb_hdmi: framebuffer@0 {
66 compatible = "allwinner,simple-framebuffer",
68 allwinner,pipeline = "de_be0-lcd0-hdmi";
69 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
70 <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
71 <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
72 <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
76 simplefb_lcd: framebuffer@1 {
77 compatible = "allwinner,simple-framebuffer",
79 allwinner,pipeline = "de_be0-lcd0";
80 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
81 <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
82 <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
88 compatible = "arm,armv7-timer";
89 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
90 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
93 clock-frequency = <24000000>;
94 arm,cpu-registers-not-fw-configured;
98 enable-method = "allwinner,sun6i-a31";
103 compatible = "arm,cortex-a7";
106 clocks = <&ccu CLK_CPU>;
107 clock-latency = <244144>; /* 8 32k periods */
115 #cooling-cells = <2>;
119 compatible = "arm,cortex-a7";
122 clocks = <&ccu CLK_CPU>;
123 clock-latency = <244144>; /* 8 32k periods */
131 #cooling-cells = <2>;
135 compatible = "arm,cortex-a7";
138 clocks = <&ccu CLK_CPU>;
139 clock-latency = <244144>; /* 8 32k periods */
147 #cooling-cells = <2>;
151 compatible = "arm,cortex-a7";
154 clocks = <&ccu CLK_CPU>;
155 clock-latency = <244144>; /* 8 32k periods */
163 #cooling-cells = <2>;
170 polling-delay-passive = <250>;
171 polling-delay = <1000>;
172 thermal-sensors = <&rtp>;
176 trip = <&cpu_alert0>;
177 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
182 cpu_alert0: cpu_alert0 {
184 temperature = <70000>;
191 temperature = <100000>;
200 reg = <0x40000000 0x80000000>;
204 compatible = "arm,cortex-a7-pmu";
205 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
212 #address-cells = <1>;
218 compatible = "fixed-clock";
219 clock-frequency = <24000000>;
224 compatible = "fixed-clock";
225 clock-frequency = <32768>;
226 clock-output-names = "osc32k";
230 * The following two are dummy clocks, placeholders
231 * used in the gmac_tx clock. The gmac driver will
232 * choose one parent depending on the PHY interface
233 * mode, using clk_set_rate auto-reparenting.
235 * The actual TX clock rate is not controlled by the
238 mii_phy_tx_clk: clk@1 {
240 compatible = "fixed-clock";
241 clock-frequency = <25000000>;
242 clock-output-names = "mii_phy_tx";
245 gmac_int_tx_clk: clk@2 {
247 compatible = "fixed-clock";
248 clock-frequency = <125000000>;
249 clock-output-names = "gmac_int_tx";
252 gmac_tx_clk: clk@1c200d0 {
254 compatible = "allwinner,sun7i-a20-gmac-clk";
255 reg = <0x01c200d0 0x4>;
256 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
257 clock-output-names = "gmac_tx";
262 compatible = "allwinner,sun6i-a31-display-engine";
263 allwinner,pipelines = <&fe0>, <&fe1>;
268 compatible = "simple-bus";
269 #address-cells = <1>;
273 dma: dma-controller@1c02000 {
274 compatible = "allwinner,sun6i-a31-dma";
275 reg = <0x01c02000 0x1000>;
276 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&ccu CLK_AHB1_DMA>;
278 resets = <&ccu RST_AHB1_DMA>;
282 tcon0: lcd-controller@1c0c000 {
283 compatible = "allwinner,sun6i-a31-tcon";
284 reg = <0x01c0c000 0x1000>;
285 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
286 resets = <&ccu RST_AHB1_LCD0>;
288 clocks = <&ccu CLK_AHB1_LCD0>,
294 clock-output-names = "tcon0-pixel-clock";
297 #address-cells = <1>;
301 #address-cells = <1>;
305 tcon0_in_drc0: endpoint@0 {
307 remote-endpoint = <&drc0_out_tcon0>;
310 tcon0_in_drc1: endpoint@1 {
312 remote-endpoint = <&drc1_out_tcon0>;
317 #address-cells = <1>;
321 tcon0_out_hdmi: endpoint@1 {
323 remote-endpoint = <&hdmi_in_tcon0>;
324 allwinner,tcon-channel = <1>;
330 tcon1: lcd-controller@1c0d000 {
331 compatible = "allwinner,sun6i-a31-tcon";
332 reg = <0x01c0d000 0x1000>;
333 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
334 resets = <&ccu RST_AHB1_LCD1>;
336 clocks = <&ccu CLK_AHB1_LCD1>,
342 clock-output-names = "tcon1-pixel-clock";
345 #address-cells = <1>;
349 #address-cells = <1>;
353 tcon1_in_drc0: endpoint@0 {
355 remote-endpoint = <&drc0_out_tcon1>;
358 tcon1_in_drc1: endpoint@1 {
360 remote-endpoint = <&drc1_out_tcon1>;
365 #address-cells = <1>;
369 tcon1_out_hdmi: endpoint@1 {
371 remote-endpoint = <&hdmi_in_tcon1>;
372 allwinner,tcon-channel = <1>;
379 compatible = "allwinner,sun7i-a20-mmc";
380 reg = <0x01c0f000 0x1000>;
381 clocks = <&ccu CLK_AHB1_MMC0>,
383 <&ccu CLK_MMC0_OUTPUT>,
384 <&ccu CLK_MMC0_SAMPLE>;
389 resets = <&ccu RST_AHB1_MMC0>;
391 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
393 #address-cells = <1>;
398 compatible = "allwinner,sun7i-a20-mmc";
399 reg = <0x01c10000 0x1000>;
400 clocks = <&ccu CLK_AHB1_MMC1>,
402 <&ccu CLK_MMC1_OUTPUT>,
403 <&ccu CLK_MMC1_SAMPLE>;
408 resets = <&ccu RST_AHB1_MMC1>;
410 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
412 #address-cells = <1>;
417 compatible = "allwinner,sun7i-a20-mmc";
418 reg = <0x01c11000 0x1000>;
419 clocks = <&ccu CLK_AHB1_MMC2>,
421 <&ccu CLK_MMC2_OUTPUT>,
422 <&ccu CLK_MMC2_SAMPLE>;
427 resets = <&ccu RST_AHB1_MMC2>;
429 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
431 #address-cells = <1>;
436 compatible = "allwinner,sun7i-a20-mmc";
437 reg = <0x01c12000 0x1000>;
438 clocks = <&ccu CLK_AHB1_MMC3>,
440 <&ccu CLK_MMC3_OUTPUT>,
441 <&ccu CLK_MMC3_SAMPLE>;
446 resets = <&ccu RST_AHB1_MMC3>;
448 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
450 #address-cells = <1>;
455 compatible = "allwinner,sun6i-a31-hdmi";
456 reg = <0x01c16000 0x1000>;
457 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>,
460 <&ccu CLK_PLL_VIDEO0_2X>,
461 <&ccu CLK_PLL_VIDEO1_2X>;
462 clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
463 resets = <&ccu RST_AHB1_HDMI>;
465 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
466 dmas = <&dma 13>, <&dma 13>, <&dma 14>;
470 #address-cells = <1>;
474 #address-cells = <1>;
478 hdmi_in_tcon0: endpoint@0 {
480 remote-endpoint = <&tcon0_out_hdmi>;
483 hdmi_in_tcon1: endpoint@1 {
485 remote-endpoint = <&tcon1_out_hdmi>;
490 #address-cells = <1>;
497 usb_otg: usb@1c19000 {
498 compatible = "allwinner,sun6i-a31-musb";
499 reg = <0x01c19000 0x0400>;
500 clocks = <&ccu CLK_AHB1_OTG>;
501 resets = <&ccu RST_AHB1_OTG>;
502 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
503 interrupt-names = "mc";
506 extcon = <&usbphy 0>;
510 usbphy: phy@1c19400 {
511 compatible = "allwinner,sun6i-a31-usb-phy";
512 reg = <0x01c19400 0x10>,
515 reg-names = "phy_ctrl",
518 clocks = <&ccu CLK_USB_PHY0>,
521 clock-names = "usb0_phy",
524 resets = <&ccu RST_USB_PHY0>,
527 reset-names = "usb0_reset",
535 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
536 reg = <0x01c1a000 0x100>;
537 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&ccu CLK_AHB1_EHCI0>;
539 resets = <&ccu RST_AHB1_EHCI0>;
546 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
547 reg = <0x01c1a400 0x100>;
548 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
550 resets = <&ccu RST_AHB1_OHCI0>;
557 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
558 reg = <0x01c1b000 0x100>;
559 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&ccu CLK_AHB1_EHCI1>;
561 resets = <&ccu RST_AHB1_EHCI1>;
568 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
569 reg = <0x01c1b400 0x100>;
570 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
572 resets = <&ccu RST_AHB1_OHCI1>;
579 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
580 reg = <0x01c1c400 0x100>;
581 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
583 resets = <&ccu RST_AHB1_OHCI2>;
588 compatible = "allwinner,sun6i-a31-ccu";
589 reg = <0x01c20000 0x400>;
590 clocks = <&osc24M>, <&osc32k>;
591 clock-names = "hosc", "losc";
596 pio: pinctrl@1c20800 {
597 compatible = "allwinner,sun6i-a31-pinctrl";
598 reg = <0x01c20800 0x400>;
599 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>;
604 clock-names = "apb", "hosc", "losc";
606 interrupt-controller;
607 #interrupt-cells = <3>;
610 gmac_pins_gmii_a: gmac_gmii@0 {
611 pins = "PA0", "PA1", "PA2", "PA3",
612 "PA4", "PA5", "PA6", "PA7",
613 "PA8", "PA9", "PA10", "PA11",
614 "PA12", "PA13", "PA14", "PA15",
615 "PA16", "PA17", "PA18", "PA19",
616 "PA20", "PA21", "PA22", "PA23",
617 "PA24", "PA25", "PA26", "PA27";
620 * data lines in GMII mode run at 125MHz and
621 * might need a higher signal drive strength
623 drive-strength = <30>;
626 gmac_pins_mii_a: gmac_mii@0 {
627 pins = "PA0", "PA1", "PA2", "PA3",
628 "PA8", "PA9", "PA11",
629 "PA12", "PA13", "PA14", "PA19",
630 "PA20", "PA21", "PA22", "PA23",
631 "PA24", "PA26", "PA27";
635 gmac_pins_rgmii_a: gmac_rgmii@0 {
636 pins = "PA0", "PA1", "PA2", "PA3",
637 "PA9", "PA10", "PA11",
638 "PA12", "PA13", "PA14", "PA19",
639 "PA20", "PA25", "PA26", "PA27";
642 * data lines in RGMII mode use DDR mode
643 * and need a higher signal drive strength
645 drive-strength = <40>;
648 i2c0_pins_a: i2c0@0 {
649 pins = "PH14", "PH15";
653 i2c1_pins_a: i2c1@0 {
654 pins = "PH16", "PH17";
658 i2c2_pins_a: i2c2@0 {
659 pins = "PH18", "PH19";
663 lcd0_rgb888_pins: lcd0_rgb888 {
664 pins = "PD0", "PD1", "PD2", "PD3",
665 "PD4", "PD5", "PD6", "PD7",
666 "PD8", "PD9", "PD10", "PD11",
667 "PD12", "PD13", "PD14", "PD15",
668 "PD16", "PD17", "PD18", "PD19",
669 "PD20", "PD21", "PD22", "PD23",
670 "PD24", "PD25", "PD26", "PD27";
674 mmc0_pins_a: mmc0@0 {
675 pins = "PF0", "PF1", "PF2",
678 drive-strength = <30>;
682 mmc1_pins_a: mmc1@0 {
683 pins = "PG0", "PG1", "PG2", "PG3",
686 drive-strength = <30>;
690 mmc2_pins_a: mmc2@0 {
691 pins = "PC6", "PC7", "PC8", "PC9",
694 drive-strength = <30>;
698 mmc2_8bit_emmc_pins: mmc2@1 {
699 pins = "PC6", "PC7", "PC8", "PC9",
700 "PC10", "PC11", "PC12",
701 "PC13", "PC14", "PC15",
704 drive-strength = <30>;
708 mmc3_8bit_emmc_pins: mmc3@1 {
709 pins = "PC6", "PC7", "PC8", "PC9",
710 "PC10", "PC11", "PC12",
711 "PC13", "PC14", "PC15",
714 drive-strength = <40>;
718 spdif_pins_a: spdif@0 {
723 uart0_pins_a: uart0@0 {
724 pins = "PH20", "PH21";
730 compatible = "allwinner,sun4i-a10-timer";
731 reg = <0x01c20c00 0xa0>;
732 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
733 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
734 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
740 wdt1: watchdog@1c20ca0 {
741 compatible = "allwinner,sun6i-a31-wdt";
742 reg = <0x01c20ca0 0x20>;
745 spdif: spdif@1c21000 {
746 #sound-dai-cells = <0>;
747 compatible = "allwinner,sun6i-a31-spdif";
748 reg = <0x01c21000 0x400>;
749 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
750 clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>;
751 resets = <&ccu RST_APB1_SPDIF>;
752 clock-names = "apb", "spdif";
753 dmas = <&dma 2>, <&dma 2>;
754 dma-names = "rx", "tx";
759 #sound-dai-cells = <0>;
760 compatible = "allwinner,sun6i-a31-i2s";
761 reg = <0x01c22000 0x400>;
762 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>;
764 resets = <&ccu RST_APB1_DAUDIO0>;
765 clock-names = "apb", "mod";
766 dmas = <&dma 3>, <&dma 3>;
767 dma-names = "rx", "tx";
772 #sound-dai-cells = <0>;
773 compatible = "allwinner,sun6i-a31-i2s";
774 reg = <0x01c22400 0x400>;
775 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
776 clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>;
777 resets = <&ccu RST_APB1_DAUDIO1>;
778 clock-names = "apb", "mod";
779 dmas = <&dma 4>, <&dma 4>;
780 dma-names = "rx", "tx";
784 lradc: lradc@1c22800 {
785 compatible = "allwinner,sun4i-a10-lradc-keys";
786 reg = <0x01c22800 0x100>;
787 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
792 compatible = "allwinner,sun6i-a31-ts";
793 reg = <0x01c25000 0x100>;
794 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
795 #thermal-sensor-cells = <0>;
798 uart0: serial@1c28000 {
799 compatible = "snps,dw-apb-uart";
800 reg = <0x01c28000 0x400>;
801 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
804 clocks = <&ccu CLK_APB2_UART0>;
805 resets = <&ccu RST_APB2_UART0>;
806 dmas = <&dma 6>, <&dma 6>;
807 dma-names = "rx", "tx";
811 uart1: serial@1c28400 {
812 compatible = "snps,dw-apb-uart";
813 reg = <0x01c28400 0x400>;
814 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
817 clocks = <&ccu CLK_APB2_UART1>;
818 resets = <&ccu RST_APB2_UART1>;
819 dmas = <&dma 7>, <&dma 7>;
820 dma-names = "rx", "tx";
824 uart2: serial@1c28800 {
825 compatible = "snps,dw-apb-uart";
826 reg = <0x01c28800 0x400>;
827 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
830 clocks = <&ccu CLK_APB2_UART2>;
831 resets = <&ccu RST_APB2_UART2>;
832 dmas = <&dma 8>, <&dma 8>;
833 dma-names = "rx", "tx";
837 uart3: serial@1c28c00 {
838 compatible = "snps,dw-apb-uart";
839 reg = <0x01c28c00 0x400>;
840 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&ccu CLK_APB2_UART3>;
844 resets = <&ccu RST_APB2_UART3>;
845 dmas = <&dma 9>, <&dma 9>;
846 dma-names = "rx", "tx";
850 uart4: serial@1c29000 {
851 compatible = "snps,dw-apb-uart";
852 reg = <0x01c29000 0x400>;
853 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
856 clocks = <&ccu CLK_APB2_UART4>;
857 resets = <&ccu RST_APB2_UART4>;
858 dmas = <&dma 10>, <&dma 10>;
859 dma-names = "rx", "tx";
863 uart5: serial@1c29400 {
864 compatible = "snps,dw-apb-uart";
865 reg = <0x01c29400 0x400>;
866 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
869 clocks = <&ccu CLK_APB2_UART5>;
870 resets = <&ccu RST_APB2_UART5>;
871 dmas = <&dma 22>, <&dma 22>;
872 dma-names = "rx", "tx";
877 compatible = "allwinner,sun6i-a31-i2c";
878 reg = <0x01c2ac00 0x400>;
879 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
880 clocks = <&ccu CLK_APB2_I2C0>;
881 resets = <&ccu RST_APB2_I2C0>;
883 #address-cells = <1>;
888 compatible = "allwinner,sun6i-a31-i2c";
889 reg = <0x01c2b000 0x400>;
890 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
891 clocks = <&ccu CLK_APB2_I2C1>;
892 resets = <&ccu RST_APB2_I2C1>;
894 #address-cells = <1>;
899 compatible = "allwinner,sun6i-a31-i2c";
900 reg = <0x01c2b400 0x400>;
901 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
902 clocks = <&ccu CLK_APB2_I2C2>;
903 resets = <&ccu RST_APB2_I2C2>;
905 #address-cells = <1>;
910 compatible = "allwinner,sun6i-a31-i2c";
911 reg = <0x01c2b800 0x400>;
912 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
913 clocks = <&ccu CLK_APB2_I2C3>;
914 resets = <&ccu RST_APB2_I2C3>;
916 #address-cells = <1>;
920 gmac: ethernet@1c30000 {
921 compatible = "allwinner,sun7i-a20-gmac";
922 reg = <0x01c30000 0x1054>;
923 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
924 interrupt-names = "macirq";
925 clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
926 clock-names = "stmmaceth", "allwinner_gmac_tx";
927 resets = <&ccu RST_AHB1_EMAC>;
928 reset-names = "stmmaceth";
931 snps,force_sf_dma_mode;
933 #address-cells = <1>;
937 crypto: crypto-engine@1c15000 {
938 compatible = "allwinner,sun6i-a31-crypto",
939 "allwinner,sun4i-a10-crypto";
940 reg = <0x01c15000 0x1000>;
941 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
942 clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
943 clock-names = "ahb", "mod";
944 resets = <&ccu RST_AHB1_SS>;
948 codec: codec@1c22c00 {
949 #sound-dai-cells = <0>;
950 compatible = "allwinner,sun6i-a31-codec";
951 reg = <0x01c22c00 0x400>;
952 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
953 clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
954 clock-names = "apb", "codec";
955 resets = <&ccu RST_APB1_CODEC>;
956 dmas = <&dma 15>, <&dma 15>;
957 dma-names = "rx", "tx";
962 compatible = "allwinner,sun6i-a31-hstimer",
963 "allwinner,sun7i-a20-hstimer";
964 reg = <0x01c60000 0x1000>;
965 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
966 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
967 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
968 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
969 clocks = <&ccu CLK_AHB1_HSTIMER>;
970 resets = <&ccu RST_AHB1_HSTIMER>;
974 compatible = "allwinner,sun6i-a31-spi";
975 reg = <0x01c68000 0x1000>;
976 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
977 clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
978 clock-names = "ahb", "mod";
979 dmas = <&dma 23>, <&dma 23>;
980 dma-names = "rx", "tx";
981 resets = <&ccu RST_AHB1_SPI0>;
986 compatible = "allwinner,sun6i-a31-spi";
987 reg = <0x01c69000 0x1000>;
988 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
989 clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
990 clock-names = "ahb", "mod";
991 dmas = <&dma 24>, <&dma 24>;
992 dma-names = "rx", "tx";
993 resets = <&ccu RST_AHB1_SPI1>;
998 compatible = "allwinner,sun6i-a31-spi";
999 reg = <0x01c6a000 0x1000>;
1000 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1001 clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
1002 clock-names = "ahb", "mod";
1003 dmas = <&dma 25>, <&dma 25>;
1004 dma-names = "rx", "tx";
1005 resets = <&ccu RST_AHB1_SPI2>;
1006 status = "disabled";
1010 compatible = "allwinner,sun6i-a31-spi";
1011 reg = <0x01c6b000 0x1000>;
1012 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1013 clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
1014 clock-names = "ahb", "mod";
1015 dmas = <&dma 26>, <&dma 26>;
1016 dma-names = "rx", "tx";
1017 resets = <&ccu RST_AHB1_SPI3>;
1018 status = "disabled";
1021 gic: interrupt-controller@1c81000 {
1022 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1023 reg = <0x01c81000 0x1000>,
1024 <0x01c82000 0x2000>,
1025 <0x01c84000 0x2000>,
1026 <0x01c86000 0x2000>;
1027 interrupt-controller;
1028 #interrupt-cells = <3>;
1029 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1032 fe0: display-frontend@1e00000 {
1033 compatible = "allwinner,sun6i-a31-display-frontend";
1034 reg = <0x01e00000 0x20000>;
1035 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1036 clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
1037 <&ccu CLK_DRAM_FE0>;
1038 clock-names = "ahb", "mod",
1040 resets = <&ccu RST_AHB1_FE0>;
1043 #address-cells = <1>;
1047 #address-cells = <1>;
1051 fe0_out_be0: endpoint@0 {
1053 remote-endpoint = <&be0_in_fe0>;
1056 fe0_out_be1: endpoint@1 {
1058 remote-endpoint = <&be1_in_fe0>;
1064 fe1: display-frontend@1e20000 {
1065 compatible = "allwinner,sun6i-a31-display-frontend";
1066 reg = <0x01e20000 0x20000>;
1067 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1068 clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>,
1069 <&ccu CLK_DRAM_FE1>;
1070 clock-names = "ahb", "mod",
1072 resets = <&ccu RST_AHB1_FE1>;
1075 #address-cells = <1>;
1079 #address-cells = <1>;
1083 fe1_out_be0: endpoint@0 {
1085 remote-endpoint = <&be0_in_fe1>;
1088 fe1_out_be1: endpoint@1 {
1090 remote-endpoint = <&be1_in_fe1>;
1096 be1: display-backend@1e40000 {
1097 compatible = "allwinner,sun6i-a31-display-backend";
1098 reg = <0x01e40000 0x10000>;
1099 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1100 clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>,
1101 <&ccu CLK_DRAM_BE1>;
1102 clock-names = "ahb", "mod",
1104 resets = <&ccu RST_AHB1_BE1>;
1106 assigned-clocks = <&ccu CLK_BE1>;
1107 assigned-clock-rates = <300000000>;
1110 #address-cells = <1>;
1114 #address-cells = <1>;
1118 be1_in_fe0: endpoint@0 {
1120 remote-endpoint = <&fe0_out_be1>;
1123 be1_in_fe1: endpoint@1 {
1125 remote-endpoint = <&fe1_out_be1>;
1130 #address-cells = <1>;
1134 be1_out_drc1: endpoint@1 {
1136 remote-endpoint = <&drc1_in_be1>;
1143 compatible = "allwinner,sun6i-a31-drc";
1144 reg = <0x01e50000 0x10000>;
1145 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1146 clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>,
1147 <&ccu CLK_DRAM_DRC1>;
1148 clock-names = "ahb", "mod",
1150 resets = <&ccu RST_AHB1_DRC1>;
1152 assigned-clocks = <&ccu CLK_IEP_DRC1>;
1153 assigned-clock-rates = <300000000>;
1156 #address-cells = <1>;
1160 #address-cells = <1>;
1164 drc1_in_be1: endpoint@1 {
1166 remote-endpoint = <&be1_out_drc1>;
1171 #address-cells = <1>;
1175 drc1_out_tcon0: endpoint@0 {
1177 remote-endpoint = <&tcon0_in_drc1>;
1180 drc1_out_tcon1: endpoint@1 {
1182 remote-endpoint = <&tcon1_in_drc1>;
1188 be0: display-backend@1e60000 {
1189 compatible = "allwinner,sun6i-a31-display-backend";
1190 reg = <0x01e60000 0x10000>;
1191 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1192 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
1193 <&ccu CLK_DRAM_BE0>;
1194 clock-names = "ahb", "mod",
1196 resets = <&ccu RST_AHB1_BE0>;
1198 assigned-clocks = <&ccu CLK_BE0>;
1199 assigned-clock-rates = <300000000>;
1202 #address-cells = <1>;
1206 #address-cells = <1>;
1210 be0_in_fe0: endpoint@0 {
1212 remote-endpoint = <&fe0_out_be0>;
1215 be0_in_fe1: endpoint@1 {
1217 remote-endpoint = <&fe1_out_be0>;
1222 #address-cells = <1>;
1226 be0_out_drc0: endpoint@0 {
1228 remote-endpoint = <&drc0_in_be0>;
1235 compatible = "allwinner,sun6i-a31-drc";
1236 reg = <0x01e70000 0x10000>;
1237 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1238 clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
1239 <&ccu CLK_DRAM_DRC0>;
1240 clock-names = "ahb", "mod",
1242 resets = <&ccu RST_AHB1_DRC0>;
1244 assigned-clocks = <&ccu CLK_IEP_DRC0>;
1245 assigned-clock-rates = <300000000>;
1248 #address-cells = <1>;
1252 #address-cells = <1>;
1256 drc0_in_be0: endpoint@0 {
1258 remote-endpoint = <&be0_out_drc0>;
1263 #address-cells = <1>;
1267 drc0_out_tcon0: endpoint@0 {
1269 remote-endpoint = <&tcon0_in_drc0>;
1272 drc0_out_tcon1: endpoint@1 {
1274 remote-endpoint = <&tcon1_in_drc0>;
1281 compatible = "allwinner,sun6i-a31-rtc";
1282 reg = <0x01f00000 0x54>;
1283 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1284 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1287 nmi_intc: interrupt-controller@1f00c00 {
1288 compatible = "allwinner,sun6i-a31-r-intc";
1289 interrupt-controller;
1290 #interrupt-cells = <2>;
1291 reg = <0x01f00c00 0x400>;
1292 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1296 compatible = "allwinner,sun6i-a31-prcm";
1297 reg = <0x01f01400 0x200>;
1300 compatible = "allwinner,sun6i-a31-ar100-clk";
1302 clocks = <&osc32k>, <&osc24M>,
1303 <&ccu CLK_PLL_PERIPH>,
1304 <&ccu CLK_PLL_PERIPH>;
1305 clock-output-names = "ar100";
1309 compatible = "fixed-factor-clock";
1314 clock-output-names = "ahb0";
1318 compatible = "allwinner,sun6i-a31-apb0-clk";
1321 clock-output-names = "apb0";
1324 apb0_gates: apb0_gates_clk {
1325 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1328 clock-output-names = "apb0_pio", "apb0_ir",
1329 "apb0_timer", "apb0_p2wi",
1330 "apb0_uart", "apb0_1wire",
1336 compatible = "allwinner,sun4i-a10-mod0-clk";
1337 clocks = <&osc32k>, <&osc24M>;
1338 clock-output-names = "ir";
1341 apb0_rst: apb0_rst {
1342 compatible = "allwinner,sun6i-a31-clock-reset";
1348 compatible = "allwinner,sun6i-a31-cpuconfig";
1349 reg = <0x01f01c00 0x300>;
1353 compatible = "allwinner,sun5i-a13-ir";
1354 clocks = <&apb0_gates 1>, <&ir_clk>;
1355 clock-names = "apb", "ir";
1356 resets = <&apb0_rst 1>;
1357 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1358 reg = <0x01f02000 0x40>;
1359 status = "disabled";
1362 r_pio: pinctrl@1f02c00 {
1363 compatible = "allwinner,sun6i-a31-r-pinctrl";
1364 reg = <0x01f02c00 0x400>;
1365 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1366 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1367 clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
1368 clock-names = "apb", "hosc", "losc";
1369 resets = <&apb0_rst 0>;
1371 interrupt-controller;
1372 #interrupt-cells = <3>;
1382 pins = "PL0", "PL1";
1383 function = "s_p2wi";
1388 compatible = "allwinner,sun6i-a31-p2wi";
1389 reg = <0x01f03400 0x400>;
1390 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1391 clocks = <&apb0_gates 3>;
1392 clock-frequency = <100000>;
1393 resets = <&apb0_rst 3>;
1394 pinctrl-names = "default";
1395 pinctrl-0 = <&p2wi_pins>;
1396 status = "disabled";
1397 #address-cells = <1>;