arch/arm/boot/dts/stm32mp153.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
   4  * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
   5  */
   6
   7 #include "stm32mp151.dtsi"
   8
   9 / {
  10         cpus {
  11                 cpu1: cpu@1 {
  12                         compatible = "arm,cortex-a7";
  13                         clock-frequency = <650000000>;
  14                         device_type = "cpu";
  15                         reg = <1>;
  16                 };
  17         };
  18
  19         arm-pmu {
  20                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
  21                              <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
  22                 interrupt-affinity = <&cpu0>, <&cpu1>;
  23         };
  24
  25         timer {
  26                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  27                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  28                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  29                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  30         };
  31
  32         soc {
  33                 m_can1: can@4400e000 {
  34                         compatible = "bosch,m_can";
  35                         reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
  36                         reg-names = "m_can", "message_ram";
  37                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
  38                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
  39                         interrupt-names = "int0", "int1";
  40                         clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
  41                         clock-names = "hclk", "cclk";
  42                         bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
  43                         status = "disabled";
  44                 };
  45
  46                 m_can2: can@4400f000 {
  47                         compatible = "bosch,m_can";
  48                         reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
  49                         reg-names = "m_can", "message_ram";
  50                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
  51                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
  52                         interrupt-names = "int0", "int1";
  53                         clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
  54                         clock-names = "hclk", "cclk";
  55                         bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
  56                         status = "disabled";
  57                 };
  58         };
  59 };