1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) Protonic Holland
4 * Author: David Jander <david@protonic.nl>
8 #include "stm32mp151a-prtt1l.dtsi"
11 model = "Protonic PRTT1C";
12 compatible = "prt,prtt1c", "st,stm32mp151";
14 clock_ksz9031: clock-ksz9031 {
15 compatible = "fixed-clock";
17 clock-frequency = <25000000>;
20 clock_sja1105: clock-sja1105 {
21 compatible = "fixed-clock";
23 clock-frequency = <25000000>;
27 compatible = "virtual,mdio-gpio";
30 gpios = <&gpioc 1 GPIO_ACTIVE_HIGH
31 &gpioa 2 GPIO_ACTIVE_HIGH>;
35 wifi_pwrseq: wifi-pwrseq {
36 compatible = "mmc-pwrseq-simple";
37 reset-gpios = <&gpiod 8 GPIO_ACTIVE_LOW>;
50 "", "", "", "PHY0_nRESET", "PHY0_nINT", "", "", "",
51 "", "", "", "", "", "", "", "SPI1_nSS";
56 "", "", "", "", "", "", "", "",
57 "WFM_RESET", "", "", "", "", "", "", "";
62 "SDMMC2_nRESET", "", "", "", "", "", "SPI1_nRESET", "",
63 "", "", "", "", "WFM_nIRQ", "", "", "";
68 "", "", "", "", "", "", "", "PHY3_nINT",
69 "PHY1_nINT", "PHY3_nRESET", "PHY2_nINT", "PHY2_nRESET",
70 "PHY1_nRESET", "SPE1_PWR", "SPE0_PWR", "";
74 /* All this DP83TD510E PHYs can't be probed before switch@0 is
75 * probed so we need to use compatible with PHYid
78 t1l0_phy: ethernet-phy@6 {
79 compatible = "ethernet-phy-id2000.0181";
81 interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>;
82 reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>;
83 reset-assert-us = <10>;
84 reset-deassert-us = <35>;
88 t1l1_phy: ethernet-phy@7 {
89 compatible = "ethernet-phy-id2000.0181";
91 interrupts-extended = <&gpiog 8 IRQ_TYPE_LEVEL_LOW>;
92 reset-gpios = <&gpiog 12 GPIO_ACTIVE_LOW>;
93 reset-assert-us = <10>;
94 reset-deassert-us = <35>;
98 t1l2_phy: ethernet-phy@10 {
99 compatible = "ethernet-phy-id2000.0181";
101 interrupts-extended = <&gpiog 10 IRQ_TYPE_LEVEL_LOW>;
102 reset-gpios = <&gpiog 11 GPIO_ACTIVE_LOW>;
103 reset-assert-us = <10>;
104 reset-deassert-us = <35>;
108 rj45_phy: ethernet-phy@2 {
110 interrupts-extended = <&gpiog 7 IRQ_TYPE_LEVEL_LOW>;
111 reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
112 reset-assert-us = <10000>;
113 reset-deassert-us = <1000>;
115 clocks = <&clock_ksz9031>;
124 pinctrl-names = "default", "opendrain", "sleep";
125 pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
126 pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
127 pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
134 vmmc-supply = <®_3v3>;
135 vqmmc-supply = <®_3v3>;
139 &sdmmc2_b4_od_pins_a {
141 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
142 <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */
143 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
144 <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
150 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
151 <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */
152 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
153 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
154 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
158 &sdmmc2_b4_sleep_pins_a {
160 pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
161 <STM32_PINMUX('B', 7, ANALOG)>, /* SDMMC2_D1 */
162 <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
163 <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
164 <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
165 <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
171 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
172 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
173 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
174 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
178 &sdmmc2_d47_sleep_pins_a {
180 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
181 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
182 <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
183 <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
188 pinctrl-names = "default", "opendrain", "sleep";
189 pinctrl-0 = <&sdmmc3_b4_pins_b>;
190 pinctrl-1 = <&sdmmc3_b4_od_pins_b>;
191 pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>;
196 vmmc-supply = <®_3v3>;
197 vqmmc-supply = <®_3v3>;
198 mmc-pwrseq = <&wifi_pwrseq>;
199 #address-cells = <1>;
204 compatible = "prt,prtt1c-wfm200", "silabs,wf200";
209 &sdmmc3_b4_od_pins_b {
211 pinmux = <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */
212 <STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */
213 <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
214 <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
220 pinmux = <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */
221 <STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */
222 <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
223 <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
224 <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */
228 &sdmmc3_b4_sleep_pins_b {
230 pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* SDMMC3_D0 */
231 <STM32_PINMUX('D', 4, ANALOG)>, /* SDMMC3_D1 */
232 <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */
233 <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
234 <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
235 <STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */
240 pinctrl-0 = <&spi1_pins_b>;
241 pinctrl-names = "default";
242 cs-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
243 /delete-property/dmas;
244 /delete-property/dma-names;
248 compatible = "nxp,sja1105q";
250 spi-max-frequency = <4000000>;
251 spi-rx-delay-us = <1>;
252 spi-tx-delay-us = <1>;
255 reset-gpios = <&gpioe 6 GPIO_ACTIVE_LOW>;
257 clocks = <&clock_sja1105>;
260 #address-cells = <1>;
267 phy-handle = <&t1l0_phy>;
274 phy-handle = <&t1l1_phy>;
281 phy-handle = <&t1l2_phy>;
287 phy-handle = <&rj45_phy>;
288 phy-mode = "rgmii-id";
294 ethernet = <ðernet0>;