arch/arm/boot/dts/stm32mp151.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
   4  * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
   5  */
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/stm32mp1-clks.h>
   8 #include <dt-bindings/reset/stm32mp1-resets.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu0: cpu@0 {
  19                         compatible = "arm,cortex-a7";
  20                         clock-frequency = <650000000>;
  21                         device_type = "cpu";
  22                         reg = <0>;
  23                 };
  24         };
  25
  26         arm-pmu {
  27                 compatible = "arm,cortex-a7-pmu";
  28                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
  29                 interrupt-affinity = <&cpu0>;
  30                 interrupt-parent = <&intc>;
  31         };
  32
  33         psci {
  34                 compatible = "arm,psci-1.0";
  35                 method = "smc";
  36         };
  37
  38         intc: interrupt-controller@a0021000 {
  39                 compatible = "arm,cortex-a7-gic";
  40                 #interrupt-cells = <3>;
  41                 interrupt-controller;
  42                 reg = <0xa0021000 0x1000>,
  43                       <0xa0022000 0x2000>;
  44         };
  45
  46         timer {
  47                 compatible = "arm,armv7-timer";
  48                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  49                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  50                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  51                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
  52                 interrupt-parent = <&intc>;
  53         };
  54
  55         clocks {
  56                 clk_hse: clk-hse {
  57                         #clock-cells = <0>;
  58                         compatible = "fixed-clock";
  59                         clock-frequency = <24000000>;
  60                 };
  61
  62                 clk_hsi: clk-hsi {
  63                         #clock-cells = <0>;
  64                         compatible = "fixed-clock";
  65                         clock-frequency = <64000000>;
  66                 };
  67
  68                 clk_lse: clk-lse {
  69                         #clock-cells = <0>;
  70                         compatible = "fixed-clock";
  71                         clock-frequency = <32768>;
  72                 };
  73
  74                 clk_lsi: clk-lsi {
  75                         #clock-cells = <0>;
  76                         compatible = "fixed-clock";
  77                         clock-frequency = <32000>;
  78                 };
  79
  80                 clk_csi: clk-csi {
  81                         #clock-cells = <0>;
  82                         compatible = "fixed-clock";
  83                         clock-frequency = <4000000>;
  84                 };
  85         };
  86
  87         thermal-zones {
  88                 cpu_thermal: cpu-thermal {
  89                         polling-delay-passive = <0>;
  90                         polling-delay = <0>;
  91                         thermal-sensors = <&dts>;
  92
  93                         trips {
  94                                 cpu_alert1: cpu-alert1 {
  95                                         temperature = <85000>;
  96                                         hysteresis = <0>;
  97                                         type = "passive";
  98                                 };
  99
 100                                 cpu-crit {
 101                                         temperature = <120000>;
 102                                         hysteresis = <0>;
 103                                         type = "critical";
 104                                 };
 105                         };
 106
 107                         cooling-maps {
 108                         };
 109                 };
 110         };
 111
 112         booster: regulator-booster {
 113                 compatible = "st,stm32mp1-booster";
 114                 st,syscfg = <&syscfg>;
 115                 status = "disabled";
 116         };
 117
 118         soc {
 119                 compatible = "simple-bus";
 120                 #address-cells = <1>;
 121                 #size-cells = <1>;
 122                 interrupt-parent = <&intc>;
 123                 ranges;
 124
 125                 timers2: timer@40000000 {
 126                         #address-cells = <1>;
 127                         #size-cells = <0>;
 128                         compatible = "st,stm32-timers";
 129                         reg = <0x40000000 0x400>;
 130                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 131                         interrupt-names = "global";
 132                         clocks = <&rcc TIM2_K>;
 133                         clock-names = "int";
 134                         dmas = <&dmamux1 18 0x400 0x1>,
 135                                <&dmamux1 19 0x400 0x1>,
 136                                <&dmamux1 20 0x400 0x1>,
 137                                <&dmamux1 21 0x400 0x1>,
 138                                <&dmamux1 22 0x400 0x1>;
 139                         dma-names = "ch1", "ch2", "ch3", "ch4", "up";
 140                         status = "disabled";
 141
 142                         pwm {
 143                                 compatible = "st,stm32-pwm";
 144                                 #pwm-cells = <3>;
 145                                 status = "disabled";
 146                         };
 147
 148                         timer@1 {
 149                                 compatible = "st,stm32h7-timer-trigger";
 150                                 reg = <1>;
 151                                 status = "disabled";
 152                         };
 153
 154                         counter {
 155                                 compatible = "st,stm32-timer-counter";
 156                                 status = "disabled";
 157                         };
 158                 };
 159
 160                 timers3: timer@40001000 {
 161                         #address-cells = <1>;
 162                         #size-cells = <0>;
 163                         compatible = "st,stm32-timers";
 164                         reg = <0x40001000 0x400>;
 165                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 166                         interrupt-names = "global";
 167                         clocks = <&rcc TIM3_K>;
 168                         clock-names = "int";
 169                         dmas = <&dmamux1 23 0x400 0x1>,
 170                                <&dmamux1 24 0x400 0x1>,
 171                                <&dmamux1 25 0x400 0x1>,
 172                                <&dmamux1 26 0x400 0x1>,
 173                                <&dmamux1 27 0x400 0x1>,
 174                                <&dmamux1 28 0x400 0x1>;
 175                         dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
 176                         status = "disabled";
 177
 178                         pwm {
 179                                 compatible = "st,stm32-pwm";
 180                                 #pwm-cells = <3>;
 181                                 status = "disabled";
 182                         };
 183
 184                         timer@2 {
 185                                 compatible = "st,stm32h7-timer-trigger";
 186                                 reg = <2>;
 187                                 status = "disabled";
 188                         };
 189
 190                         counter {
 191                                 compatible = "st,stm32-timer-counter";
 192                                 status = "disabled";
 193                         };
 194                 };
 195
 196                 timers4: timer@40002000 {
 197                         #address-cells = <1>;
 198                         #size-cells = <0>;
 199                         compatible = "st,stm32-timers";
 200                         reg = <0x40002000 0x400>;
 201                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 202                         interrupt-names = "global";
 203                         clocks = <&rcc TIM4_K>;
 204                         clock-names = "int";
 205                         dmas = <&dmamux1 29 0x400 0x1>,
 206                                <&dmamux1 30 0x400 0x1>,
 207                                <&dmamux1 31 0x400 0x1>,
 208                                <&dmamux1 32 0x400 0x1>;
 209                         dma-names = "ch1", "ch2", "ch3", "ch4";
 210                         status = "disabled";
 211
 212                         pwm {
 213                                 compatible = "st,stm32-pwm";
 214                                 #pwm-cells = <3>;
 215                                 status = "disabled";
 216                         };
 217
 218                         timer@3 {
 219                                 compatible = "st,stm32h7-timer-trigger";
 220                                 reg = <3>;
 221                                 status = "disabled";
 222                         };
 223
 224                         counter {
 225                                 compatible = "st,stm32-timer-counter";
 226                                 status = "disabled";
 227                         };
 228                 };
 229
 230                 timers5: timer@40003000 {
 231                         #address-cells = <1>;
 232                         #size-cells = <0>;
 233                         compatible = "st,stm32-timers";
 234                         reg = <0x40003000 0x400>;
 235                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 236                         interrupt-names = "global";
 237                         clocks = <&rcc TIM5_K>;
 238                         clock-names = "int";
 239                         dmas = <&dmamux1 55 0x400 0x1>,
 240                                <&dmamux1 56 0x400 0x1>,
 241                                <&dmamux1 57 0x400 0x1>,
 242                                <&dmamux1 58 0x400 0x1>,
 243                                <&dmamux1 59 0x400 0x1>,
 244                                <&dmamux1 60 0x400 0x1>;
 245                         dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
 246                         status = "disabled";
 247
 248                         pwm {
 249                                 compatible = "st,stm32-pwm";
 250                                 #pwm-cells = <3>;
 251                                 status = "disabled";
 252                         };
 253
 254                         timer@4 {
 255                                 compatible = "st,stm32h7-timer-trigger";
 256                                 reg = <4>;
 257                                 status = "disabled";
 258                         };
 259
 260                         counter {
 261                                 compatible = "st,stm32-timer-counter";
 262                                 status = "disabled";
 263                         };
 264                 };
 265
 266                 timers6: timer@40004000 {
 267                         #address-cells = <1>;
 268                         #size-cells = <0>;
 269                         compatible = "st,stm32-timers";
 270                         reg = <0x40004000 0x400>;
 271                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 272                         interrupt-names = "global";
 273                         clocks = <&rcc TIM6_K>;
 274                         clock-names = "int";
 275                         dmas = <&dmamux1 69 0x400 0x1>;
 276                         dma-names = "up";
 277                         status = "disabled";
 278
 279                         timer@5 {
 280                                 compatible = "st,stm32h7-timer-trigger";
 281                                 reg = <5>;
 282                                 status = "disabled";
 283                         };
 284                 };
 285
 286                 timers7: timer@40005000 {
 287                         #address-cells = <1>;
 288                         #size-cells = <0>;
 289                         compatible = "st,stm32-timers";
 290                         reg = <0x40005000 0x400>;
 291                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 292                         interrupt-names = "global";
 293                         clocks = <&rcc TIM7_K>;
 294                         clock-names = "int";
 295                         dmas = <&dmamux1 70 0x400 0x1>;
 296                         dma-names = "up";
 297                         status = "disabled";
 298
 299                         timer@6 {
 300                                 compatible = "st,stm32h7-timer-trigger";
 301                                 reg = <6>;
 302                                 status = "disabled";
 303                         };
 304                 };
 305
 306                 timers12: timer@40006000 {
 307                         #address-cells = <1>;
 308                         #size-cells = <0>;
 309                         compatible = "st,stm32-timers";
 310                         reg = <0x40006000 0x400>;
 311                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 312                         interrupt-names = "global";
 313                         clocks = <&rcc TIM12_K>;
 314                         clock-names = "int";
 315                         status = "disabled";
 316
 317                         pwm {
 318                                 compatible = "st,stm32-pwm";
 319                                 #pwm-cells = <3>;
 320                                 status = "disabled";
 321                         };
 322
 323                         timer@11 {
 324                                 compatible = "st,stm32h7-timer-trigger";
 325                                 reg = <11>;
 326                                 status = "disabled";
 327                         };
 328                 };
 329
 330                 timers13: timer@40007000 {
 331                         #address-cells = <1>;
 332                         #size-cells = <0>;
 333                         compatible = "st,stm32-timers";
 334                         reg = <0x40007000 0x400>;
 335                         interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
 336                         interrupt-names = "global";
 337                         clocks = <&rcc TIM13_K>;
 338                         clock-names = "int";
 339                         status = "disabled";
 340
 341                         pwm {
 342                                 compatible = "st,stm32-pwm";
 343                                 #pwm-cells = <3>;
 344                                 status = "disabled";
 345                         };
 346
 347                         timer@12 {
 348                                 compatible = "st,stm32h7-timer-trigger";
 349                                 reg = <12>;
 350                                 status = "disabled";
 351                         };
 352                 };
 353
 354                 timers14: timer@40008000 {
 355                         #address-cells = <1>;
 356                         #size-cells = <0>;
 357                         compatible = "st,stm32-timers";
 358                         reg = <0x40008000 0x400>;
 359                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
 360                         interrupt-names = "global";
 361                         clocks = <&rcc TIM14_K>;
 362                         clock-names = "int";
 363                         status = "disabled";
 364
 365                         pwm {
 366                                 compatible = "st,stm32-pwm";
 367                                 #pwm-cells = <3>;
 368                                 status = "disabled";
 369                         };
 370
 371                         timer@13 {
 372                                 compatible = "st,stm32h7-timer-trigger";
 373                                 reg = <13>;
 374                                 status = "disabled";
 375                         };
 376                 };
 377
 378                 lptimer1: timer@40009000 {
 379                         #address-cells = <1>;
 380                         #size-cells = <0>;
 381                         compatible = "st,stm32-lptimer";
 382                         reg = <0x40009000 0x400>;
 383                         interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
 384                         clocks = <&rcc LPTIM1_K>;
 385                         clock-names = "mux";
 386                         wakeup-source;
 387                         status = "disabled";
 388
 389                         pwm {
 390                                 compatible = "st,stm32-pwm-lp";
 391                                 #pwm-cells = <3>;
 392                                 status = "disabled";
 393                         };
 394
 395                         trigger@0 {
 396                                 compatible = "st,stm32-lptimer-trigger";
 397                                 reg = <0>;
 398                                 status = "disabled";
 399                         };
 400
 401                         counter {
 402                                 compatible = "st,stm32-lptimer-counter";
 403                                 status = "disabled";
 404                         };
 405                 };
 406
 407                 spi2: spi@4000b000 {
 408                         #address-cells = <1>;
 409                         #size-cells = <0>;
 410                         compatible = "st,stm32h7-spi";
 411                         reg = <0x4000b000 0x400>;
 412                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 413                         clocks = <&rcc SPI2_K>;
 414                         resets = <&rcc SPI2_R>;
 415                         dmas = <&dmamux1 39 0x400 0x05>,
 416                                <&dmamux1 40 0x400 0x05>;
 417                         dma-names = "rx", "tx";
 418                         status = "disabled";
 419                 };
 420
 421                 i2s2: audio-controller@4000b000 {
 422                         compatible = "st,stm32h7-i2s";
 423                         #sound-dai-cells = <0>;
 424                         reg = <0x4000b000 0x400>;
 425                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 426                         dmas = <&dmamux1 39 0x400 0x01>,
 427                                <&dmamux1 40 0x400 0x01>;
 428                         dma-names = "rx", "tx";
 429                         status = "disabled";
 430                 };
 431
 432                 spi3: spi@4000c000 {
 433                         #address-cells = <1>;
 434                         #size-cells = <0>;
 435                         compatible = "st,stm32h7-spi";
 436                         reg = <0x4000c000 0x400>;
 437                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 438                         clocks = <&rcc SPI3_K>;
 439                         resets = <&rcc SPI3_R>;
 440                         dmas = <&dmamux1 61 0x400 0x05>,
 441                                <&dmamux1 62 0x400 0x05>;
 442                         dma-names = "rx", "tx";
 443                         status = "disabled";
 444                 };
 445
 446                 i2s3: audio-controller@4000c000 {
 447                         compatible = "st,stm32h7-i2s";
 448                         #sound-dai-cells = <0>;
 449                         reg = <0x4000c000 0x400>;
 450                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 451                         dmas = <&dmamux1 61 0x400 0x01>,
 452                                <&dmamux1 62 0x400 0x01>;
 453                         dma-names = "rx", "tx";
 454                         status = "disabled";
 455                 };
 456
 457                 spdifrx: audio-controller@4000d000 {
 458                         compatible = "st,stm32h7-spdifrx";
 459                         #sound-dai-cells = <0>;
 460                         reg = <0x4000d000 0x400>;
 461                         clocks = <&rcc SPDIF_K>;
 462                         clock-names = "kclk";
 463                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 464                         dmas = <&dmamux1 93 0x400 0x01>,
 465                                <&dmamux1 94 0x400 0x01>;
 466                         dma-names = "rx", "rx-ctrl";
 467                         status = "disabled";
 468                 };
 469
 470                 usart2: serial@4000e000 {
 471                         compatible = "st,stm32h7-uart";
 472                         reg = <0x4000e000 0x400>;
 473                         interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
 474                         clocks = <&rcc USART2_K>;
 475                         wakeup-source;
 476                         dmas = <&dmamux1 43 0x400 0x15>,
 477                                <&dmamux1 44 0x400 0x11>;
 478                         dma-names = "rx", "tx";
 479                         status = "disabled";
 480                 };
 481
 482                 usart3: serial@4000f000 {
 483                         compatible = "st,stm32h7-uart";
 484                         reg = <0x4000f000 0x400>;
 485                         interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
 486                         clocks = <&rcc USART3_K>;
 487                         wakeup-source;
 488                         dmas = <&dmamux1 45 0x400 0x15>,
 489                                <&dmamux1 46 0x400 0x11>;
 490                         dma-names = "rx", "tx";
 491                         status = "disabled";
 492                 };
 493
 494                 uart4: serial@40010000 {
 495                         compatible = "st,stm32h7-uart";
 496                         reg = <0x40010000 0x400>;
 497                         interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
 498                         clocks = <&rcc UART4_K>;
 499                         wakeup-source;
 500                         dmas = <&dmamux1 63 0x400 0x15>,
 501                                <&dmamux1 64 0x400 0x11>;
 502                         dma-names = "rx", "tx";
 503                         status = "disabled";
 504                 };
 505
 506                 uart5: serial@40011000 {
 507                         compatible = "st,stm32h7-uart";
 508                         reg = <0x40011000 0x400>;
 509                         interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
 510                         clocks = <&rcc UART5_K>;
 511                         wakeup-source;
 512                         dmas = <&dmamux1 65 0x400 0x15>,
 513                                <&dmamux1 66 0x400 0x11>;
 514                         dma-names = "rx", "tx";
 515                         status = "disabled";
 516                 };
 517
 518                 i2c1: i2c@40012000 {
 519                         compatible = "st,stm32mp15-i2c";
 520                         reg = <0x40012000 0x400>;
 521                         interrupt-names = "event", "error";
 522                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 523                                      <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 524                         clocks = <&rcc I2C1_K>;
 525                         resets = <&rcc I2C1_R>;
 526                         #address-cells = <1>;
 527                         #size-cells = <0>;
 528                         st,syscfg-fmp = <&syscfg 0x4 0x1>;
 529                         wakeup-source;
 530                         i2c-analog-filter;
 531                         status = "disabled";
 532                 };
 533
 534                 i2c2: i2c@40013000 {
 535                         compatible = "st,stm32mp15-i2c";
 536                         reg = <0x40013000 0x400>;
 537                         interrupt-names = "event", "error";
 538                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 539                                      <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 540                         clocks = <&rcc I2C2_K>;
 541                         resets = <&rcc I2C2_R>;
 542                         #address-cells = <1>;
 543                         #size-cells = <0>;
 544                         st,syscfg-fmp = <&syscfg 0x4 0x2>;
 545                         wakeup-source;
 546                         i2c-analog-filter;
 547                         status = "disabled";
 548                 };
 549
 550                 i2c3: i2c@40014000 {
 551                         compatible = "st,stm32mp15-i2c";
 552                         reg = <0x40014000 0x400>;
 553                         interrupt-names = "event", "error";
 554                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 555                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 556                         clocks = <&rcc I2C3_K>;
 557                         resets = <&rcc I2C3_R>;
 558                         #address-cells = <1>;
 559                         #size-cells = <0>;
 560                         st,syscfg-fmp = <&syscfg 0x4 0x4>;
 561                         wakeup-source;
 562                         i2c-analog-filter;
 563                         status = "disabled";
 564                 };
 565
 566                 i2c5: i2c@40015000 {
 567                         compatible = "st,stm32mp15-i2c";
 568                         reg = <0x40015000 0x400>;
 569                         interrupt-names = "event", "error";
 570                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 571                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 572                         clocks = <&rcc I2C5_K>;
 573                         resets = <&rcc I2C5_R>;
 574                         #address-cells = <1>;
 575                         #size-cells = <0>;
 576                         st,syscfg-fmp = <&syscfg 0x4 0x10>;
 577                         wakeup-source;
 578                         i2c-analog-filter;
 579                         status = "disabled";
 580                 };
 581
 582                 cec: cec@40016000 {
 583                         compatible = "st,stm32-cec";
 584                         reg = <0x40016000 0x400>;
 585                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 586                         clocks = <&rcc CEC_K>, <&rcc CEC>;
 587                         clock-names = "cec", "hdmi-cec";
 588                         status = "disabled";
 589                 };
 590
 591                 dac: dac@40017000 {
 592                         compatible = "st,stm32h7-dac-core";
 593                         reg = <0x40017000 0x400>;
 594                         clocks = <&rcc DAC12>;
 595                         clock-names = "pclk";
 596                         #address-cells = <1>;
 597                         #size-cells = <0>;
 598                         status = "disabled";
 599
 600                         dac1: dac@1 {
 601                                 compatible = "st,stm32-dac";
 602                                 #io-channel-cells = <1>;
 603                                 reg = <1>;
 604                                 status = "disabled";
 605                         };
 606
 607                         dac2: dac@2 {
 608                                 compatible = "st,stm32-dac";
 609                                 #io-channel-cells = <1>;
 610                                 reg = <2>;
 611                                 status = "disabled";
 612                         };
 613                 };
 614
 615                 uart7: serial@40018000 {
 616                         compatible = "st,stm32h7-uart";
 617                         reg = <0x40018000 0x400>;
 618                         interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
 619                         clocks = <&rcc UART7_K>;
 620                         wakeup-source;
 621                         dmas = <&dmamux1 79 0x400 0x15>,
 622                                <&dmamux1 80 0x400 0x11>;
 623                         dma-names = "rx", "tx";
 624                         status = "disabled";
 625                 };
 626
 627                 uart8: serial@40019000 {
 628                         compatible = "st,stm32h7-uart";
 629                         reg = <0x40019000 0x400>;
 630                         interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
 631                         clocks = <&rcc UART8_K>;
 632                         wakeup-source;
 633                         dmas = <&dmamux1 81 0x400 0x15>,
 634                                <&dmamux1 82 0x400 0x11>;
 635                         dma-names = "rx", "tx";
 636                         status = "disabled";
 637                 };
 638
 639                 timers1: timer@44000000 {
 640                         #address-cells = <1>;
 641                         #size-cells = <0>;
 642                         compatible = "st,stm32-timers";
 643                         reg = <0x44000000 0x400>;
 644                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
 645                                      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
 646                                      <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 647                                      <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 648                         interrupt-names = "brk", "up", "trg-com", "cc";
 649                         clocks = <&rcc TIM1_K>;
 650                         clock-names = "int";
 651                         dmas = <&dmamux1 11 0x400 0x1>,
 652                                <&dmamux1 12 0x400 0x1>,
 653                                <&dmamux1 13 0x400 0x1>,
 654                                <&dmamux1 14 0x400 0x1>,
 655                                <&dmamux1 15 0x400 0x1>,
 656                                <&dmamux1 16 0x400 0x1>,
 657                                <&dmamux1 17 0x400 0x1>;
 658                         dma-names = "ch1", "ch2", "ch3", "ch4",
 659                                     "up", "trig", "com";
 660                         status = "disabled";
 661
 662                         pwm {
 663                                 compatible = "st,stm32-pwm";
 664                                 #pwm-cells = <3>;
 665                                 status = "disabled";
 666                         };
 667
 668                         timer@0 {
 669                                 compatible = "st,stm32h7-timer-trigger";
 670                                 reg = <0>;
 671                                 status = "disabled";
 672                         };
 673
 674                         counter {
 675                                 compatible = "st,stm32-timer-counter";
 676                                 status = "disabled";
 677                         };
 678                 };
 679
 680                 timers8: timer@44001000 {
 681                         #address-cells = <1>;
 682                         #size-cells = <0>;
 683                         compatible = "st,stm32-timers";
 684                         reg = <0x44001000 0x400>;
 685                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 686                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 687                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 688                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 689                         interrupt-names = "brk", "up", "trg-com", "cc";
 690                         clocks = <&rcc TIM8_K>;
 691                         clock-names = "int";
 692                         dmas = <&dmamux1 47 0x400 0x1>,
 693                                <&dmamux1 48 0x400 0x1>,
 694                                <&dmamux1 49 0x400 0x1>,
 695                                <&dmamux1 50 0x400 0x1>,
 696                                <&dmamux1 51 0x400 0x1>,
 697                                <&dmamux1 52 0x400 0x1>,
 698                                <&dmamux1 53 0x400 0x1>;
 699                         dma-names = "ch1", "ch2", "ch3", "ch4",
 700                                     "up", "trig", "com";
 701                         status = "disabled";
 702
 703                         pwm {
 704                                 compatible = "st,stm32-pwm";
 705                                 #pwm-cells = <3>;
 706                                 status = "disabled";
 707                         };
 708
 709                         timer@7 {
 710                                 compatible = "st,stm32h7-timer-trigger";
 711                                 reg = <7>;
 712                                 status = "disabled";
 713                         };
 714
 715                         counter {
 716                                 compatible = "st,stm32-timer-counter";
 717                                 status = "disabled";
 718                         };
 719                 };
 720
 721                 usart6: serial@44003000 {
 722                         compatible = "st,stm32h7-uart";
 723                         reg = <0x44003000 0x400>;
 724                         interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
 725                         clocks = <&rcc USART6_K>;
 726                         wakeup-source;
 727                         dmas = <&dmamux1 71 0x400 0x15>,
 728                                <&dmamux1 72 0x400 0x11>;
 729                         dma-names = "rx", "tx";
 730                         status = "disabled";
 731                 };
 732
 733                 spi1: spi@44004000 {
 734                         #address-cells = <1>;
 735                         #size-cells = <0>;
 736                         compatible = "st,stm32h7-spi";
 737                         reg = <0x44004000 0x400>;
 738                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 739                         clocks = <&rcc SPI1_K>;
 740                         resets = <&rcc SPI1_R>;
 741                         dmas = <&dmamux1 37 0x400 0x05>,
 742                                <&dmamux1 38 0x400 0x05>;
 743                         dma-names = "rx", "tx";
 744                         status = "disabled";
 745                 };
 746
 747                 i2s1: audio-controller@44004000 {
 748                         compatible = "st,stm32h7-i2s";
 749                         #sound-dai-cells = <0>;
 750                         reg = <0x44004000 0x400>;
 751                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 752                         dmas = <&dmamux1 37 0x400 0x01>,
 753                                <&dmamux1 38 0x400 0x01>;
 754                         dma-names = "rx", "tx";
 755                         status = "disabled";
 756                 };
 757
 758                 spi4: spi@44005000 {
 759                         #address-cells = <1>;
 760                         #size-cells = <0>;
 761                         compatible = "st,stm32h7-spi";
 762                         reg = <0x44005000 0x400>;
 763                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 764                         clocks = <&rcc SPI4_K>;
 765                         resets = <&rcc SPI4_R>;
 766                         dmas = <&dmamux1 83 0x400 0x05>,
 767                                <&dmamux1 84 0x400 0x05>;
 768                         dma-names = "rx", "tx";
 769                         status = "disabled";
 770                 };
 771
 772                 timers15: timer@44006000 {
 773                         #address-cells = <1>;
 774                         #size-cells = <0>;
 775                         compatible = "st,stm32-timers";
 776                         reg = <0x44006000 0x400>;
 777                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 778                         interrupt-names = "global";
 779                         clocks = <&rcc TIM15_K>;
 780                         clock-names = "int";
 781                         dmas = <&dmamux1 105 0x400 0x1>,
 782                                <&dmamux1 106 0x400 0x1>,
 783                                <&dmamux1 107 0x400 0x1>,
 784                                <&dmamux1 108 0x400 0x1>;
 785                         dma-names = "ch1", "up", "trig", "com";
 786                         status = "disabled";
 787
 788                         pwm {
 789                                 compatible = "st,stm32-pwm";
 790                                 #pwm-cells = <3>;
 791                                 status = "disabled";
 792                         };
 793
 794                         timer@14 {
 795                                 compatible = "st,stm32h7-timer-trigger";
 796                                 reg = <14>;
 797                                 status = "disabled";
 798                         };
 799                 };
 800
 801                 timers16: timer@44007000 {
 802                         #address-cells = <1>;
 803                         #size-cells = <0>;
 804                         compatible = "st,stm32-timers";
 805                         reg = <0x44007000 0x400>;
 806                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 807                         interrupt-names = "global";
 808                         clocks = <&rcc TIM16_K>;
 809                         clock-names = "int";
 810                         dmas = <&dmamux1 109 0x400 0x1>,
 811                                <&dmamux1 110 0x400 0x1>;
 812                         dma-names = "ch1", "up";
 813                         status = "disabled";
 814
 815                         pwm {
 816                                 compatible = "st,stm32-pwm";
 817                                 #pwm-cells = <3>;
 818                                 status = "disabled";
 819                         };
 820                         timer@15 {
 821                                 compatible = "st,stm32h7-timer-trigger";
 822                                 reg = <15>;
 823                                 status = "disabled";
 824                         };
 825                 };
 826
 827                 timers17: timer@44008000 {
 828                         #address-cells = <1>;
 829                         #size-cells = <0>;
 830                         compatible = "st,stm32-timers";
 831                         reg = <0x44008000 0x400>;
 832                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 833                         interrupt-names = "global";
 834                         clocks = <&rcc TIM17_K>;
 835                         clock-names = "int";
 836                         dmas = <&dmamux1 111 0x400 0x1>,
 837                                <&dmamux1 112 0x400 0x1>;
 838                         dma-names = "ch1", "up";
 839                         status = "disabled";
 840
 841                         pwm {
 842                                 compatible = "st,stm32-pwm";
 843                                 #pwm-cells = <3>;
 844                                 status = "disabled";
 845                         };
 846
 847                         timer@16 {
 848                                 compatible = "st,stm32h7-timer-trigger";
 849                                 reg = <16>;
 850                                 status = "disabled";
 851                         };
 852                 };
 853
 854                 spi5: spi@44009000 {
 855                         #address-cells = <1>;
 856                         #size-cells = <0>;
 857                         compatible = "st,stm32h7-spi";
 858                         reg = <0x44009000 0x400>;
 859                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 860                         clocks = <&rcc SPI5_K>;
 861                         resets = <&rcc SPI5_R>;
 862                         dmas = <&dmamux1 85 0x400 0x05>,
 863                                <&dmamux1 86 0x400 0x05>;
 864                         dma-names = "rx", "tx";
 865                         status = "disabled";
 866                 };
 867
 868                 sai1: sai@4400a000 {
 869                         compatible = "st,stm32h7-sai";
 870                         #address-cells = <1>;
 871                         #size-cells = <1>;
 872                         ranges = <0 0x4400a000 0x400>;
 873                         reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
 874                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 875                         resets = <&rcc SAI1_R>;
 876                         status = "disabled";
 877
 878                         sai1a: audio-controller@4400a004 {
 879                                 #sound-dai-cells = <0>;
 880
 881                                 compatible = "st,stm32-sai-sub-a";
 882                                 reg = <0x4 0x20>;
 883                                 clocks = <&rcc SAI1_K>;
 884                                 clock-names = "sai_ck";
 885                                 dmas = <&dmamux1 87 0x400 0x01>;
 886                                 status = "disabled";
 887                         };
 888
 889                         sai1b: audio-controller@4400a024 {
 890                                 #sound-dai-cells = <0>;
 891                                 compatible = "st,stm32-sai-sub-b";
 892                                 reg = <0x24 0x20>;
 893                                 clocks = <&rcc SAI1_K>;
 894                                 clock-names = "sai_ck";
 895                                 dmas = <&dmamux1 88 0x400 0x01>;
 896                                 status = "disabled";
 897                         };
 898                 };
 899
 900                 sai2: sai@4400b000 {
 901                         compatible = "st,stm32h7-sai";
 902                         #address-cells = <1>;
 903                         #size-cells = <1>;
 904                         ranges = <0 0x4400b000 0x400>;
 905                         reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
 906                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 907                         resets = <&rcc SAI2_R>;
 908                         status = "disabled";
 909
 910                         sai2a: audio-controller@4400b004 {
 911                                 #sound-dai-cells = <0>;
 912                                 compatible = "st,stm32-sai-sub-a";
 913                                 reg = <0x4 0x20>;
 914                                 clocks = <&rcc SAI2_K>;
 915                                 clock-names = "sai_ck";
 916                                 dmas = <&dmamux1 89 0x400 0x01>;
 917                                 status = "disabled";
 918                         };
 919
 920                         sai2b: audio-controller@4400b024 {
 921                                 #sound-dai-cells = <0>;
 922                                 compatible = "st,stm32-sai-sub-b";
 923                                 reg = <0x24 0x20>;
 924                                 clocks = <&rcc SAI2_K>;
 925                                 clock-names = "sai_ck";
 926                                 dmas = <&dmamux1 90 0x400 0x01>;
 927                                 status = "disabled";
 928                         };
 929                 };
 930
 931                 sai3: sai@4400c000 {
 932                         compatible = "st,stm32h7-sai";
 933                         #address-cells = <1>;
 934                         #size-cells = <1>;
 935                         ranges = <0 0x4400c000 0x400>;
 936                         reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
 937                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 938                         resets = <&rcc SAI3_R>;
 939                         status = "disabled";
 940
 941                         sai3a: audio-controller@4400c004 {
 942                                 #sound-dai-cells = <0>;
 943                                 compatible = "st,stm32-sai-sub-a";
 944                                 reg = <0x04 0x20>;
 945                                 clocks = <&rcc SAI3_K>;
 946                                 clock-names = "sai_ck";
 947                                 dmas = <&dmamux1 113 0x400 0x01>;
 948                                 status = "disabled";
 949                         };
 950
 951                         sai3b: audio-controller@4400c024 {
 952                                 #sound-dai-cells = <0>;
 953                                 compatible = "st,stm32-sai-sub-b";
 954                                 reg = <0x24 0x20>;
 955                                 clocks = <&rcc SAI3_K>;
 956                                 clock-names = "sai_ck";
 957                                 dmas = <&dmamux1 114 0x400 0x01>;
 958                                 status = "disabled";
 959                         };
 960                 };
 961
 962                 dfsdm: dfsdm@4400d000 {
 963                         compatible = "st,stm32mp1-dfsdm";
 964                         reg = <0x4400d000 0x800>;
 965                         clocks = <&rcc DFSDM_K>;
 966                         clock-names = "dfsdm";
 967                         #address-cells = <1>;
 968                         #size-cells = <0>;
 969                         status = "disabled";
 970
 971                         dfsdm0: filter@0 {
 972                                 compatible = "st,stm32-dfsdm-adc";
 973                                 #io-channel-cells = <1>;
 974                                 reg = <0>;
 975                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 976                                 dmas = <&dmamux1 101 0x400 0x01>;
 977                                 dma-names = "rx";
 978                                 status = "disabled";
 979                         };
 980
 981                         dfsdm1: filter@1 {
 982                                 compatible = "st,stm32-dfsdm-adc";
 983                                 #io-channel-cells = <1>;
 984                                 reg = <1>;
 985                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 986                                 dmas = <&dmamux1 102 0x400 0x01>;
 987                                 dma-names = "rx";
 988                                 status = "disabled";
 989                         };
 990
 991                         dfsdm2: filter@2 {
 992                                 compatible = "st,stm32-dfsdm-adc";
 993                                 #io-channel-cells = <1>;
 994                                 reg = <2>;
 995                                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 996                                 dmas = <&dmamux1 103 0x400 0x01>;
 997                                 dma-names = "rx";
 998                                 status = "disabled";
 999                         };
1000
1001                         dfsdm3: filter@3 {
1002                                 compatible = "st,stm32-dfsdm-adc";
1003                                 #io-channel-cells = <1>;
1004                                 reg = <3>;
1005                                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1006                                 dmas = <&dmamux1 104 0x400 0x01>;
1007                                 dma-names = "rx";
1008                                 status = "disabled";
1009                         };
1010
1011                         dfsdm4: filter@4 {
1012                                 compatible = "st,stm32-dfsdm-adc";
1013                                 #io-channel-cells = <1>;
1014                                 reg = <4>;
1015                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1016                                 dmas = <&dmamux1 91 0x400 0x01>;
1017                                 dma-names = "rx";
1018                                 status = "disabled";
1019                         };
1020
1021                         dfsdm5: filter@5 {
1022                                 compatible = "st,stm32-dfsdm-adc";
1023                                 #io-channel-cells = <1>;
1024                                 reg = <5>;
1025                                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1026                                 dmas = <&dmamux1 92 0x400 0x01>;
1027                                 dma-names = "rx";
1028                                 status = "disabled";
1029                         };
1030                 };
1031
1032                 dma1: dma-controller@48000000 {
1033                         compatible = "st,stm32-dma";
1034                         reg = <0x48000000 0x400>;
1035                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
1036                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1037                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
1038                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1039                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
1040                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1041                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
1042                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1043                         clocks = <&rcc DMA1>;
1044                         resets = <&rcc DMA1_R>;
1045                         #dma-cells = <4>;
1046                         st,mem2mem;
1047                         dma-requests = <8>;
1048                 };
1049
1050                 dma2: dma-controller@48001000 {
1051                         compatible = "st,stm32-dma";
1052                         reg = <0x48001000 0x400>;
1053                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1054                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1055                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1056                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1057                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1058                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1059                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1060                                      <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1061                         clocks = <&rcc DMA2>;
1062                         resets = <&rcc DMA2_R>;
1063                         #dma-cells = <4>;
1064                         st,mem2mem;
1065                         dma-requests = <8>;
1066                 };
1067
1068                 dmamux1: dma-router@48002000 {
1069                         compatible = "st,stm32h7-dmamux";
1070                         reg = <0x48002000 0x40>;
1071                         #dma-cells = <3>;
1072                         dma-requests = <128>;
1073                         dma-masters = <&dma1 &dma2>;
1074                         dma-channels = <16>;
1075                         clocks = <&rcc DMAMUX>;
1076                         resets = <&rcc DMAMUX_R>;
1077                 };
1078
1079                 adc: adc@48003000 {
1080                         compatible = "st,stm32mp1-adc-core";
1081                         reg = <0x48003000 0x400>;
1082                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1083                                      <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1084                         clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1085                         clock-names = "bus", "adc";
1086                         interrupt-controller;
1087                         st,syscfg = <&syscfg>;
1088                         #interrupt-cells = <1>;
1089                         #address-cells = <1>;
1090                         #size-cells = <0>;
1091                         status = "disabled";
1092
1093                         adc1: adc@0 {
1094                                 compatible = "st,stm32mp1-adc";
1095                                 #io-channel-cells = <1>;
1096                                 reg = <0x0>;
1097                                 interrupt-parent = <&adc>;
1098                                 interrupts = <0>;
1099                                 dmas = <&dmamux1 9 0x400 0x01>;
1100                                 dma-names = "rx";
1101                                 status = "disabled";
1102                         };
1103
1104                         adc2: adc@100 {
1105                                 compatible = "st,stm32mp1-adc";
1106                                 #io-channel-cells = <1>;
1107                                 reg = <0x100>;
1108                                 interrupt-parent = <&adc>;
1109                                 interrupts = <1>;
1110                                 dmas = <&dmamux1 10 0x400 0x01>;
1111                                 dma-names = "rx";
1112                                 status = "disabled";
1113                         };
1114                 };
1115
1116                 sdmmc3: mmc@48004000 {
1117                         compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1118                         arm,primecell-periphid = <0x00253180>;
1119                         reg = <0x48004000 0x400>;
1120                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1121                         interrupt-names = "cmd_irq";
1122                         clocks = <&rcc SDMMC3_K>;
1123                         clock-names = "apb_pclk";
1124                         resets = <&rcc SDMMC3_R>;
1125                         cap-sd-highspeed;
1126                         cap-mmc-highspeed;
1127                         max-frequency = <120000000>;
1128                         status = "disabled";
1129                 };
1130
1131                 usbotg_hs: usb-otg@49000000 {
1132                         compatible = "st,stm32mp15-hsotg", "snps,dwc2";
1133                         reg = <0x49000000 0x10000>;
1134                         clocks = <&rcc USBO_K>;
1135                         clock-names = "otg";
1136                         resets = <&rcc USBO_R>;
1137                         reset-names = "dwc2";
1138                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1139                         g-rx-fifo-size = <512>;
1140                         g-np-tx-fifo-size = <32>;
1141                         g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
1142                         dr_mode = "otg";
1143                         otg-rev = <0x200>;
1144                         usb33d-supply = <&usb33>;
1145                         status = "disabled";
1146                 };
1147
1148                 ipcc: mailbox@4c001000 {
1149                         compatible = "st,stm32mp1-ipcc";
1150                         #mbox-cells = <1>;
1151                         reg = <0x4c001000 0x400>;
1152                         st,proc-id = <0>;
1153                         interrupts-extended =
1154                                 <&exti 61 1>,
1155                                 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1156                         interrupt-names = "rx", "tx";
1157                         clocks = <&rcc IPCC>;
1158                         wakeup-source;
1159                         status = "disabled";
1160                 };
1161
1162                 dcmi: dcmi@4c006000 {
1163                         compatible = "st,stm32-dcmi";
1164                         reg = <0x4c006000 0x400>;
1165                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1166                         resets = <&rcc CAMITF_R>;
1167                         clocks = <&rcc DCMI>;
1168                         clock-names = "mclk";
1169                         dmas = <&dmamux1 75 0x400 0x01>;
1170                         dma-names = "tx";
1171                         status = "disabled";
1172                 };
1173
1174                 rcc: rcc@50000000 {
1175                         compatible = "st,stm32mp1-rcc", "syscon";
1176                         reg = <0x50000000 0x1000>;
1177                         #clock-cells = <1>;
1178                         #reset-cells = <1>;
1179                 };
1180
1181                 pwr_regulators: pwr@50001000 {
1182                         compatible = "st,stm32mp1,pwr-reg";
1183                         reg = <0x50001000 0x10>;
1184
1185                         reg11: reg11 {
1186                                 regulator-name = "reg11";
1187                                 regulator-min-microvolt = <1100000>;
1188                                 regulator-max-microvolt = <1100000>;
1189                         };
1190
1191                         reg18: reg18 {
1192                                 regulator-name = "reg18";
1193                                 regulator-min-microvolt = <1800000>;
1194                                 regulator-max-microvolt = <1800000>;
1195                         };
1196
1197                         usb33: usb33 {
1198                                 regulator-name = "usb33";
1199                                 regulator-min-microvolt = <3300000>;
1200                                 regulator-max-microvolt = <3300000>;
1201                         };
1202                 };
1203
1204                 pwr_mcu: pwr_mcu@50001014 {
1205                         compatible = "st,stm32mp151-pwr-mcu", "syscon";
1206                         reg = <0x50001014 0x4>;
1207                 };
1208
1209                 exti: interrupt-controller@5000d000 {
1210                         compatible = "st,stm32mp1-exti", "syscon";
1211                         interrupt-controller;
1212                         #interrupt-cells = <2>;
1213                         reg = <0x5000d000 0x400>;
1214                 };
1215
1216                 syscfg: syscon@50020000 {
1217                         compatible = "st,stm32mp157-syscfg", "syscon";
1218                         reg = <0x50020000 0x400>;
1219                         clocks = <&rcc SYSCFG>;
1220                 };
1221
1222                 lptimer2: timer@50021000 {
1223                         #address-cells = <1>;
1224                         #size-cells = <0>;
1225                         compatible = "st,stm32-lptimer";
1226                         reg = <0x50021000 0x400>;
1227                         interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
1228                         clocks = <&rcc LPTIM2_K>;
1229                         clock-names = "mux";
1230                         wakeup-source;
1231                         status = "disabled";
1232
1233                         pwm {
1234                                 compatible = "st,stm32-pwm-lp";
1235                                 #pwm-cells = <3>;
1236                                 status = "disabled";
1237                         };
1238
1239                         trigger@1 {
1240                                 compatible = "st,stm32-lptimer-trigger";
1241                                 reg = <1>;
1242                                 status = "disabled";
1243                         };
1244
1245                         counter {
1246                                 compatible = "st,stm32-lptimer-counter";
1247                                 status = "disabled";
1248                         };
1249                 };
1250
1251                 lptimer3: timer@50022000 {
1252                         #address-cells = <1>;
1253                         #size-cells = <0>;
1254                         compatible = "st,stm32-lptimer";
1255                         reg = <0x50022000 0x400>;
1256                         interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
1257                         clocks = <&rcc LPTIM3_K>;
1258                         clock-names = "mux";
1259                         wakeup-source;
1260                         status = "disabled";
1261
1262                         pwm {
1263                                 compatible = "st,stm32-pwm-lp";
1264                                 #pwm-cells = <3>;
1265                                 status = "disabled";
1266                         };
1267
1268                         trigger@2 {
1269                                 compatible = "st,stm32-lptimer-trigger";
1270                                 reg = <2>;
1271                                 status = "disabled";
1272                         };
1273                 };
1274
1275                 lptimer4: timer@50023000 {
1276                         compatible = "st,stm32-lptimer";
1277                         reg = <0x50023000 0x400>;
1278                         interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
1279                         clocks = <&rcc LPTIM4_K>;
1280                         clock-names = "mux";
1281                         wakeup-source;
1282                         status = "disabled";
1283
1284                         pwm {
1285                                 compatible = "st,stm32-pwm-lp";
1286                                 #pwm-cells = <3>;
1287                                 status = "disabled";
1288                         };
1289                 };
1290
1291                 lptimer5: timer@50024000 {
1292                         compatible = "st,stm32-lptimer";
1293                         reg = <0x50024000 0x400>;
1294                         interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
1295                         clocks = <&rcc LPTIM5_K>;
1296                         clock-names = "mux";
1297                         wakeup-source;
1298                         status = "disabled";
1299
1300                         pwm {
1301                                 compatible = "st,stm32-pwm-lp";
1302                                 #pwm-cells = <3>;
1303                                 status = "disabled";
1304                         };
1305                 };
1306
1307                 vrefbuf: vrefbuf@50025000 {
1308                         compatible = "st,stm32-vrefbuf";
1309                         reg = <0x50025000 0x8>;
1310                         regulator-min-microvolt = <1500000>;
1311                         regulator-max-microvolt = <2500000>;
1312                         clocks = <&rcc VREF>;
1313                         status = "disabled";
1314                 };
1315
1316                 sai4: sai@50027000 {
1317                         compatible = "st,stm32h7-sai";
1318                         #address-cells = <1>;
1319                         #size-cells = <1>;
1320                         ranges = <0 0x50027000 0x400>;
1321                         reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1322                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1323                         resets = <&rcc SAI4_R>;
1324                         status = "disabled";
1325
1326                         sai4a: audio-controller@50027004 {
1327                                 #sound-dai-cells = <0>;
1328                                 compatible = "st,stm32-sai-sub-a";
1329                                 reg = <0x04 0x20>;
1330                                 clocks = <&rcc SAI4_K>;
1331                                 clock-names = "sai_ck";
1332                                 dmas = <&dmamux1 99 0x400 0x01>;
1333                                 status = "disabled";
1334                         };
1335
1336                         sai4b: audio-controller@50027024 {
1337                                 #sound-dai-cells = <0>;
1338                                 compatible = "st,stm32-sai-sub-b";
1339                                 reg = <0x24 0x20>;
1340                                 clocks = <&rcc SAI4_K>;
1341                                 clock-names = "sai_ck";
1342                                 dmas = <&dmamux1 100 0x400 0x01>;
1343                                 status = "disabled";
1344                         };
1345                 };
1346
1347                 dts: thermal@50028000 {
1348                         compatible = "st,stm32-thermal";
1349                         reg = <0x50028000 0x100>;
1350                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1351                         clocks = <&rcc TMPSENS>;
1352                         clock-names = "pclk";
1353                         #thermal-sensor-cells = <0>;
1354                         status = "disabled";
1355                 };
1356
1357                 hash1: hash@54002000 {
1358                         compatible = "st,stm32f756-hash";
1359                         reg = <0x54002000 0x400>;
1360                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1361                         clocks = <&rcc HASH1>;
1362                         resets = <&rcc HASH1_R>;
1363                         dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
1364                         dma-names = "in";
1365                         dma-maxburst = <2>;
1366                         status = "disabled";
1367                 };
1368
1369                 rng1: rng@54003000 {
1370                         compatible = "st,stm32-rng";
1371                         reg = <0x54003000 0x400>;
1372                         clocks = <&rcc RNG1_K>;
1373                         resets = <&rcc RNG1_R>;
1374                         status = "disabled";
1375                 };
1376
1377                 mdma1: dma-controller@58000000 {
1378                         compatible = "st,stm32h7-mdma";
1379                         reg = <0x58000000 0x1000>;
1380                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1381                         clocks = <&rcc MDMA>;
1382                         resets = <&rcc MDMA_R>;
1383                         #dma-cells = <5>;
1384                         dma-channels = <32>;
1385                         dma-requests = <48>;
1386                 };
1387
1388                 fmc: memory-controller@58002000 {
1389                         #address-cells = <2>;
1390                         #size-cells = <1>;
1391                         compatible = "st,stm32mp1-fmc2-ebi";
1392                         reg = <0x58002000 0x1000>;
1393                         clocks = <&rcc FMC_K>;
1394                         resets = <&rcc FMC_R>;
1395                         status = "disabled";
1396
1397                         ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
1398                                  <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
1399                                  <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
1400                                  <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
1401                                  <4 0 0x80000000 0x10000000>; /* NAND */
1402
1403                         nand-controller@4,0 {
1404                                 #address-cells = <1>;
1405                                 #size-cells = <0>;
1406                                 compatible = "st,stm32mp1-fmc2-nfc";
1407                                 reg = <4 0x00000000 0x1000>,
1408                                       <4 0x08010000 0x1000>,
1409                                       <4 0x08020000 0x1000>,
1410                                       <4 0x01000000 0x1000>,
1411                                       <4 0x09010000 0x1000>,
1412                                       <4 0x09020000 0x1000>;
1413                                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1414                                 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
1415                                        <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
1416                                        <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
1417                                 dma-names = "tx", "rx", "ecc";
1418                                 status = "disabled";
1419                         };
1420                 };
1421
1422                 qspi: spi@58003000 {
1423                         compatible = "st,stm32f469-qspi";
1424                         reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1425                         reg-names = "qspi", "qspi_mm";
1426                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1427                         dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
1428                                <&mdma1 22 0x2 0x10100008 0x0 0x0>;
1429                         dma-names = "tx", "rx";
1430                         clocks = <&rcc QSPI_K>;
1431                         resets = <&rcc QSPI_R>;
1432                         #address-cells = <1>;
1433                         #size-cells = <0>;
1434                         status = "disabled";
1435                 };
1436
1437                 sdmmc1: mmc@58005000 {
1438                         compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1439                         arm,primecell-periphid = <0x00253180>;
1440                         reg = <0x58005000 0x1000>;
1441                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1442                         interrupt-names = "cmd_irq";
1443                         clocks = <&rcc SDMMC1_K>;
1444                         clock-names = "apb_pclk";
1445                         resets = <&rcc SDMMC1_R>;
1446                         cap-sd-highspeed;
1447                         cap-mmc-highspeed;
1448                         max-frequency = <120000000>;
1449                         status = "disabled";
1450                 };
1451
1452                 sdmmc2: mmc@58007000 {
1453                         compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1454                         arm,primecell-periphid = <0x00253180>;
1455                         reg = <0x58007000 0x1000>;
1456                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1457                         interrupt-names = "cmd_irq";
1458                         clocks = <&rcc SDMMC2_K>;
1459                         clock-names = "apb_pclk";
1460                         resets = <&rcc SDMMC2_R>;
1461                         cap-sd-highspeed;
1462                         cap-mmc-highspeed;
1463                         max-frequency = <120000000>;
1464                         status = "disabled";
1465                 };
1466
1467                 crc1: crc@58009000 {
1468                         compatible = "st,stm32f7-crc";
1469                         reg = <0x58009000 0x400>;
1470                         clocks = <&rcc CRC1>;
1471                         status = "disabled";
1472                 };
1473
1474                 ethernet0: ethernet@5800a000 {
1475                         compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1476                         reg = <0x5800a000 0x2000>;
1477                         reg-names = "stmmaceth";
1478                         interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1479                         interrupt-names = "macirq";
1480                         clock-names = "stmmaceth",
1481                                       "mac-clk-tx",
1482                                       "mac-clk-rx",
1483                                       "eth-ck",
1484                                       "ptp_ref",
1485                                       "ethstp";
1486                         clocks = <&rcc ETHMAC>,
1487                                  <&rcc ETHTX>,
1488                                  <&rcc ETHRX>,
1489                                  <&rcc ETHCK_K>,
1490                                  <&rcc ETHPTP_K>,
1491                                  <&rcc ETHSTP>;
1492                         st,syscon = <&syscfg 0x4>;
1493                         snps,mixed-burst;
1494                         snps,pbl = <2>;
1495                         snps,en-tx-lpi-clockgating;
1496                         snps,axi-config = <&stmmac_axi_config_0>;
1497                         snps,tso;
1498                         status = "disabled";
1499
1500                         stmmac_axi_config_0: stmmac-axi-config {
1501                                 snps,wr_osr_lmt = <0x7>;
1502                                 snps,rd_osr_lmt = <0x7>;
1503                                 snps,blen = <0 0 0 0 16 8 4>;
1504                         };
1505                 };
1506
1507                 usbh_ohci: usb@5800c000 {
1508                         compatible = "generic-ohci";
1509                         reg = <0x5800c000 0x1000>;
1510                         clocks = <&usbphyc>, <&rcc USBH>;
1511                         resets = <&rcc USBH_R>;
1512                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1513                         status = "disabled";
1514                 };
1515
1516                 usbh_ehci: usb@5800d000 {
1517                         compatible = "generic-ehci";
1518                         reg = <0x5800d000 0x1000>;
1519                         clocks = <&usbphyc>, <&rcc USBH>;
1520                         resets = <&rcc USBH_R>;
1521                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1522                         companion = <&usbh_ohci>;
1523                         status = "disabled";
1524                 };
1525
1526                 ltdc: display-controller@5a001000 {
1527                         compatible = "st,stm32-ltdc";
1528                         reg = <0x5a001000 0x400>;
1529                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1530                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1531                         clocks = <&rcc LTDC_PX>;
1532                         clock-names = "lcd";
1533                         resets = <&rcc LTDC_R>;
1534                         status = "disabled";
1535
1536                         port {
1537                                 #address-cells = <1>;
1538                                 #size-cells = <0>;
1539                         };
1540                 };
1541
1542                 iwdg2: watchdog@5a002000 {
1543                         compatible = "st,stm32mp1-iwdg";
1544                         reg = <0x5a002000 0x400>;
1545                         clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1546                         clock-names = "pclk", "lsi";
1547                         status = "disabled";
1548                 };
1549
1550                 usbphyc: usbphyc@5a006000 {
1551                         #address-cells = <1>;
1552                         #size-cells = <0>;
1553                         #clock-cells = <0>;
1554                         compatible = "st,stm32mp1-usbphyc";
1555                         reg = <0x5a006000 0x1000>;
1556                         clocks = <&rcc USBPHY_K>;
1557                         resets = <&rcc USBPHY_R>;
1558                         vdda1v1-supply = <&reg11>;
1559                         vdda1v8-supply = <&reg18>;
1560                         status = "disabled";
1561
1562                         usbphyc_port0: usb-phy@0 {
1563                                 #phy-cells = <0>;
1564                                 reg = <0>;
1565                         };
1566
1567                         usbphyc_port1: usb-phy@1 {
1568                                 #phy-cells = <1>;
1569                                 reg = <1>;
1570                         };
1571                 };
1572
1573                 usart1: serial@5c000000 {
1574                         compatible = "st,stm32h7-uart";
1575                         reg = <0x5c000000 0x400>;
1576                         interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
1577                         clocks = <&rcc USART1_K>;
1578                         wakeup-source;
1579                         status = "disabled";
1580                 };
1581
1582                 spi6: spi@5c001000 {
1583                         #address-cells = <1>;
1584                         #size-cells = <0>;
1585                         compatible = "st,stm32h7-spi";
1586                         reg = <0x5c001000 0x400>;
1587                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1588                         clocks = <&rcc SPI6_K>;
1589                         resets = <&rcc SPI6_R>;
1590                         dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1591                                <&mdma1 35 0x0 0x40002 0x0 0x0>;
1592                         dma-names = "rx", "tx";
1593                         status = "disabled";
1594                 };
1595
1596                 i2c4: i2c@5c002000 {
1597                         compatible = "st,stm32mp15-i2c";
1598                         reg = <0x5c002000 0x400>;
1599                         interrupt-names = "event", "error";
1600                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1601                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1602                         clocks = <&rcc I2C4_K>;
1603                         resets = <&rcc I2C4_R>;
1604                         #address-cells = <1>;
1605                         #size-cells = <0>;
1606                         st,syscfg-fmp = <&syscfg 0x4 0x8>;
1607                         wakeup-source;
1608                         i2c-analog-filter;
1609                         status = "disabled";
1610                 };
1611
1612                 rtc: rtc@5c004000 {
1613                         compatible = "st,stm32mp1-rtc";
1614                         reg = <0x5c004000 0x400>;
1615                         clocks = <&rcc RTCAPB>, <&rcc RTC>;
1616                         clock-names = "pclk", "rtc_ck";
1617                         interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
1618                         status = "disabled";
1619                 };
1620
1621                 bsec: efuse@5c005000 {
1622                         compatible = "st,stm32mp15-bsec";
1623                         reg = <0x5c005000 0x400>;
1624                         #address-cells = <1>;
1625                         #size-cells = <1>;
1626                         ts_cal1: calib@5c {
1627                                 reg = <0x5c 0x2>;
1628                         };
1629                         ts_cal2: calib@5e {
1630                                 reg = <0x5e 0x2>;
1631                         };
1632                 };
1633
1634                 i2c6: i2c@5c009000 {
1635                         compatible = "st,stm32mp15-i2c";
1636                         reg = <0x5c009000 0x400>;
1637                         interrupt-names = "event", "error";
1638                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1639                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1640                         clocks = <&rcc I2C6_K>;
1641                         resets = <&rcc I2C6_R>;
1642                         #address-cells = <1>;
1643                         #size-cells = <0>;
1644                         st,syscfg-fmp = <&syscfg 0x4 0x20>;
1645                         wakeup-source;
1646                         i2c-analog-filter;
1647                         status = "disabled";
1648                 };
1649
1650                 tamp: tamp@5c00a000 {
1651                         compatible = "st,stm32-tamp", "syscon", "simple-mfd";
1652                         reg = <0x5c00a000 0x400>;
1653                 };
1654
1655                 /*
1656                  * Break node order to solve dependency probe issue between
1657                  * pinctrl and exti.
1658                  */
1659                 pinctrl: pinctrl@50002000 {
1660                         #address-cells = <1>;
1661                         #size-cells = <1>;
1662                         compatible = "st,stm32mp157-pinctrl";
1663                         ranges = <0 0x50002000 0xa400>;
1664                         interrupt-parent = <&exti>;
1665                         st,syscfg = <&exti 0x60 0xff>;
1666                         pins-are-numbered;
1667
1668                         gpioa: gpio@50002000 {
1669                                 gpio-controller;
1670                                 #gpio-cells = <2>;
1671                                 interrupt-controller;
1672                                 #interrupt-cells = <2>;
1673                                 reg = <0x0 0x400>;
1674                                 clocks = <&rcc GPIOA>;
1675                                 st,bank-name = "GPIOA";
1676                                 status = "disabled";
1677                         };
1678
1679                         gpiob: gpio@50003000 {
1680                                 gpio-controller;
1681                                 #gpio-cells = <2>;
1682                                 interrupt-controller;
1683                                 #interrupt-cells = <2>;
1684                                 reg = <0x1000 0x400>;
1685                                 clocks = <&rcc GPIOB>;
1686                                 st,bank-name = "GPIOB";
1687                                 status = "disabled";
1688                         };
1689
1690                         gpioc: gpio@50004000 {
1691                                 gpio-controller;
1692                                 #gpio-cells = <2>;
1693                                 interrupt-controller;
1694                                 #interrupt-cells = <2>;
1695                                 reg = <0x2000 0x400>;
1696                                 clocks = <&rcc GPIOC>;
1697                                 st,bank-name = "GPIOC";
1698                                 status = "disabled";
1699                         };
1700
1701                         gpiod: gpio@50005000 {
1702                                 gpio-controller;
1703                                 #gpio-cells = <2>;
1704                                 interrupt-controller;
1705                                 #interrupt-cells = <2>;
1706                                 reg = <0x3000 0x400>;
1707                                 clocks = <&rcc GPIOD>;
1708                                 st,bank-name = "GPIOD";
1709                                 status = "disabled";
1710                         };
1711
1712                         gpioe: gpio@50006000 {
1713                                 gpio-controller;
1714                                 #gpio-cells = <2>;
1715                                 interrupt-controller;
1716                                 #interrupt-cells = <2>;
1717                                 reg = <0x4000 0x400>;
1718                                 clocks = <&rcc GPIOE>;
1719                                 st,bank-name = "GPIOE";
1720                                 status = "disabled";
1721                         };
1722
1723                         gpiof: gpio@50007000 {
1724                                 gpio-controller;
1725                                 #gpio-cells = <2>;
1726                                 interrupt-controller;
1727                                 #interrupt-cells = <2>;
1728                                 reg = <0x5000 0x400>;
1729                                 clocks = <&rcc GPIOF>;
1730                                 st,bank-name = "GPIOF";
1731                                 status = "disabled";
1732                         };
1733
1734                         gpiog: gpio@50008000 {
1735                                 gpio-controller;
1736                                 #gpio-cells = <2>;
1737                                 interrupt-controller;
1738                                 #interrupt-cells = <2>;
1739                                 reg = <0x6000 0x400>;
1740                                 clocks = <&rcc GPIOG>;
1741                                 st,bank-name = "GPIOG";
1742                                 status = "disabled";
1743                         };
1744
1745                         gpioh: gpio@50009000 {
1746                                 gpio-controller;
1747                                 #gpio-cells = <2>;
1748                                 interrupt-controller;
1749                                 #interrupt-cells = <2>;
1750                                 reg = <0x7000 0x400>;
1751                                 clocks = <&rcc GPIOH>;
1752                                 st,bank-name = "GPIOH";
1753                                 status = "disabled";
1754                         };
1755
1756                         gpioi: gpio@5000a000 {
1757                                 gpio-controller;
1758                                 #gpio-cells = <2>;
1759                                 interrupt-controller;
1760                                 #interrupt-cells = <2>;
1761                                 reg = <0x8000 0x400>;
1762                                 clocks = <&rcc GPIOI>;
1763                                 st,bank-name = "GPIOI";
1764                                 status = "disabled";
1765                         };
1766
1767                         gpioj: gpio@5000b000 {
1768                                 gpio-controller;
1769                                 #gpio-cells = <2>;
1770                                 interrupt-controller;
1771                                 #interrupt-cells = <2>;
1772                                 reg = <0x9000 0x400>;
1773                                 clocks = <&rcc GPIOJ>;
1774                                 st,bank-name = "GPIOJ";
1775                                 status = "disabled";
1776                         };
1777
1778                         gpiok: gpio@5000c000 {
1779                                 gpio-controller;
1780                                 #gpio-cells = <2>;
1781                                 interrupt-controller;
1782                                 #interrupt-cells = <2>;
1783                                 reg = <0xa000 0x400>;
1784                                 clocks = <&rcc GPIOK>;
1785                                 st,bank-name = "GPIOK";
1786                                 status = "disabled";
1787                         };
1788                 };
1789
1790                 pinctrl_z: pinctrl@54004000 {
1791                         #address-cells = <1>;
1792                         #size-cells = <1>;
1793                         compatible = "st,stm32mp157-z-pinctrl";
1794                         ranges = <0 0x54004000 0x400>;
1795                         pins-are-numbered;
1796                         interrupt-parent = <&exti>;
1797                         st,syscfg = <&exti 0x60 0xff>;
1798
1799                         gpioz: gpio@54004000 {
1800                                 gpio-controller;
1801                                 #gpio-cells = <2>;
1802                                 interrupt-controller;
1803                                 #interrupt-cells = <2>;
1804                                 reg = <0 0x400>;
1805                                 clocks = <&rcc GPIOZ>;
1806                                 st,bank-name = "GPIOZ";
1807                                 st,bank-ioport = <11>;
1808                                 status = "disabled";
1809                         };
1810                 };
1811         };
1812
1813         mlahb: ahb {
1814                 compatible = "st,mlahb", "simple-bus";
1815                 #address-cells = <1>;
1816                 #size-cells = <1>;
1817                 ranges;
1818                 dma-ranges = <0x00000000 0x38000000 0x10000>,
1819                              <0x10000000 0x10000000 0x60000>,
1820                              <0x30000000 0x30000000 0x60000>;
1821
1822                 m4_rproc: m4@10000000 {
1823                         compatible = "st,stm32mp1-m4";
1824                         reg = <0x10000000 0x40000>,
1825                               <0x30000000 0x40000>,
1826                               <0x38000000 0x10000>;
1827                         resets = <&rcc MCU_R>;
1828                         st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1829                         st,syscfg-tz = <&rcc 0x000 0x1>;
1830                         st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
1831                         st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
1832                         st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
1833                         status = "disabled";
1834                 };
1835         };
1836 };