arch/arm/boot/dts/stm32mp131.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
   4  * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
   5  */
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/stm32mp13-clks.h>
   8 #include <dt-bindings/reset/stm32mp13-resets.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu0: cpu@0 {
  19                         compatible = "arm,cortex-a7";
  20                         device_type = "cpu";
  21                         reg = <0>;
  22                 };
  23         };
  24
  25         arm-pmu {
  26                 compatible = "arm,cortex-a7-pmu";
  27                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
  28                 interrupt-affinity = <&cpu0>;
  29                 interrupt-parent = <&intc>;
  30         };
  31
  32         firmware {
  33                 optee {
  34                         method = "smc";
  35                         compatible = "linaro,optee-tz";
  36                 };
  37
  38                 scmi: scmi {
  39                         compatible = "linaro,scmi-optee";
  40                         #address-cells = <1>;
  41                         #size-cells = <0>;
  42                         linaro,optee-channel-id = <0>;
  43                         shmem = <&scmi_shm>;
  44
  45                         scmi_clk: protocol@14 {
  46                                 reg = <0x14>;
  47                                 #clock-cells = <1>;
  48                         };
  49
  50                         scmi_reset: protocol@16 {
  51                                 reg = <0x16>;
  52                                 #reset-cells = <1>;
  53                         };
  54                 };
  55         };
  56
  57         intc: interrupt-controller@a0021000 {
  58                 compatible = "arm,cortex-a7-gic";
  59                 #interrupt-cells = <3>;
  60                 interrupt-controller;
  61                 reg = <0xa0021000 0x1000>,
  62                       <0xa0022000 0x2000>;
  63         };
  64
  65         psci {
  66                 compatible = "arm,psci-1.0";
  67                 method = "smc";
  68         };
  69
  70         timer {
  71                 compatible = "arm,armv7-timer";
  72                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  73                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  74                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  75                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
  76                 interrupt-parent = <&intc>;
  77                 always-on;
  78         };
  79
  80         soc {
  81                 compatible = "simple-bus";
  82                 #address-cells = <1>;
  83                 #size-cells = <1>;
  84                 interrupt-parent = <&intc>;
  85                 ranges;
  86
  87                 scmi_sram: sram@2ffff000 {
  88                         compatible = "mmio-sram";
  89                         reg = <0x2ffff000 0x1000>;
  90                         #address-cells = <1>;
  91                         #size-cells = <1>;
  92                         ranges = <0 0x2ffff000 0x1000>;
  93
  94                         scmi_shm: scmi-sram@0 {
  95                                 compatible = "arm,scmi-shmem";
  96                                 reg = <0 0x80>;
  97                         };
  98                 };
  99
 100                 spi2: spi@4000b000 {
 101                         compatible = "st,stm32h7-spi";
 102                         reg = <0x4000b000 0x400>;
 103                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 104                         clocks = <&rcc SPI2_K>;
 105                         resets = <&rcc SPI2_R>;
 106                         #address-cells = <1>;
 107                         #size-cells = <0>;
 108                         dmas = <&dmamux1 39 0x400 0x01>,
 109                                <&dmamux1 40 0x400 0x01>;
 110                         dma-names = "rx", "tx";
 111                         status = "disabled";
 112                 };
 113
 114                 spi3: spi@4000c000 {
 115                         compatible = "st,stm32h7-spi";
 116                         reg = <0x4000c000 0x400>;
 117                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 118                         clocks = <&rcc SPI3_K>;
 119                         resets = <&rcc SPI3_R>;
 120                         #address-cells = <1>;
 121                         #size-cells = <0>;
 122                         dmas = <&dmamux1 61 0x400 0x01>,
 123                                <&dmamux1 62 0x400 0x01>;
 124                         dma-names = "rx", "tx";
 125                         status = "disabled";
 126                 };
 127
 128                 uart4: serial@40010000 {
 129                         compatible = "st,stm32h7-uart";
 130                         reg = <0x40010000 0x400>;
 131                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 132                         clocks = <&rcc UART4_K>;
 133                         resets = <&rcc UART4_R>;
 134                         status = "disabled";
 135                 };
 136
 137                 i2c1: i2c@40012000 {
 138                         compatible = "st,stm32mp13-i2c";
 139                         reg = <0x40012000 0x400>;
 140                         interrupt-names = "event", "error";
 141                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 142                                      <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 143                         clocks = <&rcc I2C1_K>;
 144                         resets = <&rcc I2C1_R>;
 145                         #address-cells = <1>;
 146                         #size-cells = <0>;
 147                         dmas = <&dmamux1 33 0x400 0x1>,
 148                                <&dmamux1 34 0x400 0x1>;
 149                         dma-names = "rx", "tx";
 150                         st,syscfg-fmp = <&syscfg 0x4 0x1>;
 151                         i2c-analog-filter;
 152                         status = "disabled";
 153                 };
 154
 155                 i2c2: i2c@40013000 {
 156                         compatible = "st,stm32mp13-i2c";
 157                         reg = <0x40013000 0x400>;
 158                         interrupt-names = "event", "error";
 159                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 160                                      <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 161                         clocks = <&rcc I2C2_K>;
 162                         resets = <&rcc I2C2_R>;
 163                         #address-cells = <1>;
 164                         #size-cells = <0>;
 165                         dmas = <&dmamux1 35 0x400 0x1>,
 166                                <&dmamux1 36 0x400 0x1>;
 167                         dma-names = "rx", "tx";
 168                         st,syscfg-fmp = <&syscfg 0x4 0x2>;
 169                         i2c-analog-filter;
 170                         status = "disabled";
 171                 };
 172
 173                 spi1: spi@44004000 {
 174                         compatible = "st,stm32h7-spi";
 175                         reg = <0x44004000 0x400>;
 176                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 177                         clocks = <&rcc SPI1_K>;
 178                         resets = <&rcc SPI1_R>;
 179                         #address-cells = <1>;
 180                         #size-cells = <0>;
 181                         dmas = <&dmamux1 37 0x400 0x01>,
 182                                <&dmamux1 38 0x400 0x01>;
 183                         dma-names = "rx", "tx";
 184                         status = "disabled";
 185                 };
 186
 187                 dma1: dma-controller@48000000 {
 188                         compatible = "st,stm32-dma";
 189                         reg = <0x48000000 0x400>;
 190                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 191                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 192                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 193                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 194                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 195                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 196                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 197                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 198                         clocks = <&rcc DMA1>;
 199                         resets = <&rcc DMA1_R>;
 200                         #dma-cells = <4>;
 201                         st,mem2mem;
 202                         dma-requests = <8>;
 203                 };
 204
 205                 dma2: dma-controller@48001000 {
 206                         compatible = "st,stm32-dma";
 207                         reg = <0x48001000 0x400>;
 208                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 209                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 210                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 211                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 212                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 213                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 214                                      <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 215                                      <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 216                         clocks = <&rcc DMA2>;
 217                         resets = <&rcc DMA2_R>;
 218                         #dma-cells = <4>;
 219                         st,mem2mem;
 220                         dma-requests = <8>;
 221                 };
 222
 223                 dmamux1: dma-router@48002000 {
 224                         compatible = "st,stm32h7-dmamux";
 225                         reg = <0x48002000 0x40>;
 226                         clocks = <&rcc DMAMUX1>;
 227                         resets = <&rcc DMAMUX1_R>;
 228                         #dma-cells = <3>;
 229                         dma-masters = <&dma1 &dma2>;
 230                         dma-requests = <128>;
 231                         dma-channels = <16>;
 232                 };
 233
 234                 spi4: spi@4c002000 {
 235                         compatible = "st,stm32h7-spi";
 236                         reg = <0x4c002000 0x400>;
 237                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 238                         clocks = <&rcc SPI4_K>;
 239                         resets = <&rcc SPI4_R>;
 240                         #address-cells = <1>;
 241                         #size-cells = <0>;
 242                         dmas = <&dmamux1 83 0x400 0x01>,
 243                                <&dmamux1 84 0x400 0x01>;
 244                         dma-names = "rx", "tx";
 245                         status = "disabled";
 246                 };
 247
 248                 spi5: spi@4c003000 {
 249                         compatible = "st,stm32h7-spi";
 250                         reg = <0x4c003000 0x400>;
 251                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 252                         clocks = <&rcc SPI5_K>;
 253                         resets = <&rcc SPI5_R>;
 254                         #address-cells = <1>;
 255                         #size-cells = <0>;
 256                         dmas = <&dmamux1 85 0x400 0x01>,
 257                                <&dmamux1 86 0x400 0x01>;
 258                         dma-names = "rx", "tx";
 259                         status = "disabled";
 260                 };
 261
 262                 i2c3: i2c@4c004000 {
 263                         compatible = "st,stm32mp13-i2c";
 264                         reg = <0x4c004000 0x400>;
 265                         interrupt-names = "event", "error";
 266                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
 267                                      <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 268                         clocks = <&rcc I2C3_K>;
 269                         resets = <&rcc I2C3_R>;
 270                         #address-cells = <1>;
 271                         #size-cells = <0>;
 272                         dmas = <&dmamux1 73 0x400 0x1>,
 273                                <&dmamux1 74 0x400 0x1>;
 274                         dma-names = "rx", "tx";
 275                         st,syscfg-fmp = <&syscfg 0x4 0x4>;
 276                         i2c-analog-filter;
 277                         status = "disabled";
 278                 };
 279
 280                 i2c4: i2c@4c005000 {
 281                         compatible = "st,stm32mp13-i2c";
 282                         reg = <0x4c005000 0x400>;
 283                         interrupt-names = "event", "error";
 284                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
 285                                      <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 286                         clocks = <&rcc I2C4_K>;
 287                         resets = <&rcc I2C4_R>;
 288                         #address-cells = <1>;
 289                         #size-cells = <0>;
 290                         dmas = <&dmamux1 75 0x400 0x1>,
 291                                <&dmamux1 76 0x400 0x1>;
 292                         dma-names = "rx", "tx";
 293                         st,syscfg-fmp = <&syscfg 0x4 0x8>;
 294                         i2c-analog-filter;
 295                         status = "disabled";
 296                 };
 297
 298                 i2c5: i2c@4c006000 {
 299                         compatible = "st,stm32mp13-i2c";
 300                         reg = <0x4c006000 0x400>;
 301                         interrupt-names = "event", "error";
 302                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 303                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 304                         clocks = <&rcc I2C5_K>;
 305                         resets = <&rcc I2C5_R>;
 306                         #address-cells = <1>;
 307                         #size-cells = <0>;
 308                         dmas = <&dmamux1 115 0x400 0x1>,
 309                                <&dmamux1 116 0x400 0x1>;
 310                         dma-names = "rx", "tx";
 311                         st,syscfg-fmp = <&syscfg 0x4 0x10>;
 312                         i2c-analog-filter;
 313                         status = "disabled";
 314                 };
 315
 316                 rcc: rcc@50000000 {
 317                         compatible = "st,stm32mp13-rcc", "syscon";
 318                         reg = <0x50000000 0x1000>;
 319                         #clock-cells = <1>;
 320                         #reset-cells = <1>;
 321                         clock-names = "hse", "hsi", "csi", "lse", "lsi";
 322                         clocks = <&scmi_clk CK_SCMI_HSE>,
 323                                  <&scmi_clk CK_SCMI_HSI>,
 324                                  <&scmi_clk CK_SCMI_CSI>,
 325                                  <&scmi_clk CK_SCMI_LSE>,
 326                                  <&scmi_clk CK_SCMI_LSI>;
 327                 };
 328
 329                 exti: interrupt-controller@5000d000 {
 330                         compatible = "st,stm32mp13-exti", "syscon";
 331                         interrupt-controller;
 332                         #interrupt-cells = <2>;
 333                         reg = <0x5000d000 0x400>;
 334                 };
 335
 336                 syscfg: syscon@50020000 {
 337                         compatible = "st,stm32mp157-syscfg", "syscon";
 338                         reg = <0x50020000 0x400>;
 339                         clocks = <&rcc SYSCFG>;
 340                 };
 341
 342                 mdma: dma-controller@58000000 {
 343                         compatible = "st,stm32h7-mdma";
 344                         reg = <0x58000000 0x1000>;
 345                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 346                         clocks = <&rcc MDMA>;
 347                         #dma-cells = <5>;
 348                         dma-channels = <32>;
 349                         dma-requests = <48>;
 350                 };
 351
 352                 sdmmc1: mmc@58005000 {
 353                         compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
 354                         arm,primecell-periphid = <0x20253180>;
 355                         reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
 356                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 357                         interrupt-names = "cmd_irq";
 358                         clocks = <&rcc SDMMC1_K>;
 359                         clock-names = "apb_pclk";
 360                         resets = <&rcc SDMMC1_R>;
 361                         cap-sd-highspeed;
 362                         cap-mmc-highspeed;
 363                         max-frequency = <130000000>;
 364                         status = "disabled";
 365                 };
 366
 367                 sdmmc2: mmc@58007000 {
 368                         compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
 369                         arm,primecell-periphid = <0x20253180>;
 370                         reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
 371                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 372                         interrupt-names = "cmd_irq";
 373                         clocks = <&rcc SDMMC2_K>;
 374                         clock-names = "apb_pclk";
 375                         resets = <&rcc SDMMC2_R>;
 376                         cap-sd-highspeed;
 377                         cap-mmc-highspeed;
 378                         max-frequency = <130000000>;
 379                         status = "disabled";
 380                 };
 381
 382                 iwdg2: watchdog@5a002000 {
 383                         compatible = "st,stm32mp1-iwdg";
 384                         reg = <0x5a002000 0x400>;
 385                         clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
 386                         clock-names = "pclk", "lsi";
 387                         status = "disabled";
 388                 };
 389
 390                 rtc: rtc@5c004000 {
 391                         compatible = "st,stm32mp1-rtc";
 392                         reg = <0x5c004000 0x400>;
 393                         interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
 394                         clocks = <&scmi_clk CK_SCMI_RTCAPB>,
 395                                  <&scmi_clk CK_SCMI_RTC>;
 396                         clock-names = "pclk", "rtc_ck";
 397                         status = "disabled";
 398                 };
 399
 400                 bsec: efuse@5c005000 {
 401                         compatible = "st,stm32mp15-bsec";
 402                         reg = <0x5c005000 0x400>;
 403                         #address-cells = <1>;
 404                         #size-cells = <1>;
 405
 406                         part_number_otp: part_number_otp@4 {
 407                                 reg = <0x4 0x2>;
 408                                 bits = <0 12>;
 409                         };
 410                         ts_cal1: calib@5c {
 411                                 reg = <0x5c 0x2>;
 412                         };
 413                         ts_cal2: calib@5e {
 414                                 reg = <0x5e 0x2>;
 415                         };
 416                 };
 417
 418                 /*
 419                  * Break node order to solve dependency probe issue between
 420                  * pinctrl and exti.
 421                  */
 422                 pinctrl: pinctrl@50002000 {
 423                         #address-cells = <1>;
 424                         #size-cells = <1>;
 425                         compatible = "st,stm32mp135-pinctrl";
 426                         ranges = <0 0x50002000 0x8400>;
 427                         interrupt-parent = <&exti>;
 428                         st,syscfg = <&exti 0x60 0xff>;
 429                         pins-are-numbered;
 430
 431                         gpioa: gpio@50002000 {
 432                                 gpio-controller;
 433                                 #gpio-cells = <2>;
 434                                 interrupt-controller;
 435                                 #interrupt-cells = <2>;
 436                                 reg = <0x0 0x400>;
 437                                 clocks = <&rcc GPIOA>;
 438                                 st,bank-name = "GPIOA";
 439                                 ngpios = <16>;
 440                                 gpio-ranges = <&pinctrl 0 0 16>;
 441                         };
 442
 443                         gpiob: gpio@50003000 {
 444                                 gpio-controller;
 445                                 #gpio-cells = <2>;
 446                                 interrupt-controller;
 447                                 #interrupt-cells = <2>;
 448                                 reg = <0x1000 0x400>;
 449                                 clocks = <&rcc GPIOB>;
 450                                 st,bank-name = "GPIOB";
 451                                 ngpios = <16>;
 452                                 gpio-ranges = <&pinctrl 0 16 16>;
 453                         };
 454
 455                         gpioc: gpio@50004000 {
 456                                 gpio-controller;
 457                                 #gpio-cells = <2>;
 458                                 interrupt-controller;
 459                                 #interrupt-cells = <2>;
 460                                 reg = <0x2000 0x400>;
 461                                 clocks = <&rcc GPIOC>;
 462                                 st,bank-name = "GPIOC";
 463                                 ngpios = <16>;
 464                                 gpio-ranges = <&pinctrl 0 32 16>;
 465                         };
 466
 467                         gpiod: gpio@50005000 {
 468                                 gpio-controller;
 469                                 #gpio-cells = <2>;
 470                                 interrupt-controller;
 471                                 #interrupt-cells = <2>;
 472                                 reg = <0x3000 0x400>;
 473                                 clocks = <&rcc GPIOD>;
 474                                 st,bank-name = "GPIOD";
 475                                 ngpios = <16>;
 476                                 gpio-ranges = <&pinctrl 0 48 16>;
 477                         };
 478
 479                         gpioe: gpio@50006000 {
 480                                 gpio-controller;
 481                                 #gpio-cells = <2>;
 482                                 interrupt-controller;
 483                                 #interrupt-cells = <2>;
 484                                 reg = <0x4000 0x400>;
 485                                 clocks = <&rcc GPIOE>;
 486                                 st,bank-name = "GPIOE";
 487                                 ngpios = <16>;
 488                                 gpio-ranges = <&pinctrl 0 64 16>;
 489                         };
 490
 491                         gpiof: gpio@50007000 {
 492                                 gpio-controller;
 493                                 #gpio-cells = <2>;
 494                                 interrupt-controller;
 495                                 #interrupt-cells = <2>;
 496                                 reg = <0x5000 0x400>;
 497                                 clocks = <&rcc GPIOF>;
 498                                 st,bank-name = "GPIOF";
 499                                 ngpios = <16>;
 500                                 gpio-ranges = <&pinctrl 0 80 16>;
 501                         };
 502
 503                         gpiog: gpio@50008000 {
 504                                 gpio-controller;
 505                                 #gpio-cells = <2>;
 506                                 interrupt-controller;
 507                                 #interrupt-cells = <2>;
 508                                 reg = <0x6000 0x400>;
 509                                 clocks = <&rcc GPIOG>;
 510                                 st,bank-name = "GPIOG";
 511                                 ngpios = <16>;
 512                                 gpio-ranges = <&pinctrl 0 96 16>;
 513                         };
 514
 515                         gpioh: gpio@50009000 {
 516                                 gpio-controller;
 517                                 #gpio-cells = <2>;
 518                                 interrupt-controller;
 519                                 #interrupt-cells = <2>;
 520                                 reg = <0x7000 0x400>;
 521                                 clocks = <&rcc GPIOH>;
 522                                 st,bank-name = "GPIOH";
 523                                 ngpios = <15>;
 524                                 gpio-ranges = <&pinctrl 0 112 15>;
 525                         };
 526
 527                         gpioi: gpio@5000a000 {
 528                                 gpio-controller;
 529                                 #gpio-cells = <2>;
 530                                 interrupt-controller;
 531                                 #interrupt-cells = <2>;
 532                                 reg = <0x8000 0x400>;
 533                                 clocks = <&rcc GPIOI>;
 534                                 st,bank-name = "GPIOI";
 535                                 ngpios = <8>;
 536                                 gpio-ranges = <&pinctrl 0 128 8>;
 537                         };
 538                 };
 539         };
 540 };