2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include "armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32fx-clock.h>
45 #include <dt-bindings/mfd/stm32f7-rcc.h>
54 compatible = "fixed-clock";
55 clock-frequency = <0>;
60 compatible = "fixed-clock";
61 clock-frequency = <32768>;
66 compatible = "fixed-clock";
67 clock-frequency = <32000>;
70 clk_i2s_ckin: clk-i2s-ckin {
72 compatible = "fixed-clock";
73 clock-frequency = <48000000>;
78 timers2: timers@40000000 {
81 compatible = "st,stm32-timers";
82 reg = <0x40000000 0x400>;
83 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
88 compatible = "st,stm32-pwm";
94 compatible = "st,stm32-timer-trigger";
100 timers3: timers@40000400 {
101 #address-cells = <1>;
103 compatible = "st,stm32-timers";
104 reg = <0x40000400 0x400>;
105 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
110 compatible = "st,stm32-pwm";
116 compatible = "st,stm32-timer-trigger";
122 timers4: timers@40000800 {
123 #address-cells = <1>;
125 compatible = "st,stm32-timers";
126 reg = <0x40000800 0x400>;
127 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
132 compatible = "st,stm32-pwm";
138 compatible = "st,stm32-timer-trigger";
144 timers5: timers@40000c00 {
145 #address-cells = <1>;
147 compatible = "st,stm32-timers";
148 reg = <0x40000C00 0x400>;
149 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
154 compatible = "st,stm32-pwm";
160 compatible = "st,stm32-timer-trigger";
166 timers6: timers@40001000 {
167 #address-cells = <1>;
169 compatible = "st,stm32-timers";
170 reg = <0x40001000 0x400>;
171 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
176 compatible = "st,stm32-timer-trigger";
182 timers7: timers@40001400 {
183 #address-cells = <1>;
185 compatible = "st,stm32-timers";
186 reg = <0x40001400 0x400>;
187 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
192 compatible = "st,stm32-timer-trigger";
198 timers12: timers@40001800 {
199 #address-cells = <1>;
201 compatible = "st,stm32-timers";
202 reg = <0x40001800 0x400>;
203 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
208 compatible = "st,stm32-pwm";
214 compatible = "st,stm32-timer-trigger";
220 timers13: timers@40001c00 {
221 compatible = "st,stm32-timers";
222 reg = <0x40001C00 0x400>;
223 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
228 compatible = "st,stm32-pwm";
234 timers14: timers@40002000 {
235 compatible = "st,stm32-timers";
236 reg = <0x40002000 0x400>;
237 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
242 compatible = "st,stm32-pwm";
249 compatible = "st,stm32-rtc";
250 reg = <0x40002800 0x400>;
251 clocks = <&rcc 1 CLK_RTC>;
252 assigned-clocks = <&rcc 1 CLK_RTC>;
253 assigned-clock-parents = <&rcc 1 CLK_LSE>;
254 interrupt-parent = <&exti>;
256 st,syscfg = <&pwrcfg 0x00 0x100>;
260 usart2: serial@40004400 {
261 compatible = "st,stm32f7-uart";
262 reg = <0x40004400 0x400>;
264 clocks = <&rcc 1 CLK_USART2>;
268 usart3: serial@40004800 {
269 compatible = "st,stm32f7-uart";
270 reg = <0x40004800 0x400>;
272 clocks = <&rcc 1 CLK_USART3>;
276 usart4: serial@40004c00 {
277 compatible = "st,stm32f7-uart";
278 reg = <0x40004c00 0x400>;
280 clocks = <&rcc 1 CLK_UART4>;
284 usart5: serial@40005000 {
285 compatible = "st,stm32f7-uart";
286 reg = <0x40005000 0x400>;
288 clocks = <&rcc 1 CLK_UART5>;
293 compatible = "st,stm32f7-i2c";
294 reg = <0x40005400 0x400>;
297 resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
298 clocks = <&rcc 1 CLK_I2C1>;
299 #address-cells = <1>;
305 compatible = "st,stm32f7-i2c";
306 reg = <0x40005800 0x400>;
309 resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
310 clocks = <&rcc 1 CLK_I2C2>;
311 #address-cells = <1>;
317 compatible = "st,stm32f7-i2c";
318 reg = <0x40005c00 0x400>;
321 resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
322 clocks = <&rcc 1 CLK_I2C3>;
323 #address-cells = <1>;
329 compatible = "st,stm32f7-i2c";
330 reg = <0x40006000 0x400>;
333 resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
334 clocks = <&rcc 1 CLK_I2C4>;
335 #address-cells = <1>;
341 compatible = "st,stm32-cec";
342 reg = <0x40006C00 0x400>;
344 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
345 clock-names = "cec", "hdmi-cec";
349 usart7: serial@40007800 {
350 compatible = "st,stm32f7-uart";
351 reg = <0x40007800 0x400>;
353 clocks = <&rcc 1 CLK_UART7>;
357 usart8: serial@40007c00 {
358 compatible = "st,stm32f7-uart";
359 reg = <0x40007c00 0x400>;
361 clocks = <&rcc 1 CLK_UART8>;
365 timers1: timers@40010000 {
366 #address-cells = <1>;
368 compatible = "st,stm32-timers";
369 reg = <0x40010000 0x400>;
370 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
375 compatible = "st,stm32-pwm";
381 compatible = "st,stm32-timer-trigger";
387 timers8: timers@40010400 {
388 #address-cells = <1>;
390 compatible = "st,stm32-timers";
391 reg = <0x40010400 0x400>;
392 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
397 compatible = "st,stm32-pwm";
403 compatible = "st,stm32-timer-trigger";
409 usart1: serial@40011000 {
410 compatible = "st,stm32f7-uart";
411 reg = <0x40011000 0x400>;
413 clocks = <&rcc 1 CLK_USART1>;
417 usart6: serial@40011400 {
418 compatible = "st,stm32f7-uart";
419 reg = <0x40011400 0x400>;
421 clocks = <&rcc 1 CLK_USART6>;
425 sdio2: mmc@40011c00 {
426 compatible = "arm,pl180", "arm,primecell";
427 arm,primecell-periphid = <0x00880180>;
428 reg = <0x40011c00 0x400>;
429 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
430 clock-names = "apb_pclk";
432 max-frequency = <48000000>;
436 sdio1: mmc@40012c00 {
437 compatible = "arm,pl180", "arm,primecell";
438 arm,primecell-periphid = <0x00880180>;
439 reg = <0x40012c00 0x400>;
440 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
441 clock-names = "apb_pclk";
443 max-frequency = <48000000>;
447 syscfg: syscon@40013800 {
448 compatible = "st,stm32-syscfg", "syscon";
449 reg = <0x40013800 0x400>;
452 exti: interrupt-controller@40013c00 {
453 compatible = "st,stm32-exti";
454 interrupt-controller;
455 #interrupt-cells = <2>;
456 reg = <0x40013C00 0x400>;
457 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
460 timers9: timers@40014000 {
461 #address-cells = <1>;
463 compatible = "st,stm32-timers";
464 reg = <0x40014000 0x400>;
465 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
470 compatible = "st,stm32-pwm";
476 compatible = "st,stm32-timer-trigger";
482 timers10: timers@40014400 {
483 compatible = "st,stm32-timers";
484 reg = <0x40014400 0x400>;
485 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
490 compatible = "st,stm32-pwm";
496 timers11: timers@40014800 {
497 compatible = "st,stm32-timers";
498 reg = <0x40014800 0x400>;
499 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
504 compatible = "st,stm32-pwm";
510 pwrcfg: power-config@40007000 {
511 compatible = "st,stm32-power-config", "syscon";
512 reg = <0x40007000 0x400>;
516 compatible = "st,stm32f7-crc";
517 reg = <0x40023000 0x400>;
518 clocks = <&rcc 0 12>;
525 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
526 reg = <0x40023800 0x400>;
527 clocks = <&clk_hse>, <&clk_i2s_ckin>;
528 st,syscfg = <&pwrcfg>;
529 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
530 assigned-clock-rates = <1000000>;
533 dma1: dma-controller@40026000 {
534 compatible = "st,stm32-dma";
535 reg = <0x40026000 0x400>;
544 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
549 dma2: dma-controller@40026400 {
550 compatible = "st,stm32-dma";
551 reg = <0x40026400 0x400>;
560 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
566 usbotg_hs: usb@40040000 {
567 compatible = "st,stm32f7-hsotg";
568 reg = <0x40040000 0x40000>;
570 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
572 g-rx-fifo-size = <256>;
573 g-np-tx-fifo-size = <32>;
574 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
578 usbotg_fs: usb@50000000 {
579 compatible = "st,stm32f4x9-fsotg";
580 reg = <0x50000000 0x40000>;
582 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;