arch/arm/boot/dts/stm32f746.dtsi

   1 /*
   2  * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include "skeleton.dtsi"
  44 #include "armv7-m.dtsi"
  45 #include <dt-bindings/clock/stm32fx-clock.h>
  46 #include <dt-bindings/mfd/stm32f7-rcc.h>
  47
  48 / {
  49         clocks {
  50                 clk_hse: clk-hse {
  51                         #clock-cells = <0>;
  52                         compatible = "fixed-clock";
  53                         clock-frequency = <0>;
  54                 };
  55
  56                 clk-lse {
  57                         #clock-cells = <0>;
  58                         compatible = "fixed-clock";
  59                         clock-frequency = <32768>;
  60                 };
  61
  62                 clk-lsi {
  63                         #clock-cells = <0>;
  64                         compatible = "fixed-clock";
  65                         clock-frequency = <32000>;
  66                 };
  67
  68                 clk_i2s_ckin: clk-i2s-ckin {
  69                         #clock-cells = <0>;
  70                         compatible = "fixed-clock";
  71                         clock-frequency = <48000000>;
  72                 };
  73         };
  74
  75         soc {
  76                 timer2: timer@40000000 {
  77                         compatible = "st,stm32-timer";
  78                         reg = <0x40000000 0x400>;
  79                         interrupts = <28>;
  80                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
  81                         status = "disabled";
  82                 };
  83
  84                 timers2: timers@40000000 {
  85                         #address-cells = <1>;
  86                         #size-cells = <0>;
  87                         compatible = "st,stm32-timers";
  88                         reg = <0x40000000 0x400>;
  89                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
  90                         clock-names = "int";
  91                         status = "disabled";
  92
  93                         pwm {
  94                                 compatible = "st,stm32-pwm";
  95                                 status = "disabled";
  96                         };
  97
  98                         timer@1 {
  99                                 compatible = "st,stm32-timer-trigger";
 100                                 reg = <1>;
 101                                 status = "disabled";
 102                         };
 103                 };
 104
 105                 timer3: timer@40000400 {
 106                         compatible = "st,stm32-timer";
 107                         reg = <0x40000400 0x400>;
 108                         interrupts = <29>;
 109                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
 110                         status = "disabled";
 111                 };
 112
 113                 timers3: timers@40000400 {
 114                         #address-cells = <1>;
 115                         #size-cells = <0>;
 116                         compatible = "st,stm32-timers";
 117                         reg = <0x40000400 0x400>;
 118                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
 119                         clock-names = "int";
 120                         status = "disabled";
 121
 122                         pwm {
 123                                 compatible = "st,stm32-pwm";
 124                                 status = "disabled";
 125                         };
 126
 127                         timer@2 {
 128                                 compatible = "st,stm32-timer-trigger";
 129                                 reg = <2>;
 130                                 status = "disabled";
 131                         };
 132                 };
 133
 134                 timer4: timer@40000800 {
 135                         compatible = "st,stm32-timer";
 136                         reg = <0x40000800 0x400>;
 137                         interrupts = <30>;
 138                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
 139                         status = "disabled";
 140                 };
 141
 142                 timers4: timers@40000800 {
 143                         #address-cells = <1>;
 144                         #size-cells = <0>;
 145                         compatible = "st,stm32-timers";
 146                         reg = <0x40000800 0x400>;
 147                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
 148                         clock-names = "int";
 149                         status = "disabled";
 150
 151                         pwm {
 152                                 compatible = "st,stm32-pwm";
 153                                 status = "disabled";
 154                         };
 155
 156                         timer@3 {
 157                                 compatible = "st,stm32-timer-trigger";
 158                                 reg = <3>;
 159                                 status = "disabled";
 160                         };
 161                 };
 162
 163                 timer5: timer@40000c00 {
 164                         compatible = "st,stm32-timer";
 165                         reg = <0x40000c00 0x400>;
 166                         interrupts = <50>;
 167                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
 168                 };
 169
 170                 timers5: timers@40000c00 {
 171                         #address-cells = <1>;
 172                         #size-cells = <0>;
 173                         compatible = "st,stm32-timers";
 174                         reg = <0x40000C00 0x400>;
 175                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
 176                         clock-names = "int";
 177                         status = "disabled";
 178
 179                         pwm {
 180                                 compatible = "st,stm32-pwm";
 181                                 status = "disabled";
 182                         };
 183
 184                         timer@4 {
 185                                 compatible = "st,stm32-timer-trigger";
 186                                 reg = <4>;
 187                                 status = "disabled";
 188                         };
 189                 };
 190
 191                 timer6: timer@40001000 {
 192                         compatible = "st,stm32-timer";
 193                         reg = <0x40001000 0x400>;
 194                         interrupts = <54>;
 195                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
 196                         status = "disabled";
 197                 };
 198
 199                 timers6: timers@40001000 {
 200                         #address-cells = <1>;
 201                         #size-cells = <0>;
 202                         compatible = "st,stm32-timers";
 203                         reg = <0x40001000 0x400>;
 204                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
 205                         clock-names = "int";
 206                         status = "disabled";
 207
 208                         timer@5 {
 209                                 compatible = "st,stm32-timer-trigger";
 210                                 reg = <5>;
 211                                 status = "disabled";
 212                         };
 213                 };
 214
 215                 timer7: timer@40001400 {
 216                         compatible = "st,stm32-timer";
 217                         reg = <0x40001400 0x400>;
 218                         interrupts = <55>;
 219                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
 220                         status = "disabled";
 221                 };
 222
 223                 timers7: timers@40001400 {
 224                         #address-cells = <1>;
 225                         #size-cells = <0>;
 226                         compatible = "st,stm32-timers";
 227                         reg = <0x40001400 0x400>;
 228                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
 229                         clock-names = "int";
 230                         status = "disabled";
 231
 232                         timer@6 {
 233                                 compatible = "st,stm32-timer-trigger";
 234                                 reg = <6>;
 235                                 status = "disabled";
 236                         };
 237                 };
 238
 239                 timers12: timers@40001800 {
 240                         #address-cells = <1>;
 241                         #size-cells = <0>;
 242                         compatible = "st,stm32-timers";
 243                         reg = <0x40001800 0x400>;
 244                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
 245                         clock-names = "int";
 246                         status = "disabled";
 247
 248                         pwm {
 249                                 compatible = "st,stm32-pwm";
 250                                 status = "disabled";
 251                         };
 252
 253                         timer@11 {
 254                                 compatible = "st,stm32-timer-trigger";
 255                                 reg = <11>;
 256                                 status = "disabled";
 257                         };
 258                 };
 259
 260                 timers13: timers@40001c00 {
 261                         compatible = "st,stm32-timers";
 262                         reg = <0x40001C00 0x400>;
 263                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
 264                         clock-names = "int";
 265                         status = "disabled";
 266
 267                         pwm {
 268                                 compatible = "st,stm32-pwm";
 269                                 status = "disabled";
 270                         };
 271                 };
 272
 273                 timers14: timers@40002000 {
 274                         compatible = "st,stm32-timers";
 275                         reg = <0x40002000 0x400>;
 276                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
 277                         clock-names = "int";
 278                         status = "disabled";
 279
 280                         pwm {
 281                                 compatible = "st,stm32-pwm";
 282                                 status = "disabled";
 283                         };
 284                 };
 285
 286                 rtc: rtc@40002800 {
 287                         compatible = "st,stm32-rtc";
 288                         reg = <0x40002800 0x400>;
 289                         clocks = <&rcc 1 CLK_RTC>;
 290                         clock-names = "ck_rtc";
 291                         assigned-clocks = <&rcc 1 CLK_RTC>;
 292                         assigned-clock-parents = <&rcc 1 CLK_LSE>;
 293                         interrupt-parent = <&exti>;
 294                         interrupts = <17 1>;
 295                         interrupt-names = "alarm";
 296                         st,syscfg = <&pwrcfg 0x00 0x100>;
 297                         status = "disabled";
 298                 };
 299
 300                 usart2: serial@40004400 {
 301                         compatible = "st,stm32f7-uart";
 302                         reg = <0x40004400 0x400>;
 303                         interrupts = <38>;
 304                         clocks = <&rcc 1 CLK_USART2>;
 305                         status = "disabled";
 306                 };
 307
 308                 usart3: serial@40004800 {
 309                         compatible = "st,stm32f7-uart";
 310                         reg = <0x40004800 0x400>;
 311                         interrupts = <39>;
 312                         clocks = <&rcc 1 CLK_USART3>;
 313                         status = "disabled";
 314                 };
 315
 316                 usart4: serial@40004c00 {
 317                         compatible = "st,stm32f7-uart";
 318                         reg = <0x40004c00 0x400>;
 319                         interrupts = <52>;
 320                         clocks = <&rcc 1 CLK_UART4>;
 321                         status = "disabled";
 322                 };
 323
 324                 usart5: serial@40005000 {
 325                         compatible = "st,stm32f7-uart";
 326                         reg = <0x40005000 0x400>;
 327                         interrupts = <53>;
 328                         clocks = <&rcc 1 CLK_UART5>;
 329                         status = "disabled";
 330                 };
 331
 332                 i2c1: i2c@40005400 {
 333                         compatible = "st,stm32f7-i2c";
 334                         reg = <0x40005400 0x400>;
 335                         interrupts = <31>,
 336                                      <32>;
 337                         resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
 338                         clocks = <&rcc 1 CLK_I2C1>;
 339                         #address-cells = <1>;
 340                         #size-cells = <0>;
 341                         status = "disabled";
 342                 };
 343
 344                 i2c2: i2c@40005800 {
 345                         compatible = "st,stm32f7-i2c";
 346                         reg = <0x40005800 0x400>;
 347                         interrupts = <33>,
 348                                      <34>;
 349                         resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
 350                         clocks = <&rcc 1 CLK_I2C2>;
 351                         #address-cells = <1>;
 352                         #size-cells = <0>;
 353                         status = "disabled";
 354                 };
 355
 356                 i2c3: i2c@40005c00 {
 357                         compatible = "st,stm32f7-i2c";
 358                         reg = <0x40005c00 0x400>;
 359                         interrupts = <72>,
 360                                      <73>;
 361                         resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
 362                         clocks = <&rcc 1 CLK_I2C3>;
 363                         #address-cells = <1>;
 364                         #size-cells = <0>;
 365                         status = "disabled";
 366                 };
 367
 368                 i2c4: i2c@40006000 {
 369                         compatible = "st,stm32f7-i2c";
 370                         reg = <0x40006000 0x400>;
 371                         interrupts = <95>,
 372                                      <96>;
 373                         resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
 374                         clocks = <&rcc 1 CLK_I2C4>;
 375                         #address-cells = <1>;
 376                         #size-cells = <0>;
 377                         status = "disabled";
 378                 };
 379
 380                 cec: cec@40006c00 {
 381                         compatible = "st,stm32-cec";
 382                         reg = <0x40006C00 0x400>;
 383                         interrupts = <94>;
 384                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
 385                         clock-names = "cec", "hdmi-cec";
 386                         status = "disabled";
 387                 };
 388
 389                 usart7: serial@40007800 {
 390                         compatible = "st,stm32f7-uart";
 391                         reg = <0x40007800 0x400>;
 392                         interrupts = <82>;
 393                         clocks = <&rcc 1 CLK_UART7>;
 394                         status = "disabled";
 395                 };
 396
 397                 usart8: serial@40007c00 {
 398                         compatible = "st,stm32f7-uart";
 399                         reg = <0x40007c00 0x400>;
 400                         interrupts = <83>;
 401                         clocks = <&rcc 1 CLK_UART8>;
 402                         status = "disabled";
 403                 };
 404
 405                 timers1: timers@40010000 {
 406                         #address-cells = <1>;
 407                         #size-cells = <0>;
 408                         compatible = "st,stm32-timers";
 409                         reg = <0x40010000 0x400>;
 410                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
 411                         clock-names = "int";
 412                         status = "disabled";
 413
 414                         pwm {
 415                                 compatible = "st,stm32-pwm";
 416                                 status = "disabled";
 417                         };
 418
 419                         timer@0 {
 420                                 compatible = "st,stm32-timer-trigger";
 421                                 reg = <0>;
 422                                 status = "disabled";
 423                         };
 424                 };
 425
 426                 timers8: timers@40010400 {
 427                         #address-cells = <1>;
 428                         #size-cells = <0>;
 429                         compatible = "st,stm32-timers";
 430                         reg = <0x40010400 0x400>;
 431                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
 432                         clock-names = "int";
 433                         status = "disabled";
 434
 435                         pwm {
 436                                 compatible = "st,stm32-pwm";
 437                                 status = "disabled";
 438                         };
 439
 440                         timer@7 {
 441                                 compatible = "st,stm32-timer-trigger";
 442                                 reg = <7>;
 443                                 status = "disabled";
 444                         };
 445                 };
 446
 447                 usart1: serial@40011000 {
 448                         compatible = "st,stm32f7-uart";
 449                         reg = <0x40011000 0x400>;
 450                         interrupts = <37>;
 451                         clocks = <&rcc 1 CLK_USART1>;
 452                         status = "disabled";
 453                 };
 454
 455                 usart6: serial@40011400 {
 456                         compatible = "st,stm32f7-uart";
 457                         reg = <0x40011400 0x400>;
 458                         interrupts = <71>;
 459                         clocks = <&rcc 1 CLK_USART6>;
 460                         status = "disabled";
 461                 };
 462
 463                 sdio2: sdio2@40011c00 {
 464                         compatible = "arm,pl180", "arm,primecell";
 465                         arm,primecell-periphid = <0x00880180>;
 466                         reg = <0x40011c00 0x400>;
 467                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
 468                         clock-names = "apb_pclk";
 469                         interrupts = <103>;
 470                         max-frequency = <48000000>;
 471                         status = "disabled";
 472                 };
 473
 474                 sdio1: sdio1@40012c00 {
 475                         compatible = "arm,pl180", "arm,primecell";
 476                         arm,primecell-periphid = <0x00880180>;
 477                         reg = <0x40012c00 0x400>;
 478                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
 479                         clock-names = "apb_pclk";
 480                         interrupts = <49>;
 481                         max-frequency = <48000000>;
 482                         status = "disabled";
 483                 };
 484
 485                 syscfg: system-config@40013800 {
 486                         compatible = "syscon";
 487                         reg = <0x40013800 0x400>;
 488                 };
 489
 490                 exti: interrupt-controller@40013c00 {
 491                         compatible = "st,stm32-exti";
 492                         interrupt-controller;
 493                         #interrupt-cells = <2>;
 494                         reg = <0x40013C00 0x400>;
 495                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
 496                 };
 497
 498                 timers9: timers@40014000 {
 499                         #address-cells = <1>;
 500                         #size-cells = <0>;
 501                         compatible = "st,stm32-timers";
 502                         reg = <0x40014000 0x400>;
 503                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
 504                         clock-names = "int";
 505                         status = "disabled";
 506
 507                         pwm {
 508                                 compatible = "st,stm32-pwm";
 509                                 status = "disabled";
 510                         };
 511
 512                         timer@8 {
 513                                 compatible = "st,stm32-timer-trigger";
 514                                 reg = <8>;
 515                                 status = "disabled";
 516                         };
 517                 };
 518
 519                 timers10: timers@40014400 {
 520                         compatible = "st,stm32-timers";
 521                         reg = <0x40014400 0x400>;
 522                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
 523                         clock-names = "int";
 524                         status = "disabled";
 525
 526                         pwm {
 527                                 compatible = "st,stm32-pwm";
 528                                 status = "disabled";
 529                         };
 530                 };
 531
 532                 timers11: timers@40014800 {
 533                         compatible = "st,stm32-timers";
 534                         reg = <0x40014800 0x400>;
 535                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
 536                         clock-names = "int";
 537                         status = "disabled";
 538
 539                         pwm {
 540                                 compatible = "st,stm32-pwm";
 541                                 status = "disabled";
 542                         };
 543                 };
 544
 545                 pwrcfg: power-config@40007000 {
 546                         compatible = "syscon";
 547                         reg = <0x40007000 0x400>;
 548                 };
 549
 550                 crc: crc@40023000 {
 551                         compatible = "st,stm32f7-crc";
 552                         reg = <0x40023000 0x400>;
 553                         clocks = <&rcc 0 12>;
 554                         status = "disabled";
 555                 };
 556
 557                 rcc: rcc@40023800 {
 558                         #reset-cells = <1>;
 559                         #clock-cells = <2>;
 560                         compatible = "st,stm32f746-rcc", "st,stm32-rcc";
 561                         reg = <0x40023800 0x400>;
 562                         clocks = <&clk_hse>, <&clk_i2s_ckin>;
 563                         st,syscfg = <&pwrcfg>;
 564                         assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
 565                         assigned-clock-rates = <1000000>;
 566                 };
 567
 568                 dma1: dma@40026000 {
 569                         compatible = "st,stm32-dma";
 570                         reg = <0x40026000 0x400>;
 571                         interrupts = <11>,
 572                                      <12>,
 573                                      <13>,
 574                                      <14>,
 575                                      <15>,
 576                                      <16>,
 577                                      <17>,
 578                                      <47>;
 579                         clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
 580                         #dma-cells = <4>;
 581                         status = "disabled";
 582                 };
 583
 584                 dma2: dma@40026400 {
 585                         compatible = "st,stm32-dma";
 586                         reg = <0x40026400 0x400>;
 587                         interrupts = <56>,
 588                                      <57>,
 589                                      <58>,
 590                                      <59>,
 591                                      <60>,
 592                                      <68>,
 593                                      <69>,
 594                                      <70>;
 595                         clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
 596                         #dma-cells = <4>;
 597                         st,mem2mem;
 598                         status = "disabled";
 599                 };
 600
 601                 usbotg_hs: usb@40040000 {
 602                         compatible = "st,stm32f7-hsotg";
 603                         reg = <0x40040000 0x40000>;
 604                         interrupts = <77>;
 605                         clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
 606                         clock-names = "otg";
 607                         g-rx-fifo-size = <256>;
 608                         g-np-tx-fifo-size = <32>;
 609                         g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
 610                         status = "disabled";
 611                 };
 612
 613                 usbotg_fs: usb@50000000 {
 614                         compatible = "st,stm32f4x9-fsotg";
 615                         reg = <0x50000000 0x40000>;
 616                         interrupts = <67>;
 617                         clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
 618                         clock-names = "otg";
 619                         status = "disabled";
 620                 };
 621         };
 622 };
 623
 624 &systick {
 625         clocks = <&rcc 1 0>;
 626         status = "okay";
 627 };