arch/arm/boot/dts/stm32f746.dtsi

   1 /*
   2  * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include "armv7-m.dtsi"
  44 #include <dt-bindings/clock/stm32fx-clock.h>
  45 #include <dt-bindings/mfd/stm32f7-rcc.h>
  46
  47 / {
  48         #address-cells = <1>;
  49         #size-cells = <1>;
  50
  51         clocks {
  52                 clk_hse: clk-hse {
  53                         #clock-cells = <0>;
  54                         compatible = "fixed-clock";
  55                         clock-frequency = <0>;
  56                 };
  57
  58                 clk-lse {
  59                         #clock-cells = <0>;
  60                         compatible = "fixed-clock";
  61                         clock-frequency = <32768>;
  62                 };
  63
  64                 clk-lsi {
  65                         #clock-cells = <0>;
  66                         compatible = "fixed-clock";
  67                         clock-frequency = <32000>;
  68                 };
  69
  70                 clk_i2s_ckin: clk-i2s-ckin {
  71                         #clock-cells = <0>;
  72                         compatible = "fixed-clock";
  73                         clock-frequency = <48000000>;
  74                 };
  75         };
  76
  77         soc {
  78                 timer2: timer@40000000 {
  79                         compatible = "st,stm32-timer";
  80                         reg = <0x40000000 0x400>;
  81                         interrupts = <28>;
  82                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
  83                         status = "disabled";
  84                 };
  85
  86                 timers2: timers@40000000 {
  87                         #address-cells = <1>;
  88                         #size-cells = <0>;
  89                         compatible = "st,stm32-timers";
  90                         reg = <0x40000000 0x400>;
  91                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
  92                         clock-names = "int";
  93                         status = "disabled";
  94
  95                         pwm {
  96                                 compatible = "st,stm32-pwm";
  97                                 #pwm-cells = <3>;
  98                                 status = "disabled";
  99                         };
 100
 101                         timer@1 {
 102                                 compatible = "st,stm32-timer-trigger";
 103                                 reg = <1>;
 104                                 status = "disabled";
 105                         };
 106                 };
 107
 108                 timer3: timer@40000400 {
 109                         compatible = "st,stm32-timer";
 110                         reg = <0x40000400 0x400>;
 111                         interrupts = <29>;
 112                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
 113                         status = "disabled";
 114                 };
 115
 116                 timers3: timers@40000400 {
 117                         #address-cells = <1>;
 118                         #size-cells = <0>;
 119                         compatible = "st,stm32-timers";
 120                         reg = <0x40000400 0x400>;
 121                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
 122                         clock-names = "int";
 123                         status = "disabled";
 124
 125                         pwm {
 126                                 compatible = "st,stm32-pwm";
 127                                 #pwm-cells = <3>;
 128                                 status = "disabled";
 129                         };
 130
 131                         timer@2 {
 132                                 compatible = "st,stm32-timer-trigger";
 133                                 reg = <2>;
 134                                 status = "disabled";
 135                         };
 136                 };
 137
 138                 timer4: timer@40000800 {
 139                         compatible = "st,stm32-timer";
 140                         reg = <0x40000800 0x400>;
 141                         interrupts = <30>;
 142                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
 143                         status = "disabled";
 144                 };
 145
 146                 timers4: timers@40000800 {
 147                         #address-cells = <1>;
 148                         #size-cells = <0>;
 149                         compatible = "st,stm32-timers";
 150                         reg = <0x40000800 0x400>;
 151                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
 152                         clock-names = "int";
 153                         status = "disabled";
 154
 155                         pwm {
 156                                 compatible = "st,stm32-pwm";
 157                                 #pwm-cells = <3>;
 158                                 status = "disabled";
 159                         };
 160
 161                         timer@3 {
 162                                 compatible = "st,stm32-timer-trigger";
 163                                 reg = <3>;
 164                                 status = "disabled";
 165                         };
 166                 };
 167
 168                 timer5: timer@40000c00 {
 169                         compatible = "st,stm32-timer";
 170                         reg = <0x40000c00 0x400>;
 171                         interrupts = <50>;
 172                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
 173                 };
 174
 175                 timers5: timers@40000c00 {
 176                         #address-cells = <1>;
 177                         #size-cells = <0>;
 178                         compatible = "st,stm32-timers";
 179                         reg = <0x40000C00 0x400>;
 180                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
 181                         clock-names = "int";
 182                         status = "disabled";
 183
 184                         pwm {
 185                                 compatible = "st,stm32-pwm";
 186                                 #pwm-cells = <3>;
 187                                 status = "disabled";
 188                         };
 189
 190                         timer@4 {
 191                                 compatible = "st,stm32-timer-trigger";
 192                                 reg = <4>;
 193                                 status = "disabled";
 194                         };
 195                 };
 196
 197                 timer6: timer@40001000 {
 198                         compatible = "st,stm32-timer";
 199                         reg = <0x40001000 0x400>;
 200                         interrupts = <54>;
 201                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
 202                         status = "disabled";
 203                 };
 204
 205                 timers6: timers@40001000 {
 206                         #address-cells = <1>;
 207                         #size-cells = <0>;
 208                         compatible = "st,stm32-timers";
 209                         reg = <0x40001000 0x400>;
 210                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
 211                         clock-names = "int";
 212                         status = "disabled";
 213
 214                         timer@5 {
 215                                 compatible = "st,stm32-timer-trigger";
 216                                 reg = <5>;
 217                                 status = "disabled";
 218                         };
 219                 };
 220
 221                 timer7: timer@40001400 {
 222                         compatible = "st,stm32-timer";
 223                         reg = <0x40001400 0x400>;
 224                         interrupts = <55>;
 225                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
 226                         status = "disabled";
 227                 };
 228
 229                 timers7: timers@40001400 {
 230                         #address-cells = <1>;
 231                         #size-cells = <0>;
 232                         compatible = "st,stm32-timers";
 233                         reg = <0x40001400 0x400>;
 234                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
 235                         clock-names = "int";
 236                         status = "disabled";
 237
 238                         timer@6 {
 239                                 compatible = "st,stm32-timer-trigger";
 240                                 reg = <6>;
 241                                 status = "disabled";
 242                         };
 243                 };
 244
 245                 timers12: timers@40001800 {
 246                         #address-cells = <1>;
 247                         #size-cells = <0>;
 248                         compatible = "st,stm32-timers";
 249                         reg = <0x40001800 0x400>;
 250                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
 251                         clock-names = "int";
 252                         status = "disabled";
 253
 254                         pwm {
 255                                 compatible = "st,stm32-pwm";
 256                                 #pwm-cells = <3>;
 257                                 status = "disabled";
 258                         };
 259
 260                         timer@11 {
 261                                 compatible = "st,stm32-timer-trigger";
 262                                 reg = <11>;
 263                                 status = "disabled";
 264                         };
 265                 };
 266
 267                 timers13: timers@40001c00 {
 268                         compatible = "st,stm32-timers";
 269                         reg = <0x40001C00 0x400>;
 270                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
 271                         clock-names = "int";
 272                         status = "disabled";
 273
 274                         pwm {
 275                                 compatible = "st,stm32-pwm";
 276                                 #pwm-cells = <3>;
 277                                 status = "disabled";
 278                         };
 279                 };
 280
 281                 timers14: timers@40002000 {
 282                         compatible = "st,stm32-timers";
 283                         reg = <0x40002000 0x400>;
 284                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
 285                         clock-names = "int";
 286                         status = "disabled";
 287
 288                         pwm {
 289                                 compatible = "st,stm32-pwm";
 290                                 #pwm-cells = <3>;
 291                                 status = "disabled";
 292                         };
 293                 };
 294
 295                 rtc: rtc@40002800 {
 296                         compatible = "st,stm32-rtc";
 297                         reg = <0x40002800 0x400>;
 298                         clocks = <&rcc 1 CLK_RTC>;
 299                         clock-names = "ck_rtc";
 300                         assigned-clocks = <&rcc 1 CLK_RTC>;
 301                         assigned-clock-parents = <&rcc 1 CLK_LSE>;
 302                         interrupt-parent = <&exti>;
 303                         interrupts = <17 1>;
 304                         interrupt-names = "alarm";
 305                         st,syscfg = <&pwrcfg 0x00 0x100>;
 306                         status = "disabled";
 307                 };
 308
 309                 usart2: serial@40004400 {
 310                         compatible = "st,stm32f7-uart";
 311                         reg = <0x40004400 0x400>;
 312                         interrupts = <38>;
 313                         clocks = <&rcc 1 CLK_USART2>;
 314                         status = "disabled";
 315                 };
 316
 317                 usart3: serial@40004800 {
 318                         compatible = "st,stm32f7-uart";
 319                         reg = <0x40004800 0x400>;
 320                         interrupts = <39>;
 321                         clocks = <&rcc 1 CLK_USART3>;
 322                         status = "disabled";
 323                 };
 324
 325                 usart4: serial@40004c00 {
 326                         compatible = "st,stm32f7-uart";
 327                         reg = <0x40004c00 0x400>;
 328                         interrupts = <52>;
 329                         clocks = <&rcc 1 CLK_UART4>;
 330                         status = "disabled";
 331                 };
 332
 333                 usart5: serial@40005000 {
 334                         compatible = "st,stm32f7-uart";
 335                         reg = <0x40005000 0x400>;
 336                         interrupts = <53>;
 337                         clocks = <&rcc 1 CLK_UART5>;
 338                         status = "disabled";
 339                 };
 340
 341                 i2c1: i2c@40005400 {
 342                         compatible = "st,stm32f7-i2c";
 343                         reg = <0x40005400 0x400>;
 344                         interrupts = <31>,
 345                                      <32>;
 346                         resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
 347                         clocks = <&rcc 1 CLK_I2C1>;
 348                         #address-cells = <1>;
 349                         #size-cells = <0>;
 350                         status = "disabled";
 351                 };
 352
 353                 i2c2: i2c@40005800 {
 354                         compatible = "st,stm32f7-i2c";
 355                         reg = <0x40005800 0x400>;
 356                         interrupts = <33>,
 357                                      <34>;
 358                         resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
 359                         clocks = <&rcc 1 CLK_I2C2>;
 360                         #address-cells = <1>;
 361                         #size-cells = <0>;
 362                         status = "disabled";
 363                 };
 364
 365                 i2c3: i2c@40005c00 {
 366                         compatible = "st,stm32f7-i2c";
 367                         reg = <0x40005c00 0x400>;
 368                         interrupts = <72>,
 369                                      <73>;
 370                         resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
 371                         clocks = <&rcc 1 CLK_I2C3>;
 372                         #address-cells = <1>;
 373                         #size-cells = <0>;
 374                         status = "disabled";
 375                 };
 376
 377                 i2c4: i2c@40006000 {
 378                         compatible = "st,stm32f7-i2c";
 379                         reg = <0x40006000 0x400>;
 380                         interrupts = <95>,
 381                                      <96>;
 382                         resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
 383                         clocks = <&rcc 1 CLK_I2C4>;
 384                         #address-cells = <1>;
 385                         #size-cells = <0>;
 386                         status = "disabled";
 387                 };
 388
 389                 cec: cec@40006c00 {
 390                         compatible = "st,stm32-cec";
 391                         reg = <0x40006C00 0x400>;
 392                         interrupts = <94>;
 393                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
 394                         clock-names = "cec", "hdmi-cec";
 395                         status = "disabled";
 396                 };
 397
 398                 usart7: serial@40007800 {
 399                         compatible = "st,stm32f7-uart";
 400                         reg = <0x40007800 0x400>;
 401                         interrupts = <82>;
 402                         clocks = <&rcc 1 CLK_UART7>;
 403                         status = "disabled";
 404                 };
 405
 406                 usart8: serial@40007c00 {
 407                         compatible = "st,stm32f7-uart";
 408                         reg = <0x40007c00 0x400>;
 409                         interrupts = <83>;
 410                         clocks = <&rcc 1 CLK_UART8>;
 411                         status = "disabled";
 412                 };
 413
 414                 timers1: timers@40010000 {
 415                         #address-cells = <1>;
 416                         #size-cells = <0>;
 417                         compatible = "st,stm32-timers";
 418                         reg = <0x40010000 0x400>;
 419                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
 420                         clock-names = "int";
 421                         status = "disabled";
 422
 423                         pwm {
 424                                 compatible = "st,stm32-pwm";
 425                                 #pwm-cells = <3>;
 426                                 status = "disabled";
 427                         };
 428
 429                         timer@0 {
 430                                 compatible = "st,stm32-timer-trigger";
 431                                 reg = <0>;
 432                                 status = "disabled";
 433                         };
 434                 };
 435
 436                 timers8: timers@40010400 {
 437                         #address-cells = <1>;
 438                         #size-cells = <0>;
 439                         compatible = "st,stm32-timers";
 440                         reg = <0x40010400 0x400>;
 441                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
 442                         clock-names = "int";
 443                         status = "disabled";
 444
 445                         pwm {
 446                                 compatible = "st,stm32-pwm";
 447                                 #pwm-cells = <3>;
 448                                 status = "disabled";
 449                         };
 450
 451                         timer@7 {
 452                                 compatible = "st,stm32-timer-trigger";
 453                                 reg = <7>;
 454                                 status = "disabled";
 455                         };
 456                 };
 457
 458                 usart1: serial@40011000 {
 459                         compatible = "st,stm32f7-uart";
 460                         reg = <0x40011000 0x400>;
 461                         interrupts = <37>;
 462                         clocks = <&rcc 1 CLK_USART1>;
 463                         status = "disabled";
 464                 };
 465
 466                 usart6: serial@40011400 {
 467                         compatible = "st,stm32f7-uart";
 468                         reg = <0x40011400 0x400>;
 469                         interrupts = <71>;
 470                         clocks = <&rcc 1 CLK_USART6>;
 471                         status = "disabled";
 472                 };
 473
 474                 sdio2: sdio2@40011c00 {
 475                         compatible = "arm,pl180", "arm,primecell";
 476                         arm,primecell-periphid = <0x00880180>;
 477                         reg = <0x40011c00 0x400>;
 478                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
 479                         clock-names = "apb_pclk";
 480                         interrupts = <103>;
 481                         max-frequency = <48000000>;
 482                         status = "disabled";
 483                 };
 484
 485                 sdio1: sdio1@40012c00 {
 486                         compatible = "arm,pl180", "arm,primecell";
 487                         arm,primecell-periphid = <0x00880180>;
 488                         reg = <0x40012c00 0x400>;
 489                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
 490                         clock-names = "apb_pclk";
 491                         interrupts = <49>;
 492                         max-frequency = <48000000>;
 493                         status = "disabled";
 494                 };
 495
 496                 syscfg: system-config@40013800 {
 497                         compatible = "syscon";
 498                         reg = <0x40013800 0x400>;
 499                 };
 500
 501                 exti: interrupt-controller@40013c00 {
 502                         compatible = "st,stm32-exti";
 503                         interrupt-controller;
 504                         #interrupt-cells = <2>;
 505                         reg = <0x40013C00 0x400>;
 506                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
 507                 };
 508
 509                 timers9: timers@40014000 {
 510                         #address-cells = <1>;
 511                         #size-cells = <0>;
 512                         compatible = "st,stm32-timers";
 513                         reg = <0x40014000 0x400>;
 514                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
 515                         clock-names = "int";
 516                         status = "disabled";
 517
 518                         pwm {
 519                                 compatible = "st,stm32-pwm";
 520                                 #pwm-cells = <3>;
 521                                 status = "disabled";
 522                         };
 523
 524                         timer@8 {
 525                                 compatible = "st,stm32-timer-trigger";
 526                                 reg = <8>;
 527                                 status = "disabled";
 528                         };
 529                 };
 530
 531                 timers10: timers@40014400 {
 532                         compatible = "st,stm32-timers";
 533                         reg = <0x40014400 0x400>;
 534                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
 535                         clock-names = "int";
 536                         status = "disabled";
 537
 538                         pwm {
 539                                 compatible = "st,stm32-pwm";
 540                                 #pwm-cells = <3>;
 541                                 status = "disabled";
 542                         };
 543                 };
 544
 545                 timers11: timers@40014800 {
 546                         compatible = "st,stm32-timers";
 547                         reg = <0x40014800 0x400>;
 548                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
 549                         clock-names = "int";
 550                         status = "disabled";
 551
 552                         pwm {
 553                                 compatible = "st,stm32-pwm";
 554                                 #pwm-cells = <3>;
 555                                 status = "disabled";
 556                         };
 557                 };
 558
 559                 pwrcfg: power-config@40007000 {
 560                         compatible = "syscon";
 561                         reg = <0x40007000 0x400>;
 562                 };
 563
 564                 crc: crc@40023000 {
 565                         compatible = "st,stm32f7-crc";
 566                         reg = <0x40023000 0x400>;
 567                         clocks = <&rcc 0 12>;
 568                         status = "disabled";
 569                 };
 570
 571                 rcc: rcc@40023800 {
 572                         #reset-cells = <1>;
 573                         #clock-cells = <2>;
 574                         compatible = "st,stm32f746-rcc", "st,stm32-rcc";
 575                         reg = <0x40023800 0x400>;
 576                         clocks = <&clk_hse>, <&clk_i2s_ckin>;
 577                         st,syscfg = <&pwrcfg>;
 578                         assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
 579                         assigned-clock-rates = <1000000>;
 580                 };
 581
 582                 dma1: dma@40026000 {
 583                         compatible = "st,stm32-dma";
 584                         reg = <0x40026000 0x400>;
 585                         interrupts = <11>,
 586                                      <12>,
 587                                      <13>,
 588                                      <14>,
 589                                      <15>,
 590                                      <16>,
 591                                      <17>,
 592                                      <47>;
 593                         clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
 594                         #dma-cells = <4>;
 595                         status = "disabled";
 596                 };
 597
 598                 dma2: dma@40026400 {
 599                         compatible = "st,stm32-dma";
 600                         reg = <0x40026400 0x400>;
 601                         interrupts = <56>,
 602                                      <57>,
 603                                      <58>,
 604                                      <59>,
 605                                      <60>,
 606                                      <68>,
 607                                      <69>,
 608                                      <70>;
 609                         clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
 610                         #dma-cells = <4>;
 611                         st,mem2mem;
 612                         status = "disabled";
 613                 };
 614
 615                 usbotg_hs: usb@40040000 {
 616                         compatible = "st,stm32f7-hsotg";
 617                         reg = <0x40040000 0x40000>;
 618                         interrupts = <77>;
 619                         clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
 620                         clock-names = "otg";
 621                         g-rx-fifo-size = <256>;
 622                         g-np-tx-fifo-size = <32>;
 623                         g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
 624                         status = "disabled";
 625                 };
 626
 627                 usbotg_fs: usb@50000000 {
 628                         compatible = "st,stm32f4x9-fsotg";
 629                         reg = <0x50000000 0x40000>;
 630                         interrupts = <67>;
 631                         clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
 632                         clock-names = "otg";
 633                         status = "disabled";
 634                 };
 635         };
 636 };
 637
 638 &systick {
 639         clocks = <&rcc 1 0>;
 640         status = "okay";
 641 };