arch/arm/boot/dts/stm32f7-pinctrl.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
   4  * Author: Alexandre Torgue  <alexandre.torgue@st.com> for STMicroelectronics.
   5  */
   6
   7 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
   8 #include <dt-bindings/mfd/stm32f7-rcc.h>
   9
  10 / {
  11         soc {
  12                 pinctrl: pin-controller {
  13                         #address-cells = <1>;
  14                         #size-cells = <1>;
  15                         ranges = <0 0x40020000 0x3000>;
  16                         interrupt-parent = <&exti>;
  17                         st,syscfg = <&syscfg 0x8>;
  18                         pins-are-numbered;
  19
  20                         gpioa: gpio@40020000 {
  21                                 gpio-controller;
  22                                 #gpio-cells = <2>;
  23                                 interrupt-controller;
  24                                 #interrupt-cells = <2>;
  25                                 reg = <0x0 0x400>;
  26                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
  27                                 st,bank-name = "GPIOA";
  28                         };
  29
  30                         gpiob: gpio@40020400 {
  31                                 gpio-controller;
  32                                 #gpio-cells = <2>;
  33                                 interrupt-controller;
  34                                 #interrupt-cells = <2>;
  35                                 reg = <0x400 0x400>;
  36                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
  37                                 st,bank-name = "GPIOB";
  38                         };
  39
  40                         gpioc: gpio@40020800 {
  41                                 gpio-controller;
  42                                 #gpio-cells = <2>;
  43                                 interrupt-controller;
  44                                 #interrupt-cells = <2>;
  45                                 reg = <0x800 0x400>;
  46                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
  47                                 st,bank-name = "GPIOC";
  48                         };
  49
  50                         gpiod: gpio@40020c00 {
  51                                 gpio-controller;
  52                                 #gpio-cells = <2>;
  53                                 interrupt-controller;
  54                                 #interrupt-cells = <2>;
  55                                 reg = <0xc00 0x400>;
  56                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
  57                                 st,bank-name = "GPIOD";
  58                         };
  59
  60                         gpioe: gpio@40021000 {
  61                                 gpio-controller;
  62                                 #gpio-cells = <2>;
  63                                 interrupt-controller;
  64                                 #interrupt-cells = <2>;
  65                                 reg = <0x1000 0x400>;
  66                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
  67                                 st,bank-name = "GPIOE";
  68                         };
  69
  70                         gpiof: gpio@40021400 {
  71                                 gpio-controller;
  72                                 #gpio-cells = <2>;
  73                                 interrupt-controller;
  74                                 #interrupt-cells = <2>;
  75                                 reg = <0x1400 0x400>;
  76                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
  77                                 st,bank-name = "GPIOF";
  78                         };
  79
  80                         gpiog: gpio@40021800 {
  81                                 gpio-controller;
  82                                 #gpio-cells = <2>;
  83                                 interrupt-controller;
  84                                 #interrupt-cells = <2>;
  85                                 reg = <0x1800 0x400>;
  86                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
  87                                 st,bank-name = "GPIOG";
  88                         };
  89
  90                         gpioh: gpio@40021c00 {
  91                                 gpio-controller;
  92                                 #gpio-cells = <2>;
  93                                 interrupt-controller;
  94                                 #interrupt-cells = <2>;
  95                                 reg = <0x1c00 0x400>;
  96                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
  97                                 st,bank-name = "GPIOH";
  98                         };
  99
 100                         gpioi: gpio@40022000 {
 101                                 gpio-controller;
 102                                 #gpio-cells = <2>;
 103                                 interrupt-controller;
 104                                 #interrupt-cells = <2>;
 105                                 reg = <0x2000 0x400>;
 106                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
 107                                 st,bank-name = "GPIOI";
 108                         };
 109
 110                         gpioj: gpio@40022400 {
 111                                 gpio-controller;
 112                                 #gpio-cells = <2>;
 113                                 interrupt-controller;
 114                                 #interrupt-cells = <2>;
 115                                 reg = <0x2400 0x400>;
 116                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
 117                                 st,bank-name = "GPIOJ";
 118                         };
 119
 120                         gpiok: gpio@40022800 {
 121                                 gpio-controller;
 122                                 #gpio-cells = <2>;
 123                                 interrupt-controller;
 124                                 #interrupt-cells = <2>;
 125                                 reg = <0x2800 0x400>;
 126                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
 127                                 st,bank-name = "GPIOK";
 128                         };
 129
 130                         cec_pins_a: cec@0 {
 131                                 pins {
 132                                         pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
 133                                         slew-rate = <0>;
 134                                         drive-open-drain;
 135                                         bias-disable;
 136                                 };
 137                         };
 138
 139                         usart1_pins_a: usart1@0 {
 140                                 pins1 {
 141                                         pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
 142                                         bias-disable;
 143                                         drive-push-pull;
 144                                         slew-rate = <0>;
 145                                 };
 146                                 pins2 {
 147                                         pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
 148                                         bias-disable;
 149                                 };
 150                         };
 151
 152                         usart1_pins_b: usart1@1 {
 153                                 pins1 {
 154                                         pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
 155                                         bias-disable;
 156                                         drive-push-pull;
 157                                         slew-rate = <0>;
 158                                 };
 159                                 pins2 {
 160                                         pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
 161                                         bias-disable;
 162                                 };
 163                         };
 164
 165                         i2c1_pins_b: i2c1@0 {
 166                                 pins {
 167                                         pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
 168                                                  <STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
 169                                         bias-disable;
 170                                         drive-open-drain;
 171                                         slew-rate = <0>;
 172                                 };
 173                         };
 174
 175                         usbotg_hs_pins_a: usbotg-hs@0 {
 176                                 pins {
 177                                         pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
 178                                                  <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
 179                                                  <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
 180                                                  <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
 181                                                  <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
 182                                                  <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
 183                                                  <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
 184                                                  <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
 185                                                  <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
 186                                                  <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
 187                                                  <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
 188                                                  <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
 189                                         bias-disable;
 190                                         drive-push-pull;
 191                                         slew-rate = <2>;
 192                                 };
 193                         };
 194
 195                         usbotg_hs_pins_b: usbotg-hs@1 {
 196                                 pins {
 197                                         pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
 198                                                  <STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
 199                                                  <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
 200                                                  <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
 201                                                  <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
 202                                                  <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
 203                                                  <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
 204                                                  <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
 205                                                  <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
 206                                                  <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
 207                                                  <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
 208                                                  <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
 209                                         bias-disable;
 210                                         drive-push-pull;
 211                                         slew-rate = <2>;
 212                                 };
 213                         };
 214
 215                         usbotg_fs_pins_a: usbotg-fs@0 {
 216                                 pins {
 217                                         pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
 218                                                  <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
 219                                                  <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
 220                                         bias-disable;
 221                                         drive-push-pull;
 222                                         slew-rate = <2>;
 223                                 };
 224                         };
 225
 226                         sdio_pins_a: sdio_pins_a@0 {
 227                                 pins {
 228                                         pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
 229                                                  <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
 230                                                  <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
 231                                                  <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
 232                                                  <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1 CLK */
 233                                                  <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
 234                                         drive-push-pull;
 235                                         slew-rate = <2>;
 236                                 };
 237                         };
 238
 239                         sdio_pins_od_a: sdio_pins_od_a@0 {
 240                                 pins1 {
 241                                         pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
 242                                                  <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
 243                                                  <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
 244                                                  <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
 245                                                  <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1 CLK */
 246                                         drive-push-pull;
 247                                         slew-rate = <2>;
 248                                 };
 249
 250                                 pins2 {
 251                                         pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
 252                                         drive-open-drain;
 253                                         slew-rate = <2>;
 254                                 };
 255                         };
 256
 257                         sdio_pins_b: sdio_pins_b@0 {
 258                                 pins {
 259                                         pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
 260                                                  <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
 261                                                  <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
 262                                                  <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
 263                                                  <STM32_PINMUX('D', 6, AF11)>, /* SDMMC2 CLK */
 264                                                  <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
 265                                         drive-push-pull;
 266                                         slew-rate = <2>;
 267                                 };
 268                         };
 269
 270                         sdio_pins_od_b: sdio_pins_od_b@0 {
 271                                 pins1 {
 272                                         pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
 273                                                  <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
 274                                                  <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
 275                                                  <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
 276                                                  <STM32_PINMUX('D', 6, AF11)>; /* SDMMC2 CLK */
 277                                         drive-push-pull;
 278                                         slew-rate = <2>;
 279                                 };
 280
 281                                 pins2 {
 282                                         pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
 283                                         drive-open-drain;
 284                                         slew-rate = <2>;
 285                                 };
 286                         };
 287                 };
 288         };
 289 };