2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
48 #include "armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
59 compatible = "fixed-clock";
60 clock-frequency = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
71 compatible = "fixed-clock";
72 clock-frequency = <32000>;
75 clk_i2s_ckin: i2s-ckin {
77 compatible = "fixed-clock";
78 clock-frequency = <0>;
83 romem: nvmem@1fff7800 {
84 compatible = "st,stm32f4-otp";
85 reg = <0x1fff7800 0x400>;
96 timer2: timer@40000000 {
97 compatible = "st,stm32-timer";
98 reg = <0x40000000 0x400>;
100 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
104 timers2: timers@40000000 {
105 #address-cells = <1>;
107 compatible = "st,stm32-timers";
108 reg = <0x40000000 0x400>;
109 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
114 compatible = "st,stm32-pwm";
120 compatible = "st,stm32-timer-trigger";
126 timer3: timer@40000400 {
127 compatible = "st,stm32-timer";
128 reg = <0x40000400 0x400>;
130 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
134 timers3: timers@40000400 {
135 #address-cells = <1>;
137 compatible = "st,stm32-timers";
138 reg = <0x40000400 0x400>;
139 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
144 compatible = "st,stm32-pwm";
150 compatible = "st,stm32-timer-trigger";
156 timer4: timer@40000800 {
157 compatible = "st,stm32-timer";
158 reg = <0x40000800 0x400>;
160 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
164 timers4: timers@40000800 {
165 #address-cells = <1>;
167 compatible = "st,stm32-timers";
168 reg = <0x40000800 0x400>;
169 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
174 compatible = "st,stm32-pwm";
180 compatible = "st,stm32-timer-trigger";
186 timer5: timer@40000c00 {
187 compatible = "st,stm32-timer";
188 reg = <0x40000c00 0x400>;
190 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
193 timers5: timers@40000c00 {
194 #address-cells = <1>;
196 compatible = "st,stm32-timers";
197 reg = <0x40000C00 0x400>;
198 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
203 compatible = "st,stm32-pwm";
209 compatible = "st,stm32-timer-trigger";
215 timer6: timer@40001000 {
216 compatible = "st,stm32-timer";
217 reg = <0x40001000 0x400>;
219 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
223 timers6: timers@40001000 {
224 #address-cells = <1>;
226 compatible = "st,stm32-timers";
227 reg = <0x40001000 0x400>;
228 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
233 compatible = "st,stm32-timer-trigger";
239 timer7: timer@40001400 {
240 compatible = "st,stm32-timer";
241 reg = <0x40001400 0x400>;
243 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
247 timers7: timers@40001400 {
248 #address-cells = <1>;
250 compatible = "st,stm32-timers";
251 reg = <0x40001400 0x400>;
252 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
257 compatible = "st,stm32-timer-trigger";
263 timers12: timers@40001800 {
264 #address-cells = <1>;
266 compatible = "st,stm32-timers";
267 reg = <0x40001800 0x400>;
268 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
273 compatible = "st,stm32-pwm";
279 compatible = "st,stm32-timer-trigger";
285 timers13: timers@40001c00 {
286 compatible = "st,stm32-timers";
287 reg = <0x40001C00 0x400>;
288 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
293 compatible = "st,stm32-pwm";
299 timers14: timers@40002000 {
300 compatible = "st,stm32-timers";
301 reg = <0x40002000 0x400>;
302 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
307 compatible = "st,stm32-pwm";
314 compatible = "st,stm32-rtc";
315 reg = <0x40002800 0x400>;
316 clocks = <&rcc 1 CLK_RTC>;
317 clock-names = "ck_rtc";
318 assigned-clocks = <&rcc 1 CLK_RTC>;
319 assigned-clock-parents = <&rcc 1 CLK_LSE>;
320 interrupt-parent = <&exti>;
322 interrupt-names = "alarm";
323 st,syscfg = <&pwrcfg 0x00 0x100>;
327 iwdg: watchdog@40003000 {
328 compatible = "st,stm32-iwdg";
329 reg = <0x40003000 0x400>;
336 #address-cells = <1>;
338 compatible = "st,stm32f4-spi";
339 reg = <0x40003800 0x400>;
341 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
346 #address-cells = <1>;
348 compatible = "st,stm32f4-spi";
349 reg = <0x40003c00 0x400>;
351 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
355 usart2: serial@40004400 {
356 compatible = "st,stm32-uart";
357 reg = <0x40004400 0x400>;
359 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
363 usart3: serial@40004800 {
364 compatible = "st,stm32-uart";
365 reg = <0x40004800 0x400>;
367 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
369 dmas = <&dma1 1 4 0x400 0x0>,
370 <&dma1 3 4 0x400 0x0>;
371 dma-names = "rx", "tx";
374 usart4: serial@40004c00 {
375 compatible = "st,stm32-uart";
376 reg = <0x40004c00 0x400>;
378 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
382 usart5: serial@40005000 {
383 compatible = "st,stm32-uart";
384 reg = <0x40005000 0x400>;
386 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
391 compatible = "st,stm32f4-i2c";
392 reg = <0x40005400 0x400>;
395 resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
396 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
397 #address-cells = <1>;
403 compatible = "st,stm32f4-dac-core";
404 reg = <0x40007400 0x400>;
405 resets = <&rcc STM32F4_APB1_RESET(DAC)>;
406 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
407 clock-names = "pclk";
408 #address-cells = <1>;
413 compatible = "st,stm32-dac";
414 #io-channels-cells = <1>;
420 compatible = "st,stm32-dac";
421 #io-channels-cells = <1>;
427 usart7: serial@40007800 {
428 compatible = "st,stm32-uart";
429 reg = <0x40007800 0x400>;
431 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
435 usart8: serial@40007c00 {
436 compatible = "st,stm32-uart";
437 reg = <0x40007c00 0x400>;
439 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
443 timers1: timers@40010000 {
444 #address-cells = <1>;
446 compatible = "st,stm32-timers";
447 reg = <0x40010000 0x400>;
448 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
453 compatible = "st,stm32-pwm";
459 compatible = "st,stm32-timer-trigger";
465 timers8: timers@40010400 {
466 #address-cells = <1>;
468 compatible = "st,stm32-timers";
469 reg = <0x40010400 0x400>;
470 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
475 compatible = "st,stm32-pwm";
481 compatible = "st,stm32-timer-trigger";
487 usart1: serial@40011000 {
488 compatible = "st,stm32-uart";
489 reg = <0x40011000 0x400>;
491 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
493 dmas = <&dma2 2 4 0x400 0x0>,
494 <&dma2 7 4 0x400 0x0>;
495 dma-names = "rx", "tx";
498 usart6: serial@40011400 {
499 compatible = "st,stm32-uart";
500 reg = <0x40011400 0x400>;
502 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
507 compatible = "st,stm32f4-adc-core";
508 reg = <0x40012000 0x400>;
510 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
512 interrupt-controller;
513 #interrupt-cells = <1>;
514 #address-cells = <1>;
519 compatible = "st,stm32f4-adc";
520 #io-channel-cells = <1>;
522 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
523 interrupt-parent = <&adc>;
525 dmas = <&dma2 0 0 0x400 0x0>;
531 compatible = "st,stm32f4-adc";
532 #io-channel-cells = <1>;
534 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
535 interrupt-parent = <&adc>;
537 dmas = <&dma2 3 1 0x400 0x0>;
543 compatible = "st,stm32f4-adc";
544 #io-channel-cells = <1>;
546 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
547 interrupt-parent = <&adc>;
549 dmas = <&dma2 1 2 0x400 0x0>;
555 sdio: sdio@40012c00 {
556 compatible = "arm,pl180", "arm,primecell";
557 arm,primecell-periphid = <0x00880180>;
558 reg = <0x40012c00 0x400>;
559 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
560 clock-names = "apb_pclk";
562 max-frequency = <48000000>;
567 #address-cells = <1>;
569 compatible = "st,stm32f4-spi";
570 reg = <0x40013000 0x400>;
572 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
577 #address-cells = <1>;
579 compatible = "st,stm32f4-spi";
580 reg = <0x40013400 0x400>;
582 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
586 syscfg: system-config@40013800 {
587 compatible = "syscon";
588 reg = <0x40013800 0x400>;
591 exti: interrupt-controller@40013c00 {
592 compatible = "st,stm32-exti";
593 interrupt-controller;
594 #interrupt-cells = <2>;
595 reg = <0x40013C00 0x400>;
596 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
599 timers9: timers@40014000 {
600 #address-cells = <1>;
602 compatible = "st,stm32-timers";
603 reg = <0x40014000 0x400>;
604 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
609 compatible = "st,stm32-pwm";
615 compatible = "st,stm32-timer-trigger";
621 timers10: timers@40014400 {
622 compatible = "st,stm32-timers";
623 reg = <0x40014400 0x400>;
624 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
629 compatible = "st,stm32-pwm";
635 timers11: timers@40014800 {
636 compatible = "st,stm32-timers";
637 reg = <0x40014800 0x400>;
638 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
643 compatible = "st,stm32-pwm";
650 #address-cells = <1>;
652 compatible = "st,stm32f4-spi";
653 reg = <0x40015000 0x400>;
655 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
660 #address-cells = <1>;
662 compatible = "st,stm32f4-spi";
663 reg = <0x40015400 0x400>;
665 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
669 pwrcfg: power-config@40007000 {
670 compatible = "syscon";
671 reg = <0x40007000 0x400>;
674 ltdc: display-controller@40016800 {
675 compatible = "st,stm32-ltdc";
676 reg = <0x40016800 0x200>;
677 interrupts = <88>, <89>;
678 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
679 clocks = <&rcc 1 CLK_LCD>;
685 compatible = "st,stm32f4-crc";
686 reg = <0x40023000 0x400>;
687 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
694 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
695 reg = <0x40023800 0x400>;
696 clocks = <&clk_hse>, <&clk_i2s_ckin>;
697 st,syscfg = <&pwrcfg>;
698 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
699 assigned-clock-rates = <1000000>;
702 dma1: dma-controller@40026000 {
703 compatible = "st,stm32-dma";
704 reg = <0x40026000 0x400>;
713 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
717 dma2: dma-controller@40026400 {
718 compatible = "st,stm32-dma";
719 reg = <0x40026400 0x400>;
728 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
733 mac: ethernet@40028000 {
734 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
735 reg = <0x40028000 0x8000>;
736 reg-names = "stmmaceth";
738 interrupt-names = "macirq";
739 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
740 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
741 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
742 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
743 st,syscon = <&syscfg 0x4>;
749 usbotg_hs: usb@40040000 {
750 compatible = "snps,dwc2";
751 reg = <0x40040000 0x40000>;
753 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
758 usbotg_fs: usb@50000000 {
759 compatible = "st,stm32f4x9-fsotg";
760 reg = <0x50000000 0x40000>;
762 clocks = <&rcc 0 39>;
767 dcmi: dcmi@50050000 {
768 compatible = "st,stm32-dcmi";
769 reg = <0x50050000 0x400>;
771 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
772 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
773 clock-names = "mclk";
774 pinctrl-names = "default";
775 pinctrl-0 = <&dcmi_pins>;
776 dmas = <&dma2 1 1 0x414 0x3>;
782 compatible = "st,stm32-rng";
783 reg = <0x50060800 0x400>;
785 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
792 clocks = <&rcc 1 SYSTICK>;