arch/arm/boot/dts/stm32f429.dtsi

   1 /*
   2  * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include "skeleton.dtsi"
  49 #include "armv7-m.dtsi"
  50 #include <dt-bindings/clock/stm32fx-clock.h>
  51 #include <dt-bindings/mfd/stm32f4-rcc.h>
  52
  53 / {
  54         clocks {
  55                 clk_hse: clk-hse {
  56                         #clock-cells = <0>;
  57                         compatible = "fixed-clock";
  58                         clock-frequency = <0>;
  59                 };
  60
  61                 clk-lse {
  62                         #clock-cells = <0>;
  63                         compatible = "fixed-clock";
  64                         clock-frequency = <32768>;
  65                 };
  66
  67                 clk_lsi: clk-lsi {
  68                         #clock-cells = <0>;
  69                         compatible = "fixed-clock";
  70                         clock-frequency = <32000>;
  71                 };
  72
  73                 clk_i2s_ckin: i2s-ckin {
  74                         #clock-cells = <0>;
  75                         compatible = "fixed-clock";
  76                         clock-frequency = <0>;
  77                 };
  78         };
  79
  80         soc {
  81                 timer2: timer@40000000 {
  82                         compatible = "st,stm32-timer";
  83                         reg = <0x40000000 0x400>;
  84                         interrupts = <28>;
  85                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
  86                         status = "disabled";
  87                 };
  88
  89                 timers2: timers@40000000 {
  90                         #address-cells = <1>;
  91                         #size-cells = <0>;
  92                         compatible = "st,stm32-timers";
  93                         reg = <0x40000000 0x400>;
  94                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
  95                         clock-names = "int";
  96                         status = "disabled";
  97
  98                         pwm {
  99                                 compatible = "st,stm32-pwm";
 100                                 status = "disabled";
 101                         };
 102
 103                         timer@1 {
 104                                 compatible = "st,stm32-timer-trigger";
 105                                 reg = <1>;
 106                                 status = "disabled";
 107                         };
 108                 };
 109
 110                 timer3: timer@40000400 {
 111                         compatible = "st,stm32-timer";
 112                         reg = <0x40000400 0x400>;
 113                         interrupts = <29>;
 114                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
 115                         status = "disabled";
 116                 };
 117
 118                 timers3: timers@40000400 {
 119                         #address-cells = <1>;
 120                         #size-cells = <0>;
 121                         compatible = "st,stm32-timers";
 122                         reg = <0x40000400 0x400>;
 123                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
 124                         clock-names = "int";
 125                         status = "disabled";
 126
 127                         pwm {
 128                                 compatible = "st,stm32-pwm";
 129                                 status = "disabled";
 130                         };
 131
 132                         timer@2 {
 133                                 compatible = "st,stm32-timer-trigger";
 134                                 reg = <2>;
 135                                 status = "disabled";
 136                         };
 137                 };
 138
 139                 timer4: timer@40000800 {
 140                         compatible = "st,stm32-timer";
 141                         reg = <0x40000800 0x400>;
 142                         interrupts = <30>;
 143                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
 144                         status = "disabled";
 145                 };
 146
 147                 timers4: timers@40000800 {
 148                         #address-cells = <1>;
 149                         #size-cells = <0>;
 150                         compatible = "st,stm32-timers";
 151                         reg = <0x40000800 0x400>;
 152                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
 153                         clock-names = "int";
 154                         status = "disabled";
 155
 156                         pwm {
 157                                 compatible = "st,stm32-pwm";
 158                                 status = "disabled";
 159                         };
 160
 161                         timer@3 {
 162                                 compatible = "st,stm32-timer-trigger";
 163                                 reg = <3>;
 164                                 status = "disabled";
 165                         };
 166                 };
 167
 168                 timer5: timer@40000c00 {
 169                         compatible = "st,stm32-timer";
 170                         reg = <0x40000c00 0x400>;
 171                         interrupts = <50>;
 172                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
 173                 };
 174
 175                 timers5: timers@40000c00 {
 176                         #address-cells = <1>;
 177                         #size-cells = <0>;
 178                         compatible = "st,stm32-timers";
 179                         reg = <0x40000C00 0x400>;
 180                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
 181                         clock-names = "int";
 182                         status = "disabled";
 183
 184                         pwm {
 185                                 compatible = "st,stm32-pwm";
 186                                 status = "disabled";
 187                         };
 188
 189                         timer@4 {
 190                                 compatible = "st,stm32-timer-trigger";
 191                                 reg = <4>;
 192                                 status = "disabled";
 193                         };
 194                 };
 195
 196                 timer6: timer@40001000 {
 197                         compatible = "st,stm32-timer";
 198                         reg = <0x40001000 0x400>;
 199                         interrupts = <54>;
 200                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
 201                         status = "disabled";
 202                 };
 203
 204                 timers6: timers@40001000 {
 205                         #address-cells = <1>;
 206                         #size-cells = <0>;
 207                         compatible = "st,stm32-timers";
 208                         reg = <0x40001000 0x400>;
 209                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
 210                         clock-names = "int";
 211                         status = "disabled";
 212
 213                         timer@5 {
 214                                 compatible = "st,stm32-timer-trigger";
 215                                 reg = <5>;
 216                                 status = "disabled";
 217                         };
 218                 };
 219
 220                 timer7: timer@40001400 {
 221                         compatible = "st,stm32-timer";
 222                         reg = <0x40001400 0x400>;
 223                         interrupts = <55>;
 224                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
 225                         status = "disabled";
 226                 };
 227
 228                 timers7: timers@40001400 {
 229                         #address-cells = <1>;
 230                         #size-cells = <0>;
 231                         compatible = "st,stm32-timers";
 232                         reg = <0x40001400 0x400>;
 233                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
 234                         clock-names = "int";
 235                         status = "disabled";
 236
 237                         timer@6 {
 238                                 compatible = "st,stm32-timer-trigger";
 239                                 reg = <6>;
 240                                 status = "disabled";
 241                         };
 242                 };
 243
 244                 timers12: timers@40001800 {
 245                         #address-cells = <1>;
 246                         #size-cells = <0>;
 247                         compatible = "st,stm32-timers";
 248                         reg = <0x40001800 0x400>;
 249                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
 250                         clock-names = "int";
 251                         status = "disabled";
 252
 253                         pwm {
 254                                 compatible = "st,stm32-pwm";
 255                                 status = "disabled";
 256                         };
 257
 258                         timer@11 {
 259                                 compatible = "st,stm32-timer-trigger";
 260                                 reg = <11>;
 261                                 status = "disabled";
 262                         };
 263                 };
 264
 265                 timers13: timers@40001c00 {
 266                         compatible = "st,stm32-timers";
 267                         reg = <0x40001C00 0x400>;
 268                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
 269                         clock-names = "int";
 270                         status = "disabled";
 271
 272                         pwm {
 273                                 compatible = "st,stm32-pwm";
 274                                 status = "disabled";
 275                         };
 276                 };
 277
 278                 timers14: timers@40002000 {
 279                         compatible = "st,stm32-timers";
 280                         reg = <0x40002000 0x400>;
 281                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
 282                         clock-names = "int";
 283                         status = "disabled";
 284
 285                         pwm {
 286                                 compatible = "st,stm32-pwm";
 287                                 status = "disabled";
 288                         };
 289                 };
 290
 291                 rtc: rtc@40002800 {
 292                         compatible = "st,stm32-rtc";
 293                         reg = <0x40002800 0x400>;
 294                         clocks = <&rcc 1 CLK_RTC>;
 295                         clock-names = "ck_rtc";
 296                         assigned-clocks = <&rcc 1 CLK_RTC>;
 297                         assigned-clock-parents = <&rcc 1 CLK_LSE>;
 298                         interrupt-parent = <&exti>;
 299                         interrupts = <17 1>;
 300                         interrupt-names = "alarm";
 301                         st,syscfg = <&pwrcfg 0x00 0x100>;
 302                         status = "disabled";
 303                 };
 304
 305                 iwdg: watchdog@40003000 {
 306                         compatible = "st,stm32-iwdg";
 307                         reg = <0x40003000 0x400>;
 308                         clocks = <&clk_lsi>;
 309                         clock-names = "lsi";
 310                         status = "disabled";
 311                 };
 312
 313                 usart2: serial@40004400 {
 314                         compatible = "st,stm32-uart";
 315                         reg = <0x40004400 0x400>;
 316                         interrupts = <38>;
 317                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
 318                         status = "disabled";
 319                 };
 320
 321                 usart3: serial@40004800 {
 322                         compatible = "st,stm32-uart";
 323                         reg = <0x40004800 0x400>;
 324                         interrupts = <39>;
 325                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
 326                         status = "disabled";
 327                         dmas = <&dma1 1 4 0x400 0x0>,
 328                                <&dma1 3 4 0x400 0x0>;
 329                         dma-names = "rx", "tx";
 330                 };
 331
 332                 usart4: serial@40004c00 {
 333                         compatible = "st,stm32-uart";
 334                         reg = <0x40004c00 0x400>;
 335                         interrupts = <52>;
 336                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
 337                         status = "disabled";
 338                 };
 339
 340                 usart5: serial@40005000 {
 341                         compatible = "st,stm32-uart";
 342                         reg = <0x40005000 0x400>;
 343                         interrupts = <53>;
 344                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
 345                         status = "disabled";
 346                 };
 347
 348                 i2c1: i2c@40005400 {
 349                         compatible = "st,stm32f4-i2c";
 350                         reg = <0x40005400 0x400>;
 351                         interrupts = <31>,
 352                                      <32>;
 353                         resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
 354                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
 355                         #address-cells = <1>;
 356                         #size-cells = <0>;
 357                         status = "disabled";
 358                 };
 359
 360                 dac: dac@40007400 {
 361                         compatible = "st,stm32f4-dac-core";
 362                         reg = <0x40007400 0x400>;
 363                         resets = <&rcc STM32F4_APB1_RESET(DAC)>;
 364                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
 365                         clock-names = "pclk";
 366                         #address-cells = <1>;
 367                         #size-cells = <0>;
 368                         status = "disabled";
 369
 370                         dac1: dac@1 {
 371                                 compatible = "st,stm32-dac";
 372                                 #io-channels-cells = <1>;
 373                                 reg = <1>;
 374                                 status = "disabled";
 375                         };
 376
 377                         dac2: dac@2 {
 378                                 compatible = "st,stm32-dac";
 379                                 #io-channels-cells = <1>;
 380                                 reg = <2>;
 381                                 status = "disabled";
 382                         };
 383                 };
 384
 385                 usart7: serial@40007800 {
 386                         compatible = "st,stm32-uart";
 387                         reg = <0x40007800 0x400>;
 388                         interrupts = <82>;
 389                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
 390                         status = "disabled";
 391                 };
 392
 393                 usart8: serial@40007c00 {
 394                         compatible = "st,stm32-uart";
 395                         reg = <0x40007c00 0x400>;
 396                         interrupts = <83>;
 397                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
 398                         status = "disabled";
 399                 };
 400
 401                 timers1: timers@40010000 {
 402                         #address-cells = <1>;
 403                         #size-cells = <0>;
 404                         compatible = "st,stm32-timers";
 405                         reg = <0x40010000 0x400>;
 406                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
 407                         clock-names = "int";
 408                         status = "disabled";
 409
 410                         pwm {
 411                                 compatible = "st,stm32-pwm";
 412                                 status = "disabled";
 413                         };
 414
 415                         timer@0 {
 416                                 compatible = "st,stm32-timer-trigger";
 417                                 reg = <0>;
 418                                 status = "disabled";
 419                         };
 420                 };
 421
 422                 timers8: timers@40010400 {
 423                         #address-cells = <1>;
 424                         #size-cells = <0>;
 425                         compatible = "st,stm32-timers";
 426                         reg = <0x40010400 0x400>;
 427                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
 428                         clock-names = "int";
 429                         status = "disabled";
 430
 431                         pwm {
 432                                 compatible = "st,stm32-pwm";
 433                                 status = "disabled";
 434                         };
 435
 436                         timer@7 {
 437                                 compatible = "st,stm32-timer-trigger";
 438                                 reg = <7>;
 439                                 status = "disabled";
 440                         };
 441                 };
 442
 443                 usart1: serial@40011000 {
 444                         compatible = "st,stm32-uart";
 445                         reg = <0x40011000 0x400>;
 446                         interrupts = <37>;
 447                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
 448                         status = "disabled";
 449                         dmas = <&dma2 2 4 0x400 0x0>,
 450                                <&dma2 7 4 0x400 0x0>;
 451                         dma-names = "rx", "tx";
 452                 };
 453
 454                 usart6: serial@40011400 {
 455                         compatible = "st,stm32-uart";
 456                         reg = <0x40011400 0x400>;
 457                         interrupts = <71>;
 458                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
 459                         status = "disabled";
 460                 };
 461
 462                 adc: adc@40012000 {
 463                         compatible = "st,stm32f4-adc-core";
 464                         reg = <0x40012000 0x400>;
 465                         interrupts = <18>;
 466                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
 467                         clock-names = "adc";
 468                         interrupt-controller;
 469                         #interrupt-cells = <1>;
 470                         #address-cells = <1>;
 471                         #size-cells = <0>;
 472                         status = "disabled";
 473
 474                         adc1: adc@0 {
 475                                 compatible = "st,stm32f4-adc";
 476                                 #io-channel-cells = <1>;
 477                                 reg = <0x0>;
 478                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
 479                                 interrupt-parent = <&adc>;
 480                                 interrupts = <0>;
 481                                 dmas = <&dma2 0 0 0x400 0x0>;
 482                                 dma-names = "rx";
 483                                 status = "disabled";
 484                         };
 485
 486                         adc2: adc@100 {
 487                                 compatible = "st,stm32f4-adc";
 488                                 #io-channel-cells = <1>;
 489                                 reg = <0x100>;
 490                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
 491                                 interrupt-parent = <&adc>;
 492                                 interrupts = <1>;
 493                                 dmas = <&dma2 3 1 0x400 0x0>;
 494                                 dma-names = "rx";
 495                                 status = "disabled";
 496                         };
 497
 498                         adc3: adc@200 {
 499                                 compatible = "st,stm32f4-adc";
 500                                 #io-channel-cells = <1>;
 501                                 reg = <0x200>;
 502                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
 503                                 interrupt-parent = <&adc>;
 504                                 interrupts = <2>;
 505                                 dmas = <&dma2 1 2 0x400 0x0>;
 506                                 dma-names = "rx";
 507                                 status = "disabled";
 508                         };
 509                 };
 510
 511                 sdio: sdio@40012c00 {
 512                         compatible = "arm,pl180", "arm,primecell";
 513                         arm,primecell-periphid = <0x00880180>;
 514                         reg = <0x40012c00 0x400>;
 515                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
 516                         clock-names = "apb_pclk";
 517                         interrupts = <49>;
 518                         max-frequency = <48000000>;
 519                         status = "disabled";
 520                 };
 521
 522                 syscfg: system-config@40013800 {
 523                         compatible = "syscon";
 524                         reg = <0x40013800 0x400>;
 525                 };
 526
 527                 exti: interrupt-controller@40013c00 {
 528                         compatible = "st,stm32-exti";
 529                         interrupt-controller;
 530                         #interrupt-cells = <2>;
 531                         reg = <0x40013C00 0x400>;
 532                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
 533                 };
 534
 535                 timers9: timers@40014000 {
 536                         #address-cells = <1>;
 537                         #size-cells = <0>;
 538                         compatible = "st,stm32-timers";
 539                         reg = <0x40014000 0x400>;
 540                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
 541                         clock-names = "int";
 542                         status = "disabled";
 543
 544                         pwm {
 545                                 compatible = "st,stm32-pwm";
 546                                 status = "disabled";
 547                         };
 548
 549                         timer@8 {
 550                                 compatible = "st,stm32-timer-trigger";
 551                                 reg = <8>;
 552                                 status = "disabled";
 553                         };
 554                 };
 555
 556                 timers10: timers@40014400 {
 557                         compatible = "st,stm32-timers";
 558                         reg = <0x40014400 0x400>;
 559                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
 560                         clock-names = "int";
 561                         status = "disabled";
 562
 563                         pwm {
 564                                 compatible = "st,stm32-pwm";
 565                                 status = "disabled";
 566                         };
 567                 };
 568
 569                 timers11: timers@40014800 {
 570                         compatible = "st,stm32-timers";
 571                         reg = <0x40014800 0x400>;
 572                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
 573                         clock-names = "int";
 574                         status = "disabled";
 575
 576                         pwm {
 577                                 compatible = "st,stm32-pwm";
 578                                 status = "disabled";
 579                         };
 580                 };
 581
 582                 pwrcfg: power-config@40007000 {
 583                         compatible = "syscon";
 584                         reg = <0x40007000 0x400>;
 585                 };
 586
 587                 ltdc: display-controller@40016800 {
 588                         compatible = "st,stm32-ltdc";
 589                         reg = <0x40016800 0x200>;
 590                         interrupts = <88>, <89>;
 591                         resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
 592                         clocks = <&rcc 1 CLK_LCD>;
 593                         clock-names = "lcd";
 594                         status = "disabled";
 595                 };
 596
 597                 crc: crc@40023000 {
 598                         compatible = "st,stm32f4-crc";
 599                         reg = <0x40023000 0x400>;
 600                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
 601                         status = "disabled";
 602                 };
 603
 604                 rcc: rcc@40023800 {
 605                         #reset-cells = <1>;
 606                         #clock-cells = <2>;
 607                         compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
 608                         reg = <0x40023800 0x400>;
 609                         clocks = <&clk_hse>, <&clk_i2s_ckin>;
 610                         st,syscfg = <&pwrcfg>;
 611                         assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
 612                         assigned-clock-rates = <1000000>;
 613                 };
 614
 615                 dma1: dma-controller@40026000 {
 616                         compatible = "st,stm32-dma";
 617                         reg = <0x40026000 0x400>;
 618                         interrupts = <11>,
 619                                      <12>,
 620                                      <13>,
 621                                      <14>,
 622                                      <15>,
 623                                      <16>,
 624                                      <17>,
 625                                      <47>;
 626                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
 627                         #dma-cells = <4>;
 628                 };
 629
 630                 dma2: dma-controller@40026400 {
 631                         compatible = "st,stm32-dma";
 632                         reg = <0x40026400 0x400>;
 633                         interrupts = <56>,
 634                                      <57>,
 635                                      <58>,
 636                                      <59>,
 637                                      <60>,
 638                                      <68>,
 639                                      <69>,
 640                                      <70>;
 641                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
 642                         #dma-cells = <4>;
 643                         st,mem2mem;
 644                 };
 645
 646                 mac: ethernet@40028000 {
 647                         compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
 648                         reg = <0x40028000 0x8000>;
 649                         reg-names = "stmmaceth";
 650                         interrupts = <61>;
 651                         interrupt-names = "macirq";
 652                         clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
 653                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
 654                                         <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
 655                                         <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
 656                         st,syscon = <&syscfg 0x4>;
 657                         snps,pbl = <8>;
 658                         snps,mixed-burst;
 659                         status = "disabled";
 660                 };
 661
 662                 usbotg_hs: usb@40040000 {
 663                         compatible = "snps,dwc2";
 664                         reg = <0x40040000 0x40000>;
 665                         interrupts = <77>;
 666                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
 667                         clock-names = "otg";
 668                         status = "disabled";
 669                 };
 670
 671                 usbotg_fs: usb@50000000 {
 672                         compatible = "st,stm32f4x9-fsotg";
 673                         reg = <0x50000000 0x40000>;
 674                         interrupts = <67>;
 675                         clocks = <&rcc 0 39>;
 676                         clock-names = "otg";
 677                         status = "disabled";
 678                 };
 679
 680                 dcmi: dcmi@50050000 {
 681                         compatible = "st,stm32-dcmi";
 682                         reg = <0x50050000 0x400>;
 683                         interrupts = <78>;
 684                         resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
 685                         clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
 686                         clock-names = "mclk";
 687                         pinctrl-names = "default";
 688                         pinctrl-0 = <&dcmi_pins>;
 689                         dmas = <&dma2 1 1 0x414 0x3>;
 690                         dma-names = "tx";
 691                         status = "disabled";
 692                 };
 693
 694                 rng: rng@50060800 {
 695                         compatible = "st,stm32-rng";
 696                         reg = <0x50060800 0x400>;
 697                         interrupts = <80>;
 698                         clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
 699
 700                 };
 701         };
 702 };
 703
 704 &systick {
 705         clocks = <&rcc 1 SYSTICK>;
 706         status = "okay";
 707 };